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2022-07-05ARM: dts: lan966x: Add UDPHS supportHerve Codina
Add UDPHS (the USB High Speed Device Port controller) support. The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS IP. This IP is also the same as the one present in the SAMA5D3 SOC. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704102845.168438-4-herve.codina@bootlin.com
2022-07-05dt-bindings: usb: atmel: Add Microchip LAN9662 compatible stringHerve Codina
The USB device controller available in the Microchip LAN9662 SOC is the same IP as the one present in the SAMA5D3 SOC. Add the LAN9662 compatible string and set the SAMA5D3 compatible string as a fallback for the LAN9662. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704102845.168438-3-herve.codina@bootlin.com
2022-07-05ARM: dts: stm32: add optee reserved memory on stm32mp135f-dkGabriel Fernandez
Add the static OP-TEE reserved memory regions. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: add RCC on STM32MP13x SoC familyGabriel Fernandez
Enables Reset and Clocks Controller on STM32MP13 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13Gabriel Fernandez
Enable optee and SCMI clocks support. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05dt-bindings: rcc: stm32: select the "secure" path for stm32mp13Alexandre Torgue
Like for stm32mp15, when stm32 RCC node is used to interact with a secure context (using clock SCMI protocol), a different path has to be used for yaml verification. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Rob Herring <robh@kernel.org>
2022-07-05ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32Leonard Göhrs
According to the OSD32MP1 Power System overview[1] the EEPROM is connected to the VDD line and not to some single-purpose fixed regulator. Set the EEPROM supply according to the diagram to eliminate this parent-less regulator. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1Leonard Göhrs
According to the OSD32MP1 Power System overview[1] ldo3's input is always internally connected to vdd_ddr. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: adjust whitespace around '=' on MCU boardsKrzysztof Kozlowski
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSIMarek Vasut
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151Fabien Dessenne
The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so remove the unsupported "wakeup" one. Note that the EXTI interrupt 61 has two roles : it is hierarchically linked to the GIC IPCC "rx" interrupt, and it acts as a wakeup source. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.Kavyasree Kotagiri
On pcb8291, Flexcom3 usart has only tx and rx pins. Cleaningup usart3 pinctrl settings. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704135809.6952-1-kavyasree.kotagiri@microchip.com
2022-07-05arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort orderGeert Uytterhoeven
The scif0 nodes were accidentally inserted after the scif3 nodes, breaking alphabetical sort order. Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2fe0e782351c202ed009dcd658f4bceec8f3a56d.1656951240.git.geert+renesas@glider.be
2022-07-04arm64: dts: qcom: msm8996: Add interconnect supportYassine Oudjana
Add interconnect providers for the multiple NoCs available on the platform, and assign interconnects used by some blocks. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211021132329.234942-6-y.oudjana@protonmail.com
2022-07-05arm64: dts: Add SFP node for TA 3.0 devicesSean Anderson
This adds an SFP node for Trust Architecture 3.0 devices. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-05arm64: dts: layerscape: Add SFP node for TA 2.1 devicesSean Anderson
This adds an appropriate SFP node for Trust Architecture 2.1 devices. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-05ARM: dts: layerscape: Add SFP node for TA 2.1 devicesSean Anderson
This adds an appropriate SFP node for Trust Architecture 2.1 devices. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-05ARM: dts: ux500: Drop unused i2c power domain supplyLinus Walleij
This regulator supply is replaced by the proper power domain. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220701225339.814962-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-07-04arm64: dts: allwinner: a64: orangepi-win: Fix LED node nameSamuel Holland
"status" does not match any pattern in the gpio-leds binding. Rename the node to the preferred pattern. This fixes a `make dtbs_check` error. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220702132816.46456-1-samuel@sholland.org
2022-07-04arm64: dts: rockchip: enable hdmi tx audio on rock-3aMichael Riesch
Enable the I2S0 controller and the hdmi-sound node on the Radxa ROCK3 Model A. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220614230354.3756364-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-07-04arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10Michael Riesch
Enable the I2S0 controller and the hdmi-sound node on the Rockchip RK3568 EVB1. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220614230354.3756364-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-07-04Merge tag 'omap-for-v5.20/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes omaps for v5.20 merge window Just one devicetree change to add EEPROM regulator for BeagleBone Black. * tag 'omap-for-v5.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am33xx: Map baseboard EEPROM on BeagleBone Black Link: https://lore.kernel.org/r/pull-1656918942-515224@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-04ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15Fabrice Gasnier
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be initialized first, before enabling (gating) them. The reverse is also required when going to suspend. So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL gets enabled 1st upon controller init. Upon suspend/resume, this also makes the clock to be disabled/re-enabled in the correct order. This fixes some IRQ storm conditions seen when going to low-power, due to PHY PLL being disabled before all clocks are cleanly gated. Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMIGabriel Fernandez
Delete the node fixed clock managed by secure world with SCMI. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 boardGabriel Fernandez
LSE clock is provided by SCMI. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: use the correct clock source for CEC on stm32mp151Gabriel Fernandez
The peripheral clock of CEC is not LSE but CEC. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: stm32: fix pwr regulators references to use scmiEtienne Carriere
Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR regulators through SCMI service. This is needed since enabling secure only access to RCC clock and reset controllers also enables secure access only on PWR voltage regulators reg11, reg18 and usb33 hence these must also be accessed through SCMI Voltage Domain protocol. This change applies on commit [2] that already corrects issues from commit [1]. Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-04ARM: dts: lan966x: Add mcan1 node.Kavyasree Kotagiri
Add the mcan1 node. By default, keep it disabled. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220627110552.26315-1-kavyasree.kotagiri@microchip.com
2022-07-04ARM: dts: at91: sama7g5: add reset-controller nodeClaudiu Beznea
Add reset controller node. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220610092414.1816571-10-claudiu.beznea@microchip.com
2022-07-04ARM: dts: at91: use generic name for reset controllerClaudiu Beznea
Use generic name for reset controller of AT91 devices to comply with DT specifications. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
2022-07-04ARM: dts: at91: sama5d2: fix compilation warningClaudiu Beznea
Fix the following compilation warning: arch/arm/boot/dts/sama5d2.dtsi:371.29-382.6: Warning (avoid_unnecessary_addr_size): /ahb/apb/ethernet@f8008000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property also defined at arch/arm/boot/dts/at91-sama5d2_icp.dts:353.8-363.3 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220615080633.1881196-2-claudiu.beznea@microchip.com
2022-07-04ARM: dts: at91: sama5d2: fix compilation warningClaudiu Beznea
Fix the following compilation warning: Warning (simple_bus_reg): /ahb/apb/resistive-touch: missing or empty reg/ranges property Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220615080633.1881196-1-claudiu.beznea@microchip.com
2022-07-02ARM: dts: qcom: Fix sdhci node names - use 'mmc@'Bhupesh Sharma
Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'sdhci@' convention used for specifying the sdhci nodes. The generic mmc bindings expect 'mmc@' format instead. Fix the same. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> [bjorn: Extracted from combined arm64 patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
2022-07-02Merge tag 'qcom-arm64-fixes-for-5.19' into arm64-for-5.20Bjorn Andersson
This merges the 'qcom-arm64-fixes-for-5.19' tag into arm64-for-5.20 to handle the merge conflict related to the header file changes in sc7180-trogdor.
2022-07-02arm64: dts: qcom: sc7180-trogdor: Split out keyboard node and describe ↵Stephen Boyd
detachables Trogdor devices that have a detachable keyboard still have a non-detachable keyboard input device present because we include the cros-ec-keyboard.dtsi snippet in the top-level sc7180-trogdor.dtsi file that every variant board includes. We do this because the keyboard-controller node also provides some buttons like the power button and volume buttons. Unfortunately, this means we register a keyboard input device that doesn't do anything on boards with a detachable keyboard. Change the node's compatible on detachables to the newly introduced "google,cros-ec-keyb-switches" compatible to indicate that there are only switches and no keyboard to register. Similarly, move the keyboard include that defines the keyboard-controller node out of sc7180-trogdor.dtsi to boards that actually have a keyboard so that the matrix properties are not defined on boards with the switches compatible. Future boards can either use the include approach or the node definition approach to describe a keyboard with possible switches or just some switches. Cc: Benson Leung <bleung@chromium.org> Cc: Guenter Roeck <groeck@chromium.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Hsin-Yi Wang <hsinyi@chromium.org> Cc: "Joseph S. Barrera III" <joebar@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220627212802.3593012-1-swboyd@chromium.org
2022-07-02arm64: dts: qcom: ipq8074: fix NAND node nameRobert Marko
Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220621120642.518575-1-robimarko@gmail.com
2022-07-02arm64: dts: qcom: msm8916: add xo clocks to rpmcc and a53pllDmitry Baryshkov
Both a53pll and rpmcc make use of xo as a clock parent. Add it to the respective device nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220620010519.1533364-1-dmitry.baryshkov@linaro.org
2022-07-02arm64: dts: qcom: msm8996: add second DSI interfaceDmitry Baryshkov
Add device nodes for the DSI1, second DSI interface found on MSM8996/APQ8096 platforms. For example on db820c it is routed to the secondary HS expansion connector. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220617103652.606250-1-dmitry.baryshkov@linaro.org
2022-07-02arm64: dts: qcom: add mdp_clk clock to the MDSS deviceDmitry Baryshkov
Add MDP_CLK ("core") clock to the mdss device to allow MDSS driver to access HW_REV/etc registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220615135935.87381-5-dmitry.baryshkov@linaro.org
2022-07-02arm64: dts: qcom: sm8250: Enable per-process page tables.Emma Anholt
This is an SMMU for the adreno gpu, and adding this compatible lets the driver use per-fd page tables, which are required for security between GPU clients. Signed-off-by: Emma Anholt <emma@anholt.net> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Move arm,smmu-500 last, per Dmitry's request] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220614230136.3726047-2-emma@anholt.net
2022-07-02arm64: dts: qcom: msm8916-samsung-a2015: Add touchscreen pinctrlLin, Meng-Bo
A3, A5 and most of the Samsung phones with MSM8916 SoC use GPIO pin 13 for touchscreen interrupts. Add touchscreen pinctrl to a2015 common dtsi. Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220610175332.104154-1-linmengbo0689@protonmail.com
2022-07-02arm64: dts: qcom: msm8996: drop phy-names from HDMI device nodeDmitry Baryshkov
The HDMI driver doesn't use the phy-names to identify the PHY. Different Qualcomm platforms have used different names for the PHY. So, we are deprecating phy-names propertty of the HDMI device and dropping them from existing DTs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220609122350.3157529-15-dmitry.baryshkov@linaro.org
2022-07-02arm64: dts: qcom: msm8994: add required ranges to OCMEMKrzysztof Kozlowski
The OCMEM bindings require ranges property. Fixes: 9d511d0a7926 ("arm64: dts: qcom: msm8994: Add OCMEM node") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-14-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: sdm845: add dedicated IMEM and syscon compatiblesKrzysztof Kozlowski
Add proper compatibles to the IMEM device node: 1. syscon to allow accessing memory from other devices, 2. dedicated compatible as required for syscon and simple-mfd nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-13-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: sdm630: add dedicated IMEM and syscon compatiblesKrzysztof Kozlowski
Add proper compatibles to the IMEM device node: 1. syscon to allow accessing memory from other devices, 2. dedicated compatible as required for syscon and simple-mfd nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-12-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: sc7280: add simple-mfd to IMEMKrzysztof Kozlowski
The IMEM node has children (PIL) which should be instantiated with simple-mfd. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-11-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: sc7180: add dedicated IMEM and syscon compatiblesKrzysztof Kozlowski
Add proper compatibles to the IMEM device node: 1. syscon to allow accessing memory from other devices, 2. dedicated compatible as required for syscon and simple-mfd nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-10-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: qcs404: add dedicated IMEM and syscon compatiblesKrzysztof Kozlowski
Add proper compatibles to the IMEM device node: 1. syscon to allow accessing memory from other devices, 2. dedicated compatible as required for syscon and simple-mfd nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-9-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: use generic sram as name for imem and ocmem nodesKrzysztof Kozlowski
According to Devicetree specification, the device nodes should be generic, reflecting the function of the device. The typical name for memory regions is "sram". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607171848.535128-8-krzysztof.kozlowski@linaro.org
2022-07-02arm64: dts: qcom: sdm845-db845c: add function and color to LED nodesKrzysztof Kozlowski
Add common LED properties - the function and color - to LED nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220607102931.102805-10-krzysztof.kozlowski@linaro.org
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