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2013-08-30drm/radeon/dpm: implement force performance level for KB/KVAlex Deucher
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: add debugfs support for KB/KVAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: implement vblank_too_short callback for CIAlex Deucher
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: implement force performance level for CIAlex Deucher
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: add debugfs support for CIAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add dpm support for CI dGPUs (v2)Alex Deucher
This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/kms: add dpm support for KB/KVAlex Deucher
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: add helper to fetch the vrefresh of the current modeAlex Deucher
Needed for DPM on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: add a helper to encode pcie lane settingAlex Deucher
convert from number of lanes to register setting. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: add vce clocks to radeon_psAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add r600_get_pcie_lane_support helperAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: parse the acp clock voltage deps tableAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: parse the samu clock voltage deps tableAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: clean up the extended table error pathesAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: parse the uvd clock voltage deps tableAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: parse the vce clock voltage deps tableAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add clock voltage dep tables for acp, samuAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add structs to store vce clock voltage depsAlex Deucher
Used for vce power management. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: grab mvdd_dependency_on_mclk info from vbiosAlex Deucher
Required for dpm on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: add support for parsing the atom powertune tableAlex Deucher
Needed for DPM on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: update cac leakage table parsing for CIAlex Deucher
Uses a different table format if the board supports EVV. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: adjust si_dpm function for code sharingAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add get_temperature() callbacks for CIK (v2)Alex Deucher
This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add KB/KV to r600_is_internal_thermal_sensorAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add CI to r600_is_internal_thermal_sensor()Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add support for thermal controller on KB/KVAlex Deucher
No support for reading temperature back yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/cik: add rlc helpers for DPMAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add structs to store uvd clock voltage depsAlex Deucher
Used for uvd power management. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: switch to pptable.hAlex Deucher
Internally we switched to using a separate header for atombios pplib definitions. Switch over the open source driver. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/sumo add helper to go from vid7 to vid2Alex Deucher
Needed for DPM on KB/KV. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add indirect accessors for dift registers on CIKAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: convert SI,CIK to use sumo_rlc functionsAlex Deucher
and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: clean up sumo_rlc_init() for code sharingAlex Deucher
This will eventually be shared with newer asics to reduce code duplication. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/cik: restructure rlc setupAlex Deucher
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add support for ASPM on CIK asicsAlex Deucher
Enables PCIE ASPM (Active State Power Management) on CIK asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/cik: add support for pcie gen1/2/3 switchingAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: switch CIK to use radeon_ucode.hAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/cik: implement some more atom helpers for DPMAlex Deucher
Required for DPM on CIK. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/kms: fix up dce8 display watermark calc for dpmAlex Deucher
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: use performance state if no UVD stateAlex Deucher
Newer asics don't have specific UVD states. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: default to 1024M gart size on rv770+Alex Deucher
Newer asics have a lot of vram so it's less of an issue to waste a little more space for the gart page table. This gives us some additional gart space before having to migrate to non-gart system ram for games, etc. where we use up most of vram. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: rework thermal state handlingAlex Deucher
1. Handle the the thermal state directly in the work handler. Remove the state selection function since nothing else uses it now. 2. On some asics there is no thermal state, so we just use a regular state and force the low performance state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/dpm: use multiple UVD power states (v3)Alex Deucher
Use the UVD handle information to determine which which power states to select when using UVD. For example, decoding a single SD stream requires much lower clocks than multiple HD streams. v2: switch to a cleaner dpm/uvd interface v3: change the uvd power state while streams are active if need be Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: add UVD->DPM helper function (v5)Alex Deucher
Add a helper function for counting the number of open stream handles. v2: fix copy-pasta in comments and whitespace error v3: make function static since it's only used in radeon_uvd.c at the moment v4: make non-static again for future changes v5: make static again for new rework of dpm uvd changes Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon/kms: remove r6xx+ blit copy routinesAlex Deucher
No longer used now that we use the async dma engines or CP DMA for bo copies. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: switch r6xx+ to using CP DMA for the blit copy callbackAlex Deucher
CP DMA is lighter weight than using the 3D engine. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/edid: add quirk for Medion MD30217PGAlex Deucher
This LCD monitor (1280x1024 native) has a completely bogus detailed timing (640x350@70hz). User reports that 1280x1024@60 has waves so prefer 1280x1024@75. Manufacturer: MED Model: 7b8 Serial#: 99188 Year: 2005 Week: 5 EDID Version: 1.3 Analog Display Input, Input Voltage Level: 0.700/0.700 V Sync: Separate Max Image Size [cm]: horiz.: 34 vert.: 27 Gamma: 2.50 DPMS capabilities: Off; RGB/Color Display First detailed timing is preferred mode redX: 0.645 redY: 0.348 greenX: 0.280 greenY: 0.605 blueX: 0.142 blueY: 0.071 whiteX: 0.313 whiteY: 0.329 Supported established timings: 720x400@70Hz 640x480@60Hz 640x480@72Hz 640x480@75Hz 800x600@56Hz 800x600@60Hz 800x600@72Hz 800x600@75Hz 1024x768@60Hz 1024x768@70Hz 1024x768@75Hz 1280x1024@75Hz Manufacturer's mask: 0 Supported standard timings: Supported detailed timing: clock: 25.2 MHz Image Size: 337 x 270 mm h_active: 640 h_sync: 688 h_sync_end 784 h_blank_end 800 h_border: 0 v_active: 350 v_sync: 350 v_sync_end 352 v_blanking: 449 v_border: 0 Monitor name: MD30217PG Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz Serial No: 501099188 EDID (in hex): 00ffffffffffff0034a4b80774830100 050f010368221b962a0c55a559479b24 125054afcf00310a0101010101018180 000000000000d60980a0205e63103060 0200510e1100001e000000fc004d4433 3032313750470a202020000000fd0038 4c1e530e000a202020202020000000ff 003530313039393138380a2020200078 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reported-by: friedrich@mailstation.de Cc: stable@vger.kernel.org
2013-08-30tipc: set sk_err correctly when connection failsErik Hugne
Should a connect fail, if the publication/server is unavailable or due to some other error, a positive value will be returned and errno is never set. If the application code checks for an explicit zero return from connect (success) or a negative return (failure), it will not catch the error and subsequent send() calls will fail as shown from the strace snippet below. socket(0x1e /* PF_??? */, SOCK_SEQPACKET, 0) = 3 connect(3, {sa_family=0x1e /* AF_??? */, sa_data="\2\1\322\4\0\0\322\4\0\0\0\0\0\0"}, 16) = 111 sendto(3, "test", 4, 0, NULL, 0) = -1 EPIPE (Broken pipe) The reason for this behaviour is that TIPC wrongly inverts error codes set in sk_err. Signed-off-by: Erik Hugne <erik.hugne@ericsson.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-08-30tcp: tcp_make_synack() should use sock_wmallocPhil Oester
In commit 90ba9b19 (tcp: tcp_make_synack() can use alloc_skb()), Eric changed the call to sock_wmalloc in tcp_make_synack to alloc_skb. In doing so, the netfilter owner match lost its ability to block the SYNACK packet on outbound listening sockets. Revert the change, restoring the owner match functionality. This closes netfilter bugzilla #847. Signed-off-by: Phil Oester <kernel@linuxace.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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