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2022-07-05dmaengine: idxd: Only call idxd_enable_system_pasid() if succeeded in ↵Jerry Snitselaar
enabling SVA feature On a Sapphire Rapids system if boot without intel_iommu=on, the IDXD driver will crash during probe in iommu_sva_bind_device(). [ 21.423729] BUG: kernel NULL pointer dereference, address: 0000000000000038 [ 21.445108] #PF: supervisor read access in kernel mode [ 21.450912] #PF: error_code(0x0000) - not-present page [ 21.456706] PGD 0 [ 21.459047] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 21.464004] CPU: 0 PID: 1420 Comm: kworker/0:3 Not tainted 5.19.0-0.rc3.27.eln120.x86_64 #1 [ 21.464011] Hardware name: Intel Corporation EAGLESTREAM/EAGLESTREAM, BIOS EGSDCRB1.SYS.0067.D12.2110190954 10/19/2021 [ 21.464015] Workqueue: events work_for_cpu_fn [ 21.464030] RIP: 0010:iommu_sva_bind_device+0x1d/0xe0 [ 21.464046] Code: c3 cc 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 57 41 56 49 89 d6 41 55 41 54 55 53 48 83 ec 08 48 8b 87 d8 02 00 00 <48> 8b 40 38 48 8b 50 10 48 83 7a 70 00 48 89 14 24 0f 84 91 00 00 [ 21.464050] RSP: 0018:ff7245d9096b7db8 EFLAGS: 00010296 [ 21.464054] RAX: 0000000000000000 RBX: ff1eadeec8a51000 RCX: 0000000000000000 [ 21.464058] RDX: ff7245d9096b7e24 RSI: 0000000000000000 RDI: ff1eadeec8a510d0 [ 21.464060] RBP: ff1eadeec8a51000 R08: ffffffffb1a12300 R09: ff1eadffbfce25b4 [ 21.464062] R10: ffffffffffffffff R11: 0000000000000038 R12: ffffffffc09f8000 [ 21.464065] R13: ff1eadeec8a510d0 R14: ff7245d9096b7e24 R15: ff1eaddf54429000 [ 21.464067] FS: 0000000000000000(0000) GS:ff1eadee7f600000(0000) knlGS:0000000000000000 [ 21.464070] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 21.464072] CR2: 0000000000000038 CR3: 00000008c0e10006 CR4: 0000000000771ef0 [ 21.464074] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 21.464076] DR3: 0000000000000000 DR6: 00000000fffe07f0 DR7: 0000000000000400 [ 21.464078] PKRU: 55555554 [ 21.464079] Call Trace: [ 21.464083] <TASK> [ 21.464092] idxd_pci_probe+0x259/0x1070 [idxd] [ 21.464121] local_pci_probe+0x3e/0x80 [ 21.464132] work_for_cpu_fn+0x13/0x20 [ 21.464136] process_one_work+0x1c4/0x380 [ 21.464143] worker_thread+0x1ab/0x380 [ 21.464147] ? _raw_spin_lock_irqsave+0x23/0x50 [ 21.464158] ? process_one_work+0x380/0x380 [ 21.464161] kthread+0xe6/0x110 [ 21.464168] ? kthread_complete_and_exit+0x20/0x20 [ 21.464172] ret_from_fork+0x1f/0x30 iommu_sva_bind_device() requires SVA has been enabled successfully on the IDXD device before it's called. Otherwise, iommu_sva_bind_device() will access a NULL pointer. If Intel IOMMU is disabled, SVA cannot be enabled and thus idxd_enable_system_pasid() and iommu_sva_bind_device() should not be called. Fixes: 42a1b73852c4 ("dmaengine: idxd: Separate user and kernel pasid enabling") Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: Dave Jiang <dave.jiang@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/dmaengine/20220623170232.6whonfjuh3m5vcoy@cantor/ Signed-off-by: Jerry Snitselaar <jsnitsel@redhat.com> Acked-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20220626051648.14249-1-jsnitsel@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05dmaengine: at_xdma: handle errors of at_xdmac_alloc_desc() correctlyMichael Walle
It seems that it is valid to have less than the requested number of descriptors. But what is not valid and leads to subsequent errors is to have zero descriptors. In that case, abort the probing. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220526135111.1470926-1-michael@walle.cc Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05arm64: mm: Remove assembly DMA cache maintenance wrappersWill Deacon
Remove the __dma_{flush,map,unmap}_area assembly wrappers and call the appropriate cache maintenance functions directly from the DMA mapping callbacks. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20220610151228.4562-3-will@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05regmap-irq: Fix bug in regmap_irq_get_irq_reg_linear()Aidan MacDonald
irq_reg_stride in struct regmap_irq_chip is often 0, but that actually means to use the default stride of 1. The effective stride is stored in struct regmap_irq_chip_data->irq_reg_stride and will get the corrected default value. The default ->get_irq_reg() callback was using the stride from the chip definition, which is wrong; fix it to use the effective stride from the chip data instead. Link: https://lore.kernel.org/lkml/acaaf77f-3282-8544-dd3c-7915fc1a6a4f@samsung.com/ Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220704112847.23844-1-aidanmacdonald.0x0@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-05Merge branch 'for-v5.20/aspeed-dts-cleanup' into for-v5.20/dts-cleanupKrzysztof Kozlowski
2022-07-05ARM: dts: aspeed: correct gpio-keys propertiesKrzysztof Kozlowski
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-37-krzysztof.kozlowski@linaro.org
2022-07-05ARM: dts: aspeed: align gpio-key node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-36-krzysztof.kozlowski@linaro.org
2022-07-05arm64: errata: Add Cortex-A510 to the repeat tlbi listJames Morse
Cortex-A510 is affected by an erratum where in rare circumstances the CPUs may not handle a race between a break-before-make sequence on one CPU, and another CPU accessing the same page. This could allow a store to a page that has been unmapped. Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice. Signed-off-by: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generationMark Brown
Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generationMark Brown
Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-28-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORID_EL1 to automatic generationMark Brown
Convert LORID_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-27-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORC_EL1 to automatic generationMark Brown
Convert LORC_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-26-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORN_EL1 to automatic generationMark Brown
Convert LORN_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-25-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LOREA_EL1 to automatic generationMark Brown
Convert LOREA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-24-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert LORSA_EL1 to automatic generationMark Brown
Convert LORSA_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-23-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generationMark Brown
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-22-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generationMark Brown
Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-21-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert GMID to automatic generationMark Brown
Automatically generate the register definitions for GMID as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-20-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert DCZID_EL0 to automatic generationMark Brown
Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-19-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Convert CTR_EL0 to automatic generationMark Brown
Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-18-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition namesMark Brown
Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR2_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-17-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition namesMark Brown
Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR1_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-16-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Remove defines for RPRES enumerationMark Brown
We have defines for the RPRES enumeration in ID_AA64ISAR2 which do not follow our normal conventions. Since these defines are never used just remove them. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-15-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fieldsMark Brown
The various defines for bitfields in ID_AA64ZFR0_EL1 do not follow our conventions for register field names, they omit the _EL1, they don't use specific defines for enumeration values and they don't follow the naming in the architecture in some cases. In preparation for automatic generation bring them into line with convention. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-14-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enumsMark Brown
We have a series of defines for enumeration values we test for in the fields in ID_AA64SMFR0_EL1 which do not follow our usual convention of including the EL1 in the name and having _IMP at the end of the basic "feature present" define. In preparation for automatic register generation bring the defines into sync with convention, no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-13-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for WFxT definesMark Brown
The defines for WFxT refer to the feature as WFXT and use SUPPORTED rather than IMP. In preparation for automatic generation of defines update these to be more standard. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-12-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Make BHB clear feature defines match the architectureMark Brown
The architecture refers to the field identifying support for BHB clear as BC but the kernel has called it CLEARBHB. In preparation for generation of defines for ID_AA64ISAR2_EL1 rename to use the architecture's naming. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-11-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Align pointer auth enumeration defines with architectureMark Brown
The defines used for the pointer authentication feature enumerations do not follow the naming convention we've decided to use where we name things after the architecture feature that introduced. Prepare for generating the defines for the ISA ID registers by updating to use the feature names. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-10-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/mte: Standardise GMID field name definitionsMark Brown
Usually our defines for bitfields in system registers do not include a SYS_ prefix but those for GMID do. In preparation for automatic generation of defines remove that prefix. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-9-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for DCZID_EL0 field namesMark Brown
The constants defining field names for DCZID_EL0 do not include the _EL0 that is included as part of our standard naming scheme. In preparation for automatic generation of the defines add the _EL0 in. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-8-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Standardise naming for CTR_EL0 fieldsMark Brown
cache.h contains some defines which are used to represent fields and enumeration values which do not follow the standard naming convention used for when we automatically generate defines for system registers. Update the names of the constants to reflect standardised naming and move them to sysreg.h. There is also a helper CTR_L1IP() which was open coded and has been converted to use SYS_FIELD_GET(). Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-7-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/cache: Restrict which headers are included in __ASSEMBLY__Mark Brown
Future changes to generate register definitions automatically will cause this header to be included in a linker script. This will mean that headers it in turn includes that are not safe for use in such a context (eg, due to the use of assembler macros) cause build problems. Avoid these issues by moving the affected includes and associated defines to the section of the file already guarded by ifndef __ASSEMBLY__. Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-6-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Add SYS_FIELD_GET() helperMark Brown
Add a SYS_FIELD_GET() helper to match SYS_FIELD_PREP(), providing a simplified interface to FIELD_GET() when using the generated defines with standardized naming. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220704170302.2609529-5-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/sysreg: Allow leading blanks on comments in sysreg fileMark Brown
Currently we only accept comments where the # is placed at the start of a line, allow leading blanks so we can format comments inside definitions in a more pleasing manner. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-4-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/idreg: Fix tab/space damageMark Brown
Quite a few of the overrides in idreg-override.c have a mix of tabs and spaces in their definitions, fix these. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-3-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/cpuinfo: Remove references to reserved cache typeMark Brown
In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT I-caches") we removed all the support fir AIVIVT cache types and renamed all references to the field to say "unknown" since support for AIVIVT caches was removed from the architecture. Some confusion has resulted since the corresponding change to the architecture left the value named as AIVIVT but documented it as reserved in v8, refactor the code so we don't define the constant instead. This will help with automatic generation of this register field since it means we care less about the correspondence with the ARM. No functional change, the value displayed to userspace is unchanged. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220704170302.2609529-2-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64/mm: Define defer_reserve_crashkernel()Anshuman Khandual
Crash kernel memory reservation gets deferred, when either CONFIG_ZONE_DMA or CONFIG_ZONE_DMA32 config is enabled on the platform. This deferral also impacts overall linear mapping creation including the crash kernel itself. Just encapsulate this deferral check in a new helper for better clarity. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20220705062556.1845734-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-07-05arm64: dts: exynosautov9: add usi device tree nodesChanho Park
Universal Serial Interface (USI) supports three types of serial interface such as Universal Asynchronous Receiver and Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C). Each protocols can be working independently and configured as one of those using external configuration inputs. Exynos Auto v9 SoC support 12 USIs. When a USI uses two pins such as i2c and 3 wire uarts(RX/TX only), we can use remain two pins as i2c mode. So, we can define one USI node that includes serial/spi and hsi2c. usi_i2c nodes can be used only for i2c mode. We can have below combinations for one USI. 1) The usi node is used either 4 pin uart or 4 pin spi -> No usi_i2c can be used 2) The usi node is used 2 pin uart(RX/TX) and i2c(SDA/SCL) -> usi_i2c should be enabled to use the latter i2c 3) The usi node is used i2c(SDA/SCL) and i2c(SDA/SCL) -> usi_i2c should be enabled to use the latter i2c By default, all USIs are initially set to uart mode by below setting. samsung,mode = <USI_V2_UART>; You can change it either USI_V2_SPI or USI_V2_I2C. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-6-chanho61.park@samsung.com
2022-07-05arm64: dts: exynosautov9: prepare usi0 changesChanho Park
Before adding whole USI nodes, this applies the changes of usi0 in advance. To be the usi0 and serian_0 nodes as SoC default, some properties should be moved to exynosautov9-sadk.dts. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-5-chanho61.park@samsung.com
2022-07-05arm64: dts: exynosautov9: add pdma0 device tree nodeChanho Park
Add an ARM pl330 dma controller DT node as pdma0. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-4-chanho61.park@samsung.com
2022-07-05dt-bindings: soc: samsung: usi: add exynosautov9-usi compatibleChanho Park
Add samsung,exynosautov9-usi dedicated compatible for representing USI of Exynos Auto v9 SoC. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220701015226.32781-2-chanho61.park@samsung.com
2022-07-05arm64: dts: exynosautov9: correct spi11 pin namesChanho Park
They should be started with "gpp5-". Fixes: 31bbac5263aa ("arm64: dts: exynos: add initial support for exynosautov9 SoC") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220627005832.8709-1-chanho61.park@samsung.com
2022-07-05Merge branch ↵Paolo Abeni
'fix-bridge_vlan_aware-sh-and-bridge_vlan_unaware-sh-with-iff_unicast_flt' Vladimir Oltean says: ==================== Fix bridge_vlan_aware.sh and bridge_vlan_unaware.sh with IFF_UNICAST_FLT Make sure that h1 and h2 don't drop packets with a random MAC DA, which otherwise confuses these selftests. Also, fix an incorrect error message found during those failures. ==================== Link: https://lore.kernel.org/r/20220703073626.937785-1-vladimir.oltean@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05selftests: forwarding: fix error message in learning_testVladimir Oltean
When packets are not received, they aren't received on $host1_if, so the message talking about the second host not receiving them is incorrect. Fix it. Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05selftests: forwarding: fix learning_test when h1 supports IFF_UNICAST_FLTVladimir Oltean
The first host interface has by default no interest in receiving packets MAC DA de:ad:be:ef:13:37, so it might drop them before they hit the tc filter and this might confuse the selftest. Enable promiscuous mode such that the filter properly counts received packets. Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Tested-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05selftests: forwarding: fix flood_unicast_test when h2 supports IFF_UNICAST_FLTVladimir Oltean
As mentioned in the blamed commit, flood_unicast_test() works by checking the match count on a tc filter placed on the receiving interface. But the second host interface (host2_if) has no interest in receiving a packet with MAC DA de:ad:be:ef:13:37, so its RX filter drops it even before the ingress tc filter gets to be executed. So we will incorrectly get the message "Packet was not flooded when should", when in fact, the packet was flooded as expected but dropped due to an unrelated reason, at some other layer on the receiving side. Force h2 to accept this packet by temporarily placing it in promiscuous mode. Alternatively we could either deliver to its MAC address or use tcpdump_start, but this has the fewest complications. This fixes the "flooding" test from bridge_vlan_aware.sh and bridge_vlan_unaware.sh, which calls flood_test from the lib. Fixes: 236dd50bf67a ("selftests: forwarding: Add a test for flooded traffic") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Tested-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-07-05ARM: dts: stm32: Add ST MIPID02 bindings to AV96Marek Vasut
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT. Both the ST MIPID02 and DCMI are disabled by default, as the AV96 camera module is optional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for RCC pinMarek Vasut
Add another mux option for RCC pin, this is used on AV96 board for e.g. sensor clock supply. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add alternate pinmux for DCMI pinsMarek Vasut
Add another mux option for DCMI pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-07-05ARM: dts: stm32: Add DHCOR based DRC Compact boardMarek Vasut
Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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