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2017-01-13ARM: dts: qcom: apq8064: Add riva-pil nodeBjorn Andersson
Add nodes for the Riva PIL, IRIS RF module, BT and WiFI services exposed by the Riva firmware and the related memory reserve. Also provides pinctrl nodes for devices enabling the riva-pil. Cc: John Stultz <john.stultz@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13ARM: dts: apq8064: add support to pm8821Srinivas Kandagatla
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13arm: dts: qcom: Fix ipq board clock ratesStephen Boyd
The ipq board has these rates as 25MHz, and not 19.2 and 27. I copy/pasted from other boards that have those rates but forgot to fix the rates here. Fixes: 30fc4212d541 ("arm: dts: qcom: Add more board clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13ARM: dts: msm8974: Remove "unused" reserved regionStephen Boyd
sources for msm8974, this isn't actually a reserved region. Instead it's marked as "unused" for reserved regions. Let's remove it so we get back a good chunk of memory. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13ARM: dts: msm8974: Add ADSP PIL nodeBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13ARM: dts: msm8974: Add ADSP smp2p and smd nodesBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13ARM: dts: qcom: msm8974: Add USB gadget nodesBjorn Andersson
Add the necessary nodes for USB gadget on MSM8974 and enable these for Honami. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-01-13arm: dts: mt2701: Add auxadc device node.Zhiyong Tao
Add auxadc device node for MT2701. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13arm: dts: mt2701: Add nand device nodeXiaolei Li
Add mt2701 nand device node, include nfi and bch ecc. Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13arm: dts: mt2701: Add spi device nodeLeilk Liu
Add spi device node for MT2701. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13ARM: dts: mt2701: add iommu/smi dtsi node for mt2701Honghui Zhang
Add the dtsi node of iommu and smi for mt2701. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13ARM: dts: mediatek: update my email addressJohn Crispin
This patch updates my email address as I no longer have access to the old one. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13arm: dts: mt2701: Add power domain controller device nodeJames Liao
Add power domain controller node (scpsys) for MT2701. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13arm: dts: mt2701: Add subsystem clock controller device nodesJames Liao
Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys, vdecsys, hifsys, ethsys and bdpsys. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13arm: dts: mt2701: Sort DT nodes by register addressJames Liao
This patch rearrange MT2701 DT nodes to keep them in ascending order. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> [mb: fix pio unit address and order] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-13ARM: dts: da850: Add ti,da830-uart compatible for serial portsDavid Lechner
TI DA8xx/OMAPL13x/AM17xx/AM18xx SoCs have extra UART registers beyond the standard 8250 registers, so we need a new compatible string to indicate this. Also, at least one of these registers uses the full 32 bits, so we need to specify reg-io-width in addition to reg-shift. "ns16550a" is left in the compatible specification since it does work as long as the bootloader configures the SoC UART power management registers. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2017-01-12ARM: dts: omap3-igep: Remove NAND partition tableLadislav Michl
FDT harcoded partition table does not match that one in historical TI's 2.6.37 kernel and non legacy kernels even use different ECC scheme, yet noone complained, so remove it altogether. Also, UBI volumes instead of partitions are used since u-boot-2016.09. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-01-12ARM: dts: am57xx-beagle-x15: implement errata "Ethernet RGMII2 Limited to ↵Grygorii Strashko
10/100 Mbps" According to errata i880 description the speed of Ethernet port 1 on AM572x SoCs rev 1.1 should be limited to 10/100Mbps, because RGMII2 Switching Characteristics are not compatible with 1000 Mbps operation [1]. The issue is fixed with Rev 2.0 silicon. Hence, rework Beagle-X15 and Begale-X15-revb1 to use phy-handle instead of phy_id and apply corresponding limitation to the Ethernet Phy 1. [1] http://www.ti.com/lit/er/sprz429j/sprz429j.pdf Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-01-12ARM: dts: am335x-phycore-som: Remove partition tablesTeresa Remmet
As the bootloader passes the NAND and the SPI flash partition tables there is no need to keep them in the kernel device tree. Removed them. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-01-12ARM: dts: dra72-evm-revc: enable irqs for dp83867 eth physGrygorii Strashko
TI DRA72-EVM Rev C has two DP83867 ethernet phys which support IRQ generation in case of phy/link status changes. The INT/PWDN lines from both DP83867 phys are wired to DRA7 gpio6.16, so reflect the same in DT. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-01-12ARM: dts: Configure BeagleBone peripheral USB VBUS irqTony Lindgren
This prevents having to poll peripheral USB port cable status. Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-01-12ARM: dts: STiH407-family: Supply Mailbox properties to delta RProcPatrice Chotard
Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH407-family: Supply mailbox properties to GP0 RProcPatrice Chotard
Signed-off-by: Loic Pallardy <loic.pallardy.chotard@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH407-family: update dmu remoteproc nodePatrice Chotard
Rename dmu_reserved to delta_reserved Rename st231_dmu to st231_delta Update the delta_reserved memory region start address Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH407-family: remove gp1 remoteproc nodePatrice Chotard
This node is unused, remove it Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH407-family: remove audio remoteproc nodePatrice Chotard
This node is unused, remove it Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH407-family: update gp0_reserved memory regionPatrice Chotard
Update the start address of gp0_reserved memory region and enable it Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH410-family: fix wrong parent clock frequencyPatrice Chotard
The clock parent was lower than child clock which is not correct. In some use case, it leads to division by zero. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2017-01-12ARM: dts: STiH410: add DELTA dt nodeHugues Fruchet
This patch adds DT node for STMicroelectronics DELTA V4L2 video decoder Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com>
2017-01-12ARM: dts: STiH407-family: disable fdma1 and fdma2Patrice Chotard
Only fdma0 instance is used for audio, so disable the 2 others instances. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-12ARM: dts: STiH410: add hqvdp nodePatrice Chotard
Enable High Quality Video Data Plane which is an hardware IP dedicated to video rendering. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-11ARM: dts: STiH410-B2120: enable sti-hda at board levelPatrice Chotard
As sti-hda is only available on STiH410-B2120, disable it in STiH410.dtsi and enable it at board level. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-01-11ARM: dts: exynos: remove Exynos4212 support (dead code)Marek Szyprowski
There are no Exynos4212 based boards in mainline, so there is no need to keep additional files for SoCs, which are never used. This patch removes support for Exynos4212 SoCs and moves previously shared Exynos4412 definitions to a single file to simplify future maintenance. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-01-10ARM: dts: at91: add devicetree for the Axentia TSE-850Peter Rosin
The Axentia TSE-850 is a SAMA5D3-based device designed to generate FM subcarrier signals. Signed-off-by: Peter Rosin <peda@axentia.se> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: add dts file for sama5d36ek CMP boardWenyou Yang
The sama5d36ek CMP board is the variant of sama5d3xek board. It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865 and some power rail. Its main purpose is used to measure the power consumption. The difference of the sama5d36ek CMP dts from sama5d36ek dts is listed as below. 1. The USB host nodes are removed, that is, the USB host is disabled. 2. The gpio_keys node is added to wake up from the sleep. 3. The LCD isn't supported due to the pins for LCD are conflicted with gpio_keys. 4. The adc0 node support the pinctrl sleep state to fix the over consumption on VDDANA. As said in errata, "When the USB host ports are used in high speed mode (EHCI), it is not possible to suspend the ports if no device is attached on each port. This leads to increased power consumption even if the system is in a low power mode." That is why the the USB host is disabled. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: sama5d2: add ssc0 definitionAlex
The sama5d2 SoC has Synchronous Serial Controller which provides synchronous communication link with external devices. It's generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync. Signed-off-by: Alex Gershgorin <alex.gershgorin@qcore.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: sama5d2 Xplained: use DMA for UART3Nicolas Ferre
Use DMA for UART3 as we have enough channels and to show how to specify DMA use with serial nodes. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: sama5d2: move UART3 to DMA1Nicolas Ferre
Now that DMA1 is defined, use it to distribute channel usage among the two controllers. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: add dma1 definition to sama5d2Nicolas Ferre
The sama5d2 SoC has a second DMA controller and can be used just like DMA0. By default both DMA controllers are configured as "Secure" in MATRIX_SPSELR so we can use whichever we want in a "single Secure World" configuration. Surprisingly the DMA1 has a lower address than DMA0. To avoid confusion place it after DMA0 node anyway. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: sama5d4 Xplained: enable UART1 node with DMANicolas Ferre
Enable UART1 and use DMA configuration with it. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: sama5d4: change DMA allocation for secure peripheralsNicolas Ferre
Some peripherals are "Programmable Secure" but left as "Secure" by default. If tried to be connected to Non-Secure DMA controller, the possibility to leak secure data is prevented so using these peripherals with DMA1 is not possible with this default configuration (MATRIX_SPSELR registers setup by bootloader). Move them to DMA0 which is an "Always-Secure" DMA controller. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: at91: sama5d3_uart: fix reg sizes to match documentationPeter Rosin
The new size (0x100) also matches the size given in sama5d3.dtsi Documentation reference: section 43.6 "Universal Asynchronous Receiver Transmitter (UART) User Interface", table 43-4 "Register Mapping" in [1]. [1] Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16 Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-01-10ARM: dts: aspeed: Add Romulus BMC platformJoel Stanley
Romulus is an OpenPower machine with an ast2500 BMC. It has NCSI networking and 512MB of RAM. Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed: Add ftgmac100 to g4 and g5 platformsJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed: Correct palmetto device treeCyril Bur
Palmettos have 512MB of memory as opposed to the previously thought 256MB. Update the device trees accordingly. We run the uart at 115200. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed: Reserve framebuffer memoryCyril Bur
When used as a BMC, the host expects to be able to use 16MB of framebuffer memory at the top of RAM. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add gpio controller to devicetreeAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add syscon and pin controller nodesAndrew Jeffery
The pin controller's child nodes expose the functions currently implemented in the g5 pin controller driver. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add LPC Controller nodeAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10ARM: dts: aspeed-g5: Add SoC Display Controller nodeAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
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