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2024-12-17arm64: dts: renesas: r9a09g047: Add I2C nodesBiju Das
Add I2C{0..8} nodes to RZ/G3E (R9A09G047) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216120029.143944-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-17dt-bindings: atmel-sysreg: add sama7d65 RAM and PITDharma Balasubiramani
Add SAMA7D65 RAM controller, PIT64 DT bindings. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/96e64f01eee264ad0ac4c720a7a1cab4f95c206b.1733505542.git.Ryan.Wanner@microchip.com [claudiu.beznea: add missing space] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-17dt-bindings: ARM: at91: Document Microchip SAMA7D65 CuriosityRomain Sioen
Document device tree binding of the Microchip SAMA7D65 Curiosity board. Signed-off-by: Romain Sioen <romain.sioen@microchip.com> Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/d5a22763a2081daa0d2155e2c05b7dc0eb468610.1733505542.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-17ARM: dts: microchip: sam9x75_curiosity: Add power monitor supportMihai Sain
Add PAC1934 support in order to monitor the board power consumption. Device is connected on flexcom7 in twi mode. [root@SAM9X75 ~]$ awk -f pac1934.awk VDD3V3 current: 10.675 mA, voltage: 3295.41 mV VDDOUT4 current: 5.7625 mA, voltage: 1196.78 mV VDDCORE current: 115.442 mA, voltage: 1243.65 mV VDDIODDR current: 29.585 mA, voltage: 1345.21 mV Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20241122080523.3941-3-mihai.sain@microchip.com [claudiu.beznea: s/VDDOUT4/DCDC4 to comply with schematics] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-17ARM: dts: microchip: sam9x7: Move i2c address/size to dtsiMihai Sain
Since these properties are common for all i2c subnodes, move them to SoC dtsi from board dts. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20241122080523.3941-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-16arm64: dts: altera: Remove unused and undocumented "snps,max-mtu" propertyRob Herring (Arm)
Remove "snps,max-mtu" property which is both unused in the kernel and undocumented. Most likely they are leftovers from downstream. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake idNiravkumar L Rabara
Add gpio0 controller node and correct DMA handshake ID for SPI tx and rx channels. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16arm64: dts: socfpga: agilex: Add VGIC maintenance interruptNiravkumar L Rabara
Add VGIC maintenance interrupt and interrupt-parent property for interrupt controller, required to run Linux in virtualized environment. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16arm: dts: socfpga: use reset-name "stmmaceth-ocp" instead of "ahb"Mamta Shukla
The ahb reset is deasserted in probe before first register access, while the stmmacheth-ocp reset needs to be asserted every time before changing the phy mode in Arria10[1]. Changed in Upstream to "ahb"(331085a423b arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb" ).This change was intended for arm64 socfpga and it is not applicable to Arria10. Further with STMMAC-SELFTEST Driver enabled, ethtool test also FAILS. $ ethtool -t eth0 [ 322.946709] socfpga-dwmac ff800000.ethernet eth0: entered promiscuous mode [ 323.374558] socfpga-dwmac ff800000.ethernet eth0: left promiscuous mode The test result is FAIL The test extra info: 1. MAC Loopback 0 2. PHY Loopback -110 3. MMC Counters -110 4. EEE -95 5. Hash Filter MC 0 6. Perfect Filter UC -110 7. MC Filter -110 8. UC Filter 0 9. Flow Control -110 10. RSS -95 11. VLAN Filtering -95 12. VLAN Filtering (perf) -95 13. Double VLAN Filter -95 14. Double VLAN Filter (perf) -95 15. Flexible RX Parser -95 16. SA Insertion (desc) -95 17. SA Replacement (desc) -95 18. SA Insertion (reg) -95 19. SA Replacement (reg) -95 20. VLAN TX Insertion -95 21. SVLAN TX Insertion -95 22. L3 DA Filtering -95 23. L3 SA Filtering -95 24. L4 DA TCP Filtering -95 25. L4 SA TCP Filtering -95 26. L4 DA UDP Filtering -95 27. L4 SA UDP Filtering -95 28. ARP Offload -95 29. Jumbo Frame -110 30. Multichannel Jumbo -95 31. Split Header -95 32. TBS (ETF Scheduler) -95 [ 324.881327] socfpga-dwmac ff800000.ethernet eth0: Link is Down [ 327.995360] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx Link:[1] https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/functional-description-of-the-emac.html Fixes: 331085a423b ("arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb") Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16ARM: dts: socfpga_cyclone5_mcvevk: Drop unused #address-cells/#size-cellsUwe Kleine-König
The properties #address-cells and #size-cells are only useful if there is a ranges property or child nodes with "reg" properties. This fixes a W=1 warning: arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts:51.22-72.4: Warning (avoid_unnecessary_addr_size): /soc/i2c@ffc04000/stmpe811@41: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-12-16arm64: dts: qcom: x1e80100-pmics: Enable all SMB2360 separatelyStephan Gerhold
At the moment, x1e80100-pmics.dtsi enables two of the SMB2360 PMICs by default and leaves the other two disabled. The third one was originally also enabled by default, but then disabled in commit a237b8da413c ("arm64: dts: qcom: x1e80100: Disable SMB2360_2 by default"). This is inconsistent and confusing. Some laptops will even need SMB2360_1 disabled by default if they just have a single USB-C port. Make this consistent by keeping all SMB2360 disabled in x1e80100-pmics.dtsi and enable them separately for all boards where needed. That way it is always clear which ones are available and avoids accidentally trying to read/write from missing chips when some of the PMICs are not present. Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241210-x1e80100-disable-smb2360-v2-1-2449be2eca29@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-14arm64: dts: exynosautov920: Add DMA nodesFaraz Ata
ExynosAutov920 SoC has 7 DMA controllers. Two secure DMAC (SPDMA0 & SPDMA1) and five non-secure DMAC (PDMA0 to PDMA4). Add the required dt nodes for the same. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Faraz Ata <faraz.ata@samsung.com> Link: https://lore.kernel.org/r/20241212115709.1724-1-faraz.ata@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-14arm64: dts: exynos8895: Add a PMU node for the second clusterIvaylo Ivanov
Since we have a PMU compatible for Samsung's Mongoose cores now, drop the comment that explains the lack of it and define the node. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241211162942.450525-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-14dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindingsIgor Belwon
Add dt-schema documentation for the Exynos990 SoC CMU. This clock management unit has a topmost block (CMU_TOP) that generates top clocks for other blocks. Currently the only other block implemented is CMU_HSI0, which provides clocks for the USB part of the SoC. Also, device-tree binding definitions added for these blocks: - CMU_TOP - CMU_HSI0 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-1-57f07080f9e4@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-13ARM: dts: nuvoton: Fix at24 EEPROM node namesRob Herring (Arm)
at24.yaml defines the node name for at24 EEPROMs as 'eeprom'. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20240910215905.823337-1-robh@kernel.org Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-13arm64: dts: renesas: rzg3s-smarc: Add sound cardClaudiu Beznea
Add sound card with SSI3 as CPU DAI and DA7212 as codec DAI. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241210170953.2936724-25-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: rzg3s-smarc: Enable SSI3Claudiu Beznea
Enable SSI3. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241210170953.2936724-24-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: Add da7212 audio codec nodeClaudiu Beznea
Add the da7212 audio codec node. Along with it regulators nodes were reworked to be able to re-use them on da7212. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241210170953.2936724-23-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator nodeClaudiu Beznea
Add versa3 clock generator node. It provides the clocks for the Ethernet PHY, PCIe, audio devices. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241210170953.2936724-22-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: r9a08g045: Add SSI nodesClaudiu Beznea
Add DT nodes for the SSI IPs available on the Renesas RZ/G3S SoC. Along with it external audio clocks were added. Board device tree could use it and update the frequencies. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241210170953.2936724-21-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: rzg3s-smarc-som: Enable ADCClaudiu Beznea
Enable ADC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241206111337.726244-16-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: r9a08g045: Add ADC nodeClaudiu Beznea
Add the device tree node for the ADC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241206111337.726244-15-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK boardBiju Das
Add the initial device tree for the Renesas RZ/G3E SMARC EVK board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoMBiju Das
Add initial support for the RZ/G3E SMARC SoM with 4GB memory, audio_extal, qextal and rtxin clks. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: r9a09g047: Add OPP tableBiju Das
Add OPP table for RZ/G3E SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-11-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: Add initial DTSI for RZ/G3E SoCBiju Das
Add the initial DTSI for the RZ/G3E SoC. The files in this commit have the following meaning: - r9a09g047.dtsi: RZ/G3E family SoC common parts - r9a09g047e57.dtsi: RZ/G3E R0A09G047E{4,5}{7,8} SoC specific parts - r9a09g047e37.dtsi: RZ/G3E R0A09G047E{2,3}{7,8} SoC specific parts Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-dts-for-v6.14Geert Uytterhoeven
Renesas RZ/G3E DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.
2024-12-13arm64: dts: renesas: falcon-ethernet: Describe PHYs connected on the ↵Niklas Söderlund
breakout board Describe and connect the five Marvell 88Q2110 PHYs present on the Falcon Ethernet breakout board. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241023154643.4025941-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: renesas: r8a779a0: Remove address- and size-cells from AVB[1-5]Niklas Söderlund
When describing the PHYs on the Falcon Ethernet breakout board mdio nodes will be needed to describe the connections, and each mdio node will need to contain these two properties instead. This will make the address-cells and size-cells described in the base SoC include file redundant and they will produce warnings, remove them. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241023154643.4025941-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13dt-bindings: clock: renesas: Document RZ/G3E SoC CPGBiju Das
Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVKBiju Das
Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variantsBiju Das
Document Renesas RZ/G3E (R9A09G047) SoC variants. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-13arm64: dts: meson: remove broadcom wifi compatible from GX reference boardsChristian Hewitt
Amlogic GX reference boards shipped with Broadcom SDIO modules and this is described in device-tree files. These boards are rare, but their device-trees are commonly used to boot no-name Android STB's that closely follow the vendor reference design. For cost reasons these boxes often use non-Broadcom RTL8189ES/FS and QCA9377 SDIO modules, and for availability reasons the chipset/module used can change between batches of the same device. Testing shows the only requirement for WiFi driver probe and load is presence of the correct 'reg' value, and all Amlogic boards use the same <1> value. Removing the 'brcm,bcm4329-fmac' compatible allows a wider range of Android STB boards to boot from reference design device-trees and have working WiFi. Also convert the 'brcmf' node name to a more generic 'sdio' to reflect we are not always using the Broadcom brcmfmac driver now. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/20241127043358.3799737-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-12-13ARM: dts: aspeed: minerva: add second source RTCYang Chen
Add second source RTC on i2c bus 9. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://patch.msgid.link/20241212133226.342937-5-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: minerva: add bmc ready led settingYang Chen
Add GPIO BMC_READY on LED and give it active value and transitory flag. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://patch.msgid.link/20241212133226.342937-4-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: minerva: add i/o expanders on each FCBYang Chen
Add four I/O expanders on each i2c of fan control board (FCB), assign the GPIO line name to each GPIO in use, and specify the interrupt GPIO number for each FCB's i/o expander. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://patch.msgid.link/20241212133226.342937-3-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: minerva: add i/o expanders on bus 0Yang Chen
Add three I/O expanders on i2c bus 0, assign the GPIO line name to each GPIO in use, and specify the interrupt GPIO that has been used on it and give the interrupt gpio number. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://patch.msgid.link/20241212133226.342937-2-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: catalina: remove interrupt of GPIOB4 form all IOEXPPotin Lai
We notice this interrupt pin always keep low, it cause BMC stuck at boot up until kernel disabling IRQ of this GPIO pin. Remove the interrupt of GPIOB4 pin from all IOEXP for now to avoid BMC get stuck. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20241121-catalina-dts-20241120-v1-2-e4212502624b@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: catalina: revise ltc4287 shunt-resistor valuePotin Lai
Fix wrong shunt-resistor settings of two ltc4287 nodes. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20241121-catalina-dts-20241120-v1-1-e4212502624b@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13arm: dts: aspeed: Blueridge and Rainer: Add VRM presence GPIOsEddie James
Add GPIO line names to the GPIO expander to describe DCM and VRM presence detection lines. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://patch.msgid.link/20241115222721.1564735-1-eajames@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: Blueridge and Fuji: Fix LED node namesEddie James
The addressing on PCA LED nodes should be in hexadecimal, not decimal. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://patch.msgid.link/20241107151431.1045102-1-eajames@linux.ibm.com [aj: Capitalise ARM in subject] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13arm: dts: aspeed: Everest and Fuji: Add VRM presence gpio expanderEddie James
Add the gpio expander that provides the VRM presence detection pins. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://patch.msgid.link/20241106193303.748824-1-eajames@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: sbp1: IBM sbp1 BMC boardPatrick Rudolph
Add a device tree for IBM sbp1 BMC board which is based on AST2600 SOC. sbp1 baseboard has: - support for up to four Sapphire Rapids sockets having 16 DIMMS each. - 240 core/480 threads at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM Added the following: - Indication LEDs - I2C mux & GPIO controller, pin assignments, - Thermister, - Voltage regulator - EEPROM/VPD Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Link: https://patch.msgid.link/20241104092220.2268805-2-naresh.solanki@9elements.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13dt-bindings: arm: aspeed: add IBM SBP1 boardNaresh Solanki
Document the new compatibles used on IBM SBP1. Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20241104092220.2268805-1-naresh.solanki@9elements.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: Add device tree for Ampere's Mt. Jefferson BMCChanh Nguyen
The Mt. Jefferson BMC is an ASPEED AST2600-based BMC for the Mt. Jefferson hardware reference platform with AmpereOne(TM)M processor. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Link: https://patch.msgid.link/20241021083702.9734-3-chanh@os.amperecomputing.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13dt-bindings: arm: aspeed: add Mt. Jefferson boardChanh Nguyen
Document Ampere's Mt. Jefferson BMC board compatible. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20241021083702.9734-2-chanh@os.amperecomputing.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: yosemite4: Add i2c-mux for ADC monitor on Spider BoardRicky CX Wu
Add I2C mux for ADC monitors on Spider Board. Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com> Link: https://patch.msgid.link/20241003074251.3818101-10-Delphine_CC_Chiu@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode on Fan BoardsRicky CX Wu
Revise adc128d818 adc mode on Fan Boards according to schematic. Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com> Link: https://patch.msgid.link/20241003074251.3818101-9-Delphine_CC_Chiu@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: yosemite4: Change the address of Fan IC on fan boardsRicky CX Wu
Change the address of Fan IC: Max31790 on fan boards according to schematic. Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com> Link: https://patch.msgid.link/20241003074251.3818101-8-Delphine_CC_Chiu@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-12-13ARM: dts: aspeed: yosemite4: Revise address of i2c-mux for two fan boardsRicky CX Wu
Change the address of the I2C mux for two fan boards to 0x74 according to schematic. Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com> Link: https://patch.msgid.link/20241003074251.3818101-7-Delphine_CC_Chiu@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
generated by cgit (git 2.34.1) at 2025-09-13 02:24:58 +0000