summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-06-28sched/fair: Ensure _sum and _avg values stay consistentOdin Ugedal
The _sum and _avg values are in general sync together with the PELT divider. They are however not always completely in perfect sync, resulting in situations where _sum gets to zero while _avg stays positive. Such situations are undesirable. This comes from the fact that PELT will increase period_contrib, also increasing the PELT divider, without updating _sum and _avg values to stay in perfect sync where (_sum == _avg * divider). However, such PELT change will never lower _sum, making it impossible to end up in a situation where _sum is zero and _avg is not. Therefore, we need to ensure that when subtracting load outside PELT, that when _sum is zero, _avg is also set to zero. This occurs when (_sum < _avg * divider), and the subtracted (_avg * divider) is bigger or equal to the current _sum, while the subtracted _avg is smaller than the current _avg. Reported-by: Sachin Sant <sachinp@linux.vnet.ibm.com> Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Odin Ugedal <odin@uged.al> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Vincent Guittot <vincent.guittot@linaro.org> Tested-by: Sachin Sant <sachinp@linux.vnet.ibm.com> Link: https://lore.kernel.org/r/20210624111815.57937-1-odin@uged.al
2021-06-28media: s5p-mfc: Fix display delay control creationMarek Szyprowski
v4l2_ctrl_new_std() fails if the caller provides no 'step' parameter for integer control, so define it to fix following error: s5p_mfc_dec_ctrls_setup:1166: Adding control (1) failed Fixes: c3042bff918a ("media: s5p-mfc: Use display delay and display enable std controls") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-28media: mtk-vpu: on suspend, read/write regs only if vpu is runningDafna Hirschfeld
If the vpu is not running, we should not rely on VPU_IDLE_REG value. In this case, the suspend cb should only unprepare the clock. This fixes a system-wide suspend to ram failure: [ 273.073363] PM: suspend entry (deep) [ 273.410502] mtk-msdc 11230000.mmc: phase: [map:ffffffff] [maxlen:32] [final:10] [ 273.455926] Filesystems sync: 0.378 seconds [ 273.589707] Freezing user space processes ... (elapsed 0.003 seconds) done. [ 273.600104] OOM killer disabled. [ 273.603409] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 273.613361] mwifiex_sdio mmc2:0001:1: None of the WOWLAN triggers enabled [ 274.784952] mtk_vpu 10020000.vpu: vpu idle timeout [ 274.789764] PM: dpm_run_callback(): platform_pm_suspend+0x0/0x70 returns -5 [ 274.796740] mtk_vpu 10020000.vpu: PM: failed to suspend: error -5 [ 274.802842] PM: Some devices failed to suspend, or early wake event detected [ 275.426489] OOM killer enabled. [ 275.429718] Restarting tasks ... [ 275.435765] done. [ 275.447510] PM: suspend exit Fixes: 1f565e263c3e ("media: mtk-vpu: VPU should be in idle state before system is suspended") Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-28media: video-mux: Skip dangling endpointsPhilipp Zabel
i.MX6 device tree include files contain dangling endpoints for the board device tree writers' convenience. These are still included in many existing device trees. Treat dangling endpoints as non-existent to support them. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Fixes: 612b385efb1e ("media: video-mux: Create media links in bound notifier") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-06-28bpf, x86: Fix extable offset calculationRavi Bangoria
Commit 4c5de127598e1 ("bpf: Emit explicit NULL pointer checks for PROBE_LDX instructions.") is emitting a couple of instructions before the actual load. Consider those additional instructions while calculating extable offset. Fixes: 4c5de127598e1 ("bpf: Emit explicit NULL pointer checks for PROBE_LDX instructions.") Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20210622110026.1157847-1-ravi.bangoria@linux.ibm.com
2021-06-28gfs2: Fix error handling in init_statfsAndreas Gruenbacher
On an error path, init_statfs calls iput(pn) after pn has already been put. Fix that by setting pn to NULL after the initial iput. Fixes: 97fd734ba17e ("gfs2: lookup local statfs inodes prior to journal recovery") Cc: stable@vger.kernel.org # v5.10+ Reported-by: Jing Xiangfeng <jingxiangfeng@huawei.com> Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
2021-06-28gfs2: Fix underflow in gfs2_page_mkwriteAndreas Gruenbacher
On filesystems with a block size smaller than PAGE_SIZE and non-empty files smaller then PAGE_SIZE, gfs2_page_mkwrite could end up allocating excess blocks beyond the end of the file, similar to fallocate. This doesn't make sense; fix it. Reported-by: Bob Peterson <rpeterso@redhat.com> Fixes: 184b4e60853d ("gfs2: Fix end-of-file handling in gfs2_page_mkwrite") Cc: stable@vger.kernel.org # v5.5+ Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
2021-06-28gfs2: Use list_move_tail instead of list_del/list_add_tailBaokun Li
Using list_move_tail() instead of list_del() + list_add_tail(). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Baokun Li <libaokun1@huawei.com> Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
2021-06-28gfs2: Fix do_gfs2_set_flags descriptionAndreas Gruenbacher
Commit 88b631cbfbeb ("gfs2: convert to fileattr") changed the argument list without updating the description. Signed-off-by: Andreas Gruenbacher <agruenba@redhat.com>
2021-06-28drm/i915: Reinstate the mmap ioctl for some platformsThomas Hellström
Reinstate the mmap ioctl for all current integrated platforms. The intention was really to have it disabled for discrete graphics where we enforce a single mmap mode. This was reported to break ADL-P with the media stack, which was not the intention. Although longer term we do still plan to sunset this ioctl even for integrated, in favour of using mmap_offset instead. Fixes: 35cbd91eb541 ("drm/i915: Disable mmap ioctl for gen12+") Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210624112914.311984-1-thomas.hellstrom@linux.intel.com (cherry picked from commit d3f3baa3562a5d09f3e87f5fdf84952112807753) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2021-06-28drm/i915/dsc: abstract helpers to get bigjoiner primary/secondary crtcJani Nikula
Add a single point of truth for figuring out the primary/secondary crtc for bigjoiner instead of duplicating the magic pipe +/- 1 in multiple places. Also fix the pipe validity checks to properly take non-contiguous pipes into account. The current checks may theoretically overflow i915->pipe_to_crtc_mapping[pipe], albeit with a warning, due to fused off pipes, as INTEL_NUM_PIPES() returns the actual number of pipes on the platform, and the check is for INTEL_NUM_PIPES() == pipe + 1. Prefer primary/secondary terminology going forward. v2: - Improved abstractions for pipe validity etc. Fixes: 8a029c113b17 ("drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave") Fixes: d961eb20adb6 ("drm/i915/bigjoiner: atomic commit changes for uncompressed joiner") Cc: Animesh Manna <animesh.manna@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Manasi Navare <manasi.dl.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210610090528.20511-1-jani.nikula@intel.com (cherry picked from commit 17203224f0536cf223dc5789028d04a768d96ec3) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2021-06-28Merge tag 'irqchip-5.14' of ↵Thomas Gleixner
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier: - Revamped the irqdomain internals to consistently cache irqdata - Expose a new API to simplify IRQ handling involving an irqdomain by not using the IRQ number - Convert all the irqchip drivers to this new API - Allow the Qualcomm PDC driver to be compiled as a module - Fix HiSi MBIGEN compile warning when CONFIG_ACPI isn't selected - Remove a bunch of spurious printks on error paths - The obligatory couple of DT updates
2021-06-28platform/x86: dell-wmi-sysman: Change user experience when Admin/System ↵Prasanth KSR
Password is modified Whenever user has changed an Admin/System Password using the sysfs, then we are automatically copying the new password to existing password field. Co-developed-by: Divya Bharathi <divya.bharathi@dell.com> Signed-off-by: Divya Bharathi <divya.bharathi@dell.com> Signed-off-by: Prasanth KSR <prasanth.ksr@dell.com> Link: https://lore.kernel.org/r/20210628084906.4233-1-prasanth.ksr@dell.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-06-28platform/x86: intel_skl_int3472: Uninitialized variable in ↵Dan Carpenter
skl_int3472_handle_gpio_resources() This function returns negative error codes, zero (to indicate that everything has been completed successfully) and one (to indicate that more resources need to be handled still). This code prints an uninitialized error message when the function returns one which potentially leads to an Oops. Fixes: 5de691bffe57 ("platform/x86: Add intel_skl_int3472 driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Daniel Scally <djrscally@gmail.com> Link: https://lore.kernel.org/r/YNXTkLNtiTDlFlZa@mwanda Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-06-28platform/x86: think-lmi: Move kfree(setting->possible_values) to ↵Hans de Goede
tlmi_attr_setting_release() We must not free the possible_values string before we have called sysfs_remove_group(kobj, &tlmi_attr_group) otherwise there is a race where a sysfs read of possible_values could reference the free-ed memory. Move the kfree(setting->possible_values) together with the free of the actual tlmi_attr_setting struct to avoid this race. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-06-28platform/x86: think-lmi: Split current_value to reflect only the valueMario Limonciello
Currently attributes will show things like: `BootOrderLock,Disable` rather than just `Disable`. Of course this works, but the attribute is intended to be read by userspace tools and not require further processing. That is a userspace tool can display a drop down of `possible_values` and `current_value` is one of them from the list. This also aligns `think-lmi` with how `dell-wmi-sysman` works. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20210622200755.12379-3-mario.limonciello@amd.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-06-28platform/x86: think-lmi: Fix issues with duplicate attributesMario Limonciello
On an AMD based Lenovo T14, I find that the module doesn't work at all, and instead has a traceback with messages like: ``` sysfs: cannot create duplicate filename '/devices/virtual/firmware-attributes/thinklmi/attributes/Reserved' ``` Duplicate and reserved values showing up appear to be a firmware bug, but they shouldn't make the driver explode. So catch them and skip them. Fixes: a40cd7ef22fb ("platform/x86: think-lmi: Add WMI interface support on Lenovo platforms") Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20210622200755.12379-2-mario.limonciello@amd.com [hdegoede@redhat.com: Add missing kfree(tlmi_priv.setting[i])] Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-06-28time/kunit: Add missing MODULE_LICENSE()Thomas Gleixner
[ mingo: MODULE_LICENSE() takes a string. ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2021-06-27clk: hisilicon: Add clock driver for hi3559A SoCDongjiu Geng
Add clock drivers for hi3559A SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Link: https://lore.kernel.org/r/1616498973-47067-3-git-send-email-gengdongjiu1@gmail.com [sboyd@kernel.org: Mark arrays static, add __iomem, drop unused array, avoid kfree of devm memory] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: Document the hi3559a clock bindingsDongjiu Geng
Add DT bindings documentation for hi3559a SoC clock. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1616498973-47067-2-git-send-email-gengdongjiu1@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add sysfs properties to allow checking/resetting device faultsRobert Hancock
Add sysfs property files to allow viewing the current and latched states of the input present and PLL lock bits, and allow resetting the latched fault state. This allows manual checks or automated userspace polling for faults occurring after initialization. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-10-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add silabs,iovdd-33 propertyRobert Hancock
Add a property to allow specifying that the external I2C IO pins are using 3.3V voltage thresholds rather than 1.8V. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-9-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add silabs,xaxb-ext-clk propertyRobert Hancock
Add a property to allow specifying that the device XA/XB pins are used for an external clock input rather than for a clock crystal. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-8-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Allow different output VDD_SEL valuesRobert Hancock
The driver was not previously programming the VDD_SEL values for each output to indicate what external VDDO voltage was used for each. Add ability to specify a regulator supplying the VDDO pin for each output of the device. The voltage of the regulator is used to automatically set the VDD_SEL value appropriately. If no regulator is specified and the chip is being reconfigured, assume 2.5V which appears to be the chip default. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-7-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Update initialization magicRobert Hancock
Update the default register settings to include the VCO_RESET_CALCODE settings (set by the SiLabs ClockBuilder software but not described in the datasheet). Also update part of the initialization sequence to match ClockBuilder and the datasheet. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-6-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock
After initializing the device, wait for it to report that the input clock is present and the PLL has locked before declaring success. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-5-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock
If the Si5341 is being initially programmed and has no stored NVM configuration, some of the register contents may contain unexpected values, such as zeros, which could cause divide by zero errors during driver initialization. Trap errors caused by zero registers or zero clock rates which could result in divide errors later in the code. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-4-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Wait for DEVICE_READY on startupRobert Hancock
The Si5341 datasheet warns that before accessing any other registers, including the PAGE register, we need to wait for the DEVICE_READY register to indicate the device is ready, or the process of the device loading its state from NVM can be corrupted. Wait for DEVICE_READY on startup before continuing initialization. This is done using a raw I2C register read prior to setting up regmap to avoid any potential unwanted automatic PAGE register accesses from regmap at this stage. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-3-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: clk-si5341: Add new attributesRobert Hancock
Add new silabs,xaxb-ext-clk and silabs,iovdd-33 properties. Changed vdd-supply on top-level node to optional since it is not actually used by the driver. Removed vdd-supply from output sub-nodes, as it was not supported by the driver and it is not easily possible to support this in that location with the kernel regulator infrastructure. Changed to have vddoX-supply attributes for each output on the top-level device node. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-2-robert.hancock@calian.com Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27drivers: ti: remove redundant error message in adpll.cYu Jiahua
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Yu Jiahua <yujiahua1@huawei.com> Link: https://lore.kernel.org/r/20210616034826.37276-1-yujiahua1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: clkgen-fsyn: add new introduced compatibleAlain Volmat
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Link: https://lore.kernel.org/r/20210331201632.24530-8-avolmat@me.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-7-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: clkgen-pll: add new introduced compatibleAlain Volmat
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210331201632.24530-6-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-5-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: flexgen: add new introduced compatibleAlain Volmat
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210331201632.24530-4-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-3-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat
ODF field within the struct clkgen_pll is never used by the driver and can thus be removed. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-2-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: Support bypassing dividersPaul Cercueil
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatiblesPaul Cercueil
Add ingenic,jz4760-cgu and ingenic,jz4760b-cgu compatible strings for the JZ4760 and JZ4760B SoCs respectively. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210530164923.18134-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek
Caught this when looking at alpha-pll code. Untested but it is clear that this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL. Fixes: 691865bad627 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea
Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/d62e4f1f85c5cef05be14d9e8143e88bbddd2e0f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoCCristian Ciocaltea
Add the missing NIC and ETHERNET clock bindings constants for Actions Semi Owl S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1d0902cf073f76a1a602410061481ccb3fc36a72.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea
There are a few issues with the setup of the Actions Semi Owl S500 SoC's clock chain involving AHPPREDIV, H and AHB clocks: * AHBPREDIV clock is defined as a muxer only, although it also acts as a divider. * H clock is using a wrong divider register offset * AHB is defined as a multi-rate factor clock, but it is actually just a fixed pass clock. Let's provide the following fixes: * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition. * Use the correct register shift value in the OWL_DIVIDER definition for H clock * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an ungated OWL_COMP_FIXED_FACTOR definition. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Link: https://lore.kernel.org/r/21c1abd19a7089b65a34852ac6513961be88cbe1.1623354574.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea
The following clocks of the Actions Semi Owl S500 SoC have been defined to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, VDE, BISP, SENSOR[0-1] There are several issues involved in this approach: * 'bisp_factor_table[]' describes the configuration of a regular 8-rates divider, so its usage is redundant. Additionally, judging by the BISP clock context, it is incomplete since it maps only 8 out of 12 possible entries. * The clocks mentioned above are not identical in terms of the available rates, therefore cannot rely on the same factor table. Specifically, BISP and SENSOR* are standard 12-rate dividers so their configuration should rely on a proper clock div table, while VCE and VDE require a factor table that is a actually a subset of the one needed for DE[1-2] clocks. Let's fix this by implementing the following: * Add new factor tables 'de_factor_table' and 'hde_factor_table' to properly handle DE[1-2], VCE and VDE clocks. * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] clocks converted to OWL_COMP_DIV. * Drop the now unused 'bisp_factor_table[]'. Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since there is no reason to always keep ON those clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/e675820a46cd9930d8d576c6cae61d41c1a8416f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea
Drop the unsupported entries in the factor table used for the SD[0-2] clocks definitions on the Actions Semi Owl S500 SoC. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/196c948d708a22b8198c95f064a0f6b6820f9980.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea
Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/4714d05982b19ac5fec2ed74f54be42d8238e392.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit (git 2.34.1) at 2025-10-01 02:48:32 +0000