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2017-09-01Merge remote-tracking branches 'asoc/topic/blackfin', 'asoc/topic/build', ↵Mark Brown
'asoc/topic/cirrus' and 'asoc/topic/compress' into asoc-next
2017-09-01Merge remote-tracking branches 'asoc/topic/adau1977', 'asoc/topic/arizona', ↵Mark Brown
'asoc/topic/atmel', 'asoc/topic/au1x' and 'asoc/topic/bcm' into asoc-next
2017-09-01Merge remote-tracking branch 'asoc/topic/rcar' into asoc-nextMark Brown
2017-09-01Merge remote-tracking branch 'asoc/topic/intel' into asoc-nextMark Brown
2017-09-01Merge remote-tracking branch 'asoc/topic/core' into asoc-nextMark Brown
2017-09-01Merge remote-tracking branch 'asoc/topic/const' into asoc-nextMark Brown
2017-09-01Merge remote-tracking branch 'asoc/topic/component' into asoc-nextMark Brown
2017-09-01Merge remote-tracking branch 'asoc/topic/msm8916' into asoc-nextMark Brown
2017-09-01Merge remote-tracking branches 'asoc/fix/arizona' and 'asoc/fix/mtk' into ↵Mark Brown
asoc-linus
2017-09-01Merge remote-tracking branch 'asoc/fix/rcar' into asoc-linusMark Brown
2017-09-01Merge remote-tracking branch 'asoc/fix/intel' into asoc-linusMark Brown
2017-09-01Merge tag 'asoc-fix-v4.13-rc7' into asoc-linusMark Brown
ASoC: Fixes for v4.13 A couple of fixes, one for a regression in simple-card introduced during the merge window that was only reported this week and another for a regression in registration of ACPI GPIOs. # gpg: Signature made Thu 31 Aug 2017 12:50:29 BST # gpg: using RSA key ADE668AA675718B59FE29FEA24D68B725D5487D0 # gpg: issuer "broonie@kernel.org" # gpg: Good signature from "Mark Brown <broonie@sirena.org.uk>" [unknown] # gpg: aka "Mark Brown <broonie@debian.org>" [unknown] # gpg: aka "Mark Brown <broonie@kernel.org>" [unknown] # gpg: aka "Mark Brown <broonie@tardis.ed.ac.uk>" [unknown] # gpg: aka "Mark Brown <broonie@linaro.org>" [unknown] # gpg: aka "Mark Brown <Mark.Brown@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3F25 68AA C269 98F9 E813 A1C5 C3F4 36CA 30F5 D8EB # Subkey fingerprint: ADE6 68AA 6757 18B5 9FE2 9FEA 24D6 8B72 5D54 87D0
2017-09-01ASoC: Intel: Skylake: Add IPC to configure the copier secondary pinsPradeep Tewani
Copier can support upto 4 output pins. However, only pin 0 is configured as a part of copier initialization. Configuring rest of pins require the separate IPC to be sent to fw. Signed-off-by: Pradeep Tewani <pradeep.d.tewani@intel.com> Acked-By: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01ASoC: add missing compile rule for max98371Kuninori Morimoto
It is still using old driver style, this patch also fixup it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01ASoC: add missing compile rule for sirf-audio-codecKuninori Morimoto
It is still using old driver style, this patch also fixup it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01ASoC: add missing compile rule for max98371Kuninori Morimoto
It is still using old driver style, this patch also fixup it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01ASoC: cs43130: Add devicetree bindings for CS43130Li Xu
Add devicetree bindings documentation file for Cirrus Logic CS43130 codec. Signed-off-by: Li Xu <li.xu@cirrus.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01ASoC: cs43130: Add support for CS43130 codecLi Xu
Add support for Cirrus Logic CS43130 codec. Support: I2S/DSP PCM playback. DoP/DSD playback. HP detection and DC/AC impedance measurement. Signed-off-by: Li Xu <li.xu@cirrus.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01ASoC: make clock direction configurable in asoc-simpleVitaly Wool
Some CPU drivers (e. g. davinci-mcasp) may require the system clock to be configured as OUT, while there's no good way currently to set SND_SOC_CLK_OUT in simple-soc driver if the clock is fixed-rate. This patch makes asoc_simple_card_init_dai() initialize clock to SND_SOCK_CLK_OUT if explicitly stated in the relevant dts file. This change is transparent and doesn't change the default behavior. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01spi: spi-falcon: drop check of boot selectHauke Mehrtens
Do not check which flash type the SoC was booted from before using this driver. Assume that the device tree is correct and use this driver when it was added to device tree. This also removes a build dependency to the SoC code. All device trees I am aware of only have one correct flash device entry in it. The device tree is anyway bundled with the kernel in all systems using device tree I know of. The boot mode can be specified with some pin straps and will select the flash type the rom code will boot from. One SPI, NOR or NAND flash chip can be connect to the EBU and used to load the first stage boot loader from. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-01x86/idt: Fix the X86_TRAP_BP gateIngo Molnar
Andrei Vagin reported a CRIU regression and bisected it back to: 90f6225fba0c ("x86/idt: Move IST stack based traps to table init") This table init conversion loses the system-gate property of X86_TRAP_BP and erroneously moves it from DPL3 to DPL0. Fix it. Reported-by: Andrei Vagin <avagin@virtuozzo.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: dvlasenk@redhat.com Cc: linux-tip-commits@vger.kernel.org Cc: peterz@infradead.org Cc: brgerst@gmail.com Cc: rostedt@goodmis.org Cc: bp@alien8.de Cc: luto@kernel.org Cc: jpoimboe@redhat.com Cc: Cyrill Gorcunov <gorcunov@openvz.org> Cc: torvalds@linux-foundation.org Cc: tip-bot for Jacob Shin <tipbot@zytor.com> Link: http://lkml.kernel.org/r/20170901082630.xvyi5bwk6etmppqc@gmail.com
2017-09-01ANDROID: binder: don't queue async transactions to thread.Martijn Coenen
This can cause issues with processes using the poll() interface: 1) client sends two oneway transactions 2) the second one gets queued on async_todo (because the server didn't handle the first one yet) 3) server returns from poll(), picks up the first transaction and does transaction work 4) server is done with the transaction, sends BC_FREE_BUFFER, and the second transaction gets moved to thread->todo 5) libbinder's handlePolledCommands() only handles the commands in the current data buffer, so doesn't see the new transaction 6) the server continues running and issues a new outgoing transaction. Now, it suddenly finds the incoming oneway transaction on its thread todo, and returns that to userspace. 7) userspace does not expect this to happen; it may be holding a lock while making the outgoing transaction, and if handling the incoming trasnaction requires taking the same lock, userspace will deadlock. By queueing the async transaction to the proc workqueue, we make sure it's only picked up when a thread is ready for proc work. Signed-off-by: Martijn Coenen <maco@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01ANDROID: binder: don't enqueue death notifications to thread todo.Martijn Coenen
This allows userspace to request death notifications without having to worry about getting an immediate callback on the same thread; one scenario where this would be problematic is if the death recipient handler grabs a lock that was already taken earlier (eg as part of a nested transaction). Signed-off-by: Martijn Coenen <maco@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01ANDROID: binder: Don't BUG_ON(!spin_is_locked()).Martijn Coenen
Because is_spin_locked() always returns false on UP systems. Use assert_spin_locked() instead, and remove the WARN_ON() instances, since those were easy to verify. Signed-off-by: Martijn Coenen <maco@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01ANDROID: binder: Add BINDER_GET_NODE_DEBUG_INFO ioctlColin Cross
The BINDER_GET_NODE_DEBUG_INFO ioctl will return debug info on a node. Each successive call reusing the previous return value will return the next node. The data will be used by libmemunreachable to mark the pointers with kernel references as reachable. Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Martijn Coenen <maco@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01ANDROID: binder: push new transactions to waiting threads.Martijn Coenen
Instead of pushing new transactions to the process waitqueue, select a thread that is waiting on proc work to handle the transaction. This will make it easier to improve priority inheritance in future patches, by setting the priority before we wake up a thread. If we can't find a waiting thread, submit the work to the proc waitqueue instead as we did previously. Signed-off-by: Martijn Coenen <maco@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01ANDROID: binder: remove proc waitqueueMartijn Coenen
Removes the process waitqueue, so that threads can only wait on the thread waitqueue. Whenever there is process work to do, pick a thread and wake it up. Having the caller pick a thread is helpful for things like priority inheritance. This also fixes an issue with using epoll(), since we no longer have to block on different waitqueues. Signed-off-by: Martijn Coenen <maco@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01android: binder: Add page usage in binder statsSherry Yang
Add the number of active, lru, and free pages for each binder process in binder stats Signed-off-by: Sherry Yang <sherryy@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01android: binder: fixup crash introduced by moving buffer hdrSherry Yang
Fix crash introduced by 74310e06be4d74dcf67cd108366710dee5c576d5 (android: binder: Move buffer out of area shared with user space) when close is called after open without mmap in between. Reported-by: kernel test robot <fengguang.wu@intel.com> Fixes: 74310e06be4d ("android: binder: Move buffer out of area shared with user space") Signed-off-by: Sherry Yang <sherryy@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-01axonram: Return directly after a failed kzalloc() in axon_ram_probe()Markus Elfring
* Return directly after a call of the function "kzalloc" failed at the beginning. * Delete a repeated check for the local variable "bank" which became unnecessary with this refactoring. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01axonram: Improve a size determination in axon_ram_probe()Markus Elfring
Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01axonram: Delete an error message for a failed memory allocation in ↵Markus Elfring
axon_ram_probe() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/powernv/npu: Move tlb flush before launching ATSDAlistair Popple
The nest MMU tlb flush needs to happen before the GPU translation shootdown is launched to avoid the GPU refilling its tlb with stale nmmu translations prior to the nmmu flush completing. Fixes: 1ab66d1fbada ("powerpc/powernv: Introduce address translation services for Nvlink2") Cc: stable@vger.kernel.org # v4.12+ Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/macintosh: constify wf_sensor_ops structuresJulia Lawall
The wf_sensor_ops structures are only stored in the ops field of a wf_sensor structure, which is declared as const. Thus the wf_sensor_ops structures themselves can be const. Done with the help of Coccinelle. // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct wf_sensor_ops i@p = { ... }; @ok1@ identifier r.i; struct wf_sensor s; position p; @@ s.ops = &i@p @ok2@ identifier r.i; struct wf_sat_sensor s; position p; @@ s.sens.ops = &i@p @bad@ position p != {r.p,ok1.p,ok2.p}; identifier r.i; struct wf_sensor_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct wf_sensor_ops i = { ... }; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/iommu: Use permission-specific DEVICE_ATTR variantsJulia Lawall
Use DEVICE_ATTR_RW for read-write attributes. This simplifies the source code, improves readbility, and reduces the chance of inconsistencies. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/eeh: Delete an error out of memory message at init timeMarkus Elfring
Omit an extra message for a memory allocation failure in eeh_dev_init(). This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> [mpe: Do not drop the message that can happen at runtime and lead to an event not being handled] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/mm: Use seq_putc() in two functionsMarkus Elfring
Two single characters (line breaks) should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01macintosh: Convert to using %pOF instead of full_nameRob Herring
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> [mpe: Also convert the two cases inside #if 0] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01ide: pmac: Convert to using %pOF instead of full_nameRob Herring
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-ide@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Add P9 NX support for 842 compression engineHaren Myneni
This patch adds P9 NX support for 842 compression engine. Virtual Accelerator Switchboard (VAS) is used to access 842 engine on P9. For each NX engine per chip, setup receive window using vas_rx_win_open() which configures RxFIFo with FIFO address, lpid, pid and tid values. This unique (lpid, pid, tid) combination will be used to identify the target engine. For crypto open request, open send window on the NX engine for the corresponding chip / cpu where the open request is executed. This send window will be closed upon crypto close request. NX provides high and normal priority FIFOs. For compression / decompression requests, we use only hight priority FIFOs in kernel. Each NX request will be communicated to VAS using copy/paste instructions with vas_copy_crb() / vas_paste_crb() functions. Signed-off-by: Haren Myneni <haren@us.ibm.com> Reviewed-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Add P9 NX specific error codes for 842 engineHaren Myneni
This patch adds changes for checking P9 specific 842 engine error codes. These errros are reported in coprocessor status block (CSB) for failures. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Use kzalloc for workmem allocationHaren Myneni
Send window is opened / closed for each crypto session. So initializes txwin in workmem. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Add nx842_add_coprocs_list functionHaren Myneni
Updating coprocessor list is moved to nx842_add_coprocs_list(). This function will be used for both icswx and VAS functions. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Create nx842_delete_coprocs functionHaren Myneni
Move deleting coprocessors info upon exit or failure to nx842_delete_coprocs(). Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Create nx842_configure_crb functionHaren Myneni
Configure CRB is moved to nx842_configure_crb() so that it can be used for icswx and VAS exec functions. VAS function will be added later with P9 support. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01crypto/nx: Rename nx842_powernv_function as icswx functionHaren Myneni
Rename nx842_powernv_function to nx842_powernv_exec. nx842_powernv_exec points to nx842_exec_icswx and will be point to VAS exec function which will be added later for P9 NX support. Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/32: remove a NOP from memset()Christophe Leroy
memset() is patched after initialisation to activate the optimised part which uses cache instructions. Today we have a 'b 2f' to skip the optimised patch, which then gets replaced by a NOP, implying a useless cycle consumption. As we have a 'bne 2f' just before, we could use that instruction for the live patching, hence removing the need to have a dedicated 'b 2f' to be replaced by a NOP. This patch changes the 'bne 2f' by a 'b 2f'. During init, that 'b 2f' is then replaced by 'bne 2f' Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/32: optimise memset()Christophe Leroy
There is no need to extend the set value to an int when the length is lower than 4 as in that case we only do byte stores. We can therefore immediately branch to the part handling it. By separating it from the normal case, we are able to eliminate a few actions on the destination pointer. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc: fix location of two EXPORT_SYMBOLChristophe Leroy
Commit 9445aa1a3062a ("ppc: move exports to definitions") added EXPORT_SYMBOL() for memset() and flush_hash_pages() in the middle of the functions. This patch moves them at the end of the two functions. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-09-01powerpc/32: add memset16()Christophe Leroy
Commit 694fc88ce271f ("powerpc/string: Implement optimized memset variants") added memset16(), memset32() and memset64() for the 64 bits PPC. On 32 bits, memset64() is not relevant, and as shown below, the generic version of memset32() gives a good code, so only memset16() is candidate for an optimised version. 000009c0 <memset32>: 9c0: 2c 05 00 00 cmpwi r5,0 9c4: 39 23 ff fc addi r9,r3,-4 9c8: 4d 82 00 20 beqlr 9cc: 7c a9 03 a6 mtctr r5 9d0: 94 89 00 04 stwu r4,4(r9) 9d4: 42 00 ff fc bdnz 9d0 <memset32+0x10> 9d8: 4e 80 00 20 blr The last part of memset() handling the not 4-bytes multiples operates on bytes, making it unsuitable for handling word without modification. As it would increase memset() complexity, it is better to implement memset16() from scratch. In addition it has the advantage of allowing a more optimised memset16() than what we would have by using the memset() function. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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