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2024-10-29arm64: dts: st: add RTC on stm32mp25xValentin Caron
Add compatible, clock, and interrupt properties of STM32 RTC on stm32mp25x SOCs. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: add support of WLAN/BT on stm32mp135f-dkChristophe Roullier
Add support of WLAN/BT Murata Type 1DX module: - usart2 is used for Bluetooth interface - sdmmc2 is used for WLAN (sdio) interface Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2Christophe Roullier
Add support of WLAN/BT Murata Type 1DX module: - usart2 is used for Bluetooth interface - sdmmc2 is used for WLAN (sdio) interface Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp135f-dkValentin Caron
On stm32mp135f-dk board, WLAN/BT module LPO_IN pin is wired to RTC OUT2_RMP pin. Provide a pinctrl configuration to enable LSCO on OUT2_RMP. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp157c-dk2Valentin Caron
On stm32mp157c-dk2 board, WLAN/BT module LPO_IN pin is wired to RTC OUT2_RMP pin. Provide a pinctrl configuration to enable LSCO on OUT2_RMP. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp13Valentin Caron
Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin for RTC OUT2_RMP, in stm32mp13-pinctrl.dtsi. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15Valentin Caron
Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin for RTC OUT2_RMP, in stm32mp15-pinctrl.dtsi. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx ↵Marek Vasut
DHCOR SoM DT The STM32MP13xx DHCOR SoM is populated with M24256E EEPROM which has Additional Write lockable page at separate I2C address. Describe the page in DT to make it available. Note that the WLP page on this device is hardware write-protected by R37 which pulls the nWC signal high to VDD_3V3_1V8 power rail. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variantDmitry Baryshkov
As most other board Miix uses board-id = 0xff, so define calibration variant to distinguish it from other devices with the same chip_id. qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40010002 Cc: Kalle Valo <kvalo@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240723-miix630-support-v2-5-7d98f6047a17@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29arm64: dts: qcom: msm8998-clamshell: enable resin/VolDownDmitry Baryshkov
Let resin device generate the VolumeDown key. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240723-miix630-support-v2-4-7d98f6047a17@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp buttonDmitry Baryshkov
Add gpio-keys device, responsible for a single button: Volume Up. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240723-miix630-support-v2-3-7d98f6047a17@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPIDmitry Baryshkov
Enable two other DSP instances on this platofm, aDSP and SLPI. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240723-miix630-support-v2-2-7d98f6047a17@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreenDmitry Baryshkov
There is no point in keeping touchscreen disabled, enable corresponding i2c-hid device. 04F3:2608 Touchscreen as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input1 04F3:2608 as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input2 04F3:2608 as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input3 04F3:2608 Stylus as /devices/platform/soc@0/c179000.i2c/i2c-0/0-0010/0018:04F3:2608.0001/input/input4 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20240723-miix630-support-v2-1-7d98f6047a17@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29ARM: dts: stm32: Add IWDG2 EXTI interrupt mapping and mark as wakeup sourceMarek Vasut
The IWDG2 is capable of generating pre-timeout interrupt, which can be used to wake the system up from suspend to mem. Add the EXTI interrupt mapping and mark the IWDG2 as wake up source. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-28arm64: dts: ti: k3-am64-phycore-som: Add M4F remoteproc nodesWadim Egorov
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor does not have an MMU, and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240911124251.702590-2-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am62-phycore-som: Add M4F remoteproc nodesWadim Egorov
The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor does not have an MMU, and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240911124251.702590-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space before '{' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240905154440.424488-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am62x-phyboard-lyra: Fix indentation in audio-cardJohn Ma
Corrected the indentation for the audio card node in the phyBOARD-Lyra. Signed-off-by: John Ma <jma@phytec.com> Link: https://lore.kernel.org/r/20240926184849.3341986-1-jma@phytec.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fix bus-width property in MMC ↵John Ma
nodes The bus-width property was moved to k3-am64-main.dtsi. See commit 0ae3113a46a6 ("arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodes") Signed-off-by: John Ma <jma@phytec.com> Link: https://lore.kernel.org/r/20240926184918.3342719-2-jma@phytec.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am64-phycore-som: Fix bus-width property in MMC nodesJohn Ma
The bus-width property was moved to k3-am64-main.dtsi. See commit 0ae3113a46a6 ("arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodes") Signed-off-by: John Ma <jma@phytec.com> Link: https://lore.kernel.org/r/20240926184918.3342719-1-jma@phytec.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am642-evm: Add overlay for PCIe0 EP modeSiddharth Vadapalli
Add overlay to enable the PCIe0 instance of PCIe on AM642-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20240930103413.3085689-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint ModeSiddharth Vadapalli
Add overlay to enable the PCIE1 instance of PCIe on J7200-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20241001093426.3401765-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am62-main: Update otap/itap valuesJudith Mendez
Update itap/itap values according to device datasheet [0]. Now that we have fixed timing issues for am62x [1], lets change the otap/itap values back according to the device datasheet. [0] https://www.ti.com/lit/ds/symlink/am625.pdf [1] https://lore.kernel.org/linux-mmc/20240913185403.1339115-1-jm@ti.com/ Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240924195335.546900-1-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am625-beagleplay: Enable MikroBUS PWMAyush Singh
Add pinmux for PWM functionality of MikroBUS PWM pin and enable the pwm controller. Signed-off-by: Ayush Singh <ayush@beagleboard.org> Link: https://lore.kernel.org/r/20241016-beagleplay-pwm-v1-1-245ae88859bc@beagleboard.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am62-verdin: Fix SD regulator startup delayFrancesco Dolcini
The power switch used to power the SD card interface might have more than 2ms turn-on time, increase the startup delay to 20ms to prevent failures. Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") Cc: stable@vger.kernel.org Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20241024130628.49650-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am62-verdin: Fix SoM ADC compatibleJoão Paulo Gonçalves
Fix Verdin AM62 on-SOM ADC compatible. Currently the hardware is not correctly described in the DT, use the correct TI TLA2024 compatible that matches what is assembled on the board. The "ti,tla2024" compatible was introduced in Linux v5.19 and Verdin AM62 support was introduced in Linux v6.5. The new DTB will not work on kernel older than v5.19, but this seems unlikely to happen. U-Boot does not use the ADC node and a known Android 14 out-of-tree port uses a Linux Kernel 6.1. With that said, despite this being a breaking change, it seems fair to to not expect any regression because of it. Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Link: https://lore.kernel.org/r/20241015113334.246110-1-jpaulo.silvagoncalves@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am625-verdin: add TPM deviceFrancesco Dolcini
Add on-SOM TPM device to the device tree file. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20241018170436.80010-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721s2: Fix clock IDs for MCSPI instancesAnurag Dutta
The clock IDs for multiple MCSPI instances across wakeup domain in J721s2 are incorrect when compared with documentation [1]. Fix the clock IDs to their appropriate values. [1]https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html Fixes: 04d7cb647b85 ("arm64: dts: ti: k3-j721s2: Add MCSPI nodes") Signed-off-by: Anurag Dutta <a-dutta@ti.com> Link: https://lore.kernel.org/r/20241023104532.3438851-4-a-dutta@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721e: Fix clock IDs for MCSPI instancesAnurag Dutta
The clock IDs for multiple MCSPI instances across wakeup domain in J721e are incorrect when compared with documentation [1]. Fix the clock ids to their appropriate values. [1]https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/clocks.html Fixes: 76aa309f9fa7 ("arm64: dts: ti: k3-j721e: Add MCSPI nodes") Signed-off-by: Anurag Dutta <a-dutta@ti.com> Link: https://lore.kernel.org/r/20241023104532.3438851-3-a-dutta@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j7200: Fix clock ids for MCSPI instancesAnurag Dutta
The clock IDs for multiple MCSPI instances across wakeup as well as main domain in J7200 are incorrect when compared with documentation [1]. This results in kernel crashes when the said instances are enabled. Fix the clock ids to their appropriate values. [1]https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html Fixes: 8f6c475f4ca7 ("arm64: dts: ti: k3-j7200: Add MCSPI nodes") Signed-off-by: Anurag Dutta <a-dutta@ti.com> Reviewed-by: Aniket Limaye <a-limaye@ti.com> Link: https://lore.kernel.org/r/20241023104532.3438851-2-a-dutta@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j7200: Fix register map for main domain pmxJared McArthur
Commit 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux range") split the main_pmx0 into two nodes: main_pmx0 and main_pmx1 due to a non-addressable region, but incorrectly represented the ranges. As a result, the memory map for the pinctrl is incorrect. Fix this by introducing the correct ranges. The ranges are taken from the J7200 TRM [1] (Table 5-695. CTRL_MMR0 Registers). Padconfig starting addresses and ranges: - 0 to 66: 0x11c000, 0x10c - 68: 0x11c110, 0x004 - 71 to 73: 0x11c11c, 0x00c - 89 to 90: 0x11c164, 0x008 The datasheet [2] doesn't contain PADCONFIG63 (Table 6-106. Pin Multiplexing), but the pin is necessary for enabling the MMC1 CLKLP pad loopback and should be included in the pinmux register map. Due to the change in pinmux node addresses, change the pinmux node for the USB0_DRVVBUS pin to main_pmx2. The offset has not changed since the new main_pmx2 node has the same base address and range as the original main_pmx1 node. All other pinmuxing done within J7200 dts or dtso files only uses main_pmx0 which has not changed. [1] https://www.ti.com/lit/pdf/spruiu1 [2] https://www.ti.com/lit/gpn/dra821u Fixes: 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux range") Signed-off-by: Aniket Limaye <a-limaye@ti.com> Signed-off-by: Jared McArthur <j-mcarthur@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20240926102533.398139-1-a-limaye@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j7200-evm*: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - pmic regulator for enabling AVS Support - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, hbmc for enabling various bootmodes. Reviewed-by: Aniket Limaye <a-limaye@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-12-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721e-sk*: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, usb0, usb1, ospi0 for enabling various bootmodes. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-11-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721e-evm*: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1, hbmc for enabling various bootmodes. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-10-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-am68-sk*: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, ospi0 for enabling various bootmodes. - eeprom for board detection Reviewed-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-9-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721s2-evm*: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - pmic regulator for enabling AVS Support - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1 for enabling various bootmodes. Reviewed-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-8-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j784s4-j742s2-evm-common: Remove parent nodes bootph-*Manorit Chawdhry
Adding bootph properties on leaf nodes imply that they are applicable to the parent nodes as well. Bootloaders can derive the parent nodes when bootph is available in the leaf nodes. Remove the bootph-* properties from parent nodes as they are redundant. Reviewed-by: Aniket Limaye <a-limaye@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-7-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j7200: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - hbmc_mux for enabling Hyperflash support - ESM nodes for enabling ESM support. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Aniket Limaye <a-limaye@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-6-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721e: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - hbmc_mux for enabling Hyperflash support - ESM nodes for enabling ESM support. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-5-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j721s2: Add bootph-* propertiesManorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-4-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j784s4: Add bootph-* propertiesManorit Chawdhry
The following nodes are being used in the bootloaders. Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-3-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Remove parent nodes bootph-*Manorit Chawdhry
Adding bootph properties on leaf nodes imply that they are applicable to the parent nodes as well. Bootloaders can derive the parent nodes when bootph is available in the leaf nodes. Remove the bootph-* properties from parent nodes as they are redundant. Reviewed-by: Aniket Limaye <a-limaye@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-2-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-28arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Move bootph from mcu_timer1 to ↵Manorit Chawdhry
mcu_timer0 Bootloader are using mcu_timer0 instead of mcu_timer1. Adds bootph to mcu_timer0 instead of mcu_timer1. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-1-2af90e3a4fe7@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2024-10-27dt-bindings: arm: samsung: Document Exynos9810 and starlte board bindingMarkuss Broks
Add the compatibles for Exynos9810 SoC and samsung,starlte board to the list of boards. Samsung Galaxy S9 (SM-G960F, codenamed starlte) is a mobile phone, released in 2018. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241026-exynos9810-v3-6-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-27dt-bindings: soc: samsung: exynos-pmu: Add exynos9810 compatibleMarkuss Broks
Add compatible for Samsung Exynos9810 PMU to the schema. Like on other devices, it contains various registers related to power management and other vital to SoC functions. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241026-exynos9810-v3-5-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-27dt-bindings: arm: cpus: Add Samsung Mongoose M3Markuss Broks
Add the compatible for Samsung Mongoose M3 CPU core to the schema. Mongoose M3 (codenamed Meerkat) is the big core in Exynos9810 SoC, designed by Samsung. It implements ARMv8.2-A ISA. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241026-exynos9810-v3-1-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26arm64: dts: exynos8895: Add spi_0/1 nodesIvaylo Ivanov
Add nodes for spi_0 (SPI_CAM0) and spi_1 (SPI_CAM1), which allows using them. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023091734.538682-6-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26arm64: dts: exynos8895: Add Multi Core Timer (MCT) nodeIvaylo Ivanov
MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023091734.538682-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26arm64: dts: exynos8895: Add clock management unit nodesIvaylo Ivanov
Add clock management unit nodes for: - cmu_top, which provides muxes, divs and gates for other CMUs - cmu_peris, which provides clocks for GIC and MCT - cmu_fsys0, which provides clocks for USBDRD30 - cmu_fsys1, which provides clocks for MMC, UFS and PCIE - cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03 - cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13 Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023091734.538682-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatibleIvaylo Ivanov
Just like most Samsung Exynos SoCs, Exynos8895 uses almost the same Multi-Core Timer block with no functional differences. Add dedicated samsung,exynos8895-mct compatible to the dt-schema for representing the MCT timer of Exynos8895 SoC. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241023091734.538682-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-13 01:29:39 +0000