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2023-07-27drm/i915/color: Upscale degamma values for MTLChaitanya Kumar Borah
MTL onwards Degamma LUT/PRE-CSC LUT precision has been increased from 16 bits to 24 bits. Currently, drm framework only supports LUTs up to 16 bit precision. Until a new uapi comes along to support higher bitdepth, upscale the values sent from userland to 24 bit before writing into the HW to continue supporting degamma on MTL. Add helper function to upscale or downscale lut values. Parameters 'to' and 'from' needs to be less than 32. This should be sufficient as currently there are no lut values exceeding 32 bit. v2: (Jani) - Reuse glk_load_degamma_lut() - Create a helper function for upscaling values v3: Fix multi line comment style (Uma) v4: Remove extra line(Ankit) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230727123342.4077017-1-chaitanya.kumar.borah@intel.com
2023-07-27Merge tag 'drm-misc-next-2023-07-21' of ↵Daniel Vetter
ssh://git.freedesktop.org/git/drm/drm-misc into drm-next drm-misc-next for 6.6: UAPI Changes: - syncobj: New DRM_IOCTL_SYNCOBJ_EVENTFD ioctl Cross-subsystem Changes: - Converge to use of_device_uevent() Core Changes: - GPU VA Manager - improvements to make it clearer that drm_minor_type is uAPI Driver Changes: - ssd130x: Improve intermediate buffer size computation - bridges: - adv7511: Fix low refresh rate - anx7625: Switch to macros instead of hardcoded values - panel: - ld9040: Backlight support, magic improved Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/urs7omo5xnhglztxgwgsslws7duqfj4jhzrtppaenuvdh2lwuz@4htm4iiqhkep
2023-07-27dma-buf: Fix the typo in DMA-BUF statistics docLuc Ma
The kernel-doc for DMA-BUF statistics mentions /sys/kernel/dma-buf/buffers but the correct path is /sys/kernel/dmabuf/buffers instead. Signed-off-by: Luc Ma <luc@sietium.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/64b6749a.170a0220.3acab.2af9@mx.google.com Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
2023-07-26drm/ssd130x: Allocate buffer in the plane's .atomic_check() callbackJavier Martinez Canillas
Drivers are not allowed to fail after drm_atomic_helper_swap_state() has been called and the new atomic state is stored into the current sw state. Since the struct ssd130x_device .data_array is allocated in the encoder's .atomic_enable callback, the operation can fail and this is after the new state has been stored. So it can break an atomic mode settings assumption. Fix this by having custom helpers to allocate, duplicate and destroy the plane state, that will take care of allocating and freeing these buffers. Suggested-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230726105433.389740-2-javierm@redhat.com
2023-07-26drm/ssd130x: Inline the ssd130x_buf_{alloc, free}() function helpersJavier Martinez Canillas
There is only a single caller for both helper functions and these don't do much other than allocate and free two buffers, so let's just inline them. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230726105433.389740-1-javierm@redhat.com
2023-07-26drm/i915/gt: Support aux invalidation on all enginesAndi Shyti
Perform some refactoring with the purpose of keeping in one single place all the operations around the aux table invalidation. With this refactoring add more engines where the invalidation should be performed. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-8-andi.shyti@linux.intel.com
2023-07-26drm/i915/gt: Poll aux invalidation register bit on invalidationJonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to complete by checking the aux invalidation register bit is cleared. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-7-andi.shyti@linux.intel.com
2023-07-26drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the CSAndi Shyti
Enable the CCS_FLUSH bit 13 in the control pipe for render and compute engines in platforms starting from Meteor Lake (BSPEC 43904 and 47112). For the copy engine add MI_FLUSH_DW_CCS (bit 16) in the command streamer. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet") Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-6-andi.shyti@linux.intel.com
2023-07-26drm/i915/gt: Rename flags with bit_group_X according to the datasheetAndi Shyti
In preparation of the next patch align with the datasheet (BSPEC 47112) with the naming of the pipe control set of flag values. The variable "flags" in gen12_emit_flush_rcs() is applied as a set of flags called Bit Group 1. Define also the Bit Group 0 as bit_group_0 where currently only PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-5-andi.shyti@linux.intel.com
2023-07-26drm/i915/gt: Ensure memory quiesced before invalidationJonathan Cavitt
All memory traffic must be quiesced before requesting an aux invalidation on platforms that use Aux CCS. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Requires: a2a4aa0eef3b ("drm/i915: Add the gen12_needs_ccs_aux_inv helper") Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-4-andi.shyti@linux.intel.com
2023-07-26drm/i915: Add the gen12_needs_ccs_aux_inv helperAndi Shyti
We always assumed that a device might either have AUX or FLAT CCS, but this is an approximation that is not always true, e.g. PVC represents an exception. Set the basis for future finer selection by implementing a boolean gen12_needs_ccs_aux_inv() function that tells whether aux invalidation is needed or not. Currently PVC is the only exception to the above mentioned rule. Requires: 059ae7ae2a1c ("drm/i915/gt: Cleanup aux invalidation registers") Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-3-andi.shyti@linux.intel.com
2023-07-26drm/i915/gt: Cleanup aux invalidation registersAndi Shyti
Fix the 'NV' definition postfix that is supposed to be INV. Take the chance to also order properly the registers based on their address and call the GEN12_GFX_CCS_AUX_INV address as GEN12_CCS_AUX_INV like all the other similar registers. Remove also VD1, VD3 and VE1 registers that don't exist and add BCS0 and CCS0. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-2-andi.shyti@linux.intel.com
2023-07-26drm/i915: Use the i915_vma_flush_writes helperTvrtko Ursulin
We can use the existing helper in flush_write_domain() and save some lines of code. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230721130741.1306563-1-tvrtko.ursulin@linux.intel.com
2023-07-26drm/i915/hotplug: Reduce SHPD_FILTER to 250usSuraj Kandpal
On TGP, the RTC (always running) was reduced from 3MHz to 32KHz. As a result of this change, when HPD active going low pulse or HPD IRQ is presented and the refclk (19.2MHz) is not toggling already toggling, there is a 60 to 90us synchronization delay which effectively reduces the duration of the IRQ pulse to less than the programmed 500us filter value and the hot plug interrupt is NOT registered. Solution was to Reduce SHPD_FILTER to 250us for ADL and above. This solution was derived when the below patch was floated. [1]https://patchwork.freedesktop.org/patch/532187 and after some internal discussion Ville's suggestion made sense. Bspec: 68970 Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230720104624.3063544-1-suraj.kandpal@intel.com
2023-07-25drm/ast: Do not enable PCI resources multiple timesThomas Zimmermann
Remove ast_init_pci_config() as the ast driver already enables the PCI resources by calling pcim_enable_device(). Suggested-by: Sui Jingfeng <suijingfeng@loongson.cn> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Tested-by: Sui Jingfeng <suijingfeng@loongson.cn> Link: https://patchwork.freedesktop.org/patch/msgid/20230712130826.3318-1-tzimmermann@suse.de
2023-07-25drm/amdgpu: Restore HQD persistent state registerLijo Lazar
On GFX v9.4.3, compute queue MQD is populated using the values in HQD persistent state register. Hence don't clear the values on module unload, instead restore it to the default reset value so that MQD is initialized correctly during next module load. In particular, preload flag needs to be set on compute queue MQD, otherwise it could cause uninitialized values being used at device reset state resulting in EDC. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/radeon: add missing spaces before ';'Ran Sun
ERROR: space required after that ';' (ctx:BxV) Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/radeon/si_dpm: open brace '{' following struct go on the same lineRan Sun
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metricsWenyou Yang
To acquire the voltage and current info from gpu_metrics interface, but gpu_metrics_v2_3 doesn't contain them, and to be backward compatible, add new gpu_metrics_v2_4 structure. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Wenyou Yang <WenYou.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: load sdma ucode in the guest machineYuanShang
[why] User mode driver need to check the sdma ucode version to see whether the sdma engine supports a new type of PM4 packet. In SRIOV, sdma is loaded by the host. And, there is no way to check the sdma ucode version of CHIP_NAVI12 and CHIP_SIENNA_CICHLID of the host in the guest machine. [how] Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID in the guest machine. Signed-off-by: YuanShang <YuanShang.Mao@amd.com> Reviewed-By: Horace Chen <horace.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Use seq_puts() instead of seq_printf()Srinivasan Shanmugam
For a constant format without additional arguments, use seq_puts() instead of seq_printf(). Also, it fixes the following warning. WARNING: Prefer seq_puts to seq_printf And other style fixes: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Block comments should align the * on each line Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Update min() to min_t() in 'amdgpu_info_ioctl'Srinivasan Shanmugam
Fixes the following: WARNING: min() should probably be min_t(size_t, size, sizeof(ip)) + ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); And other style fixes: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Missing a blank line after declarations Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Remove else after return in 'is_fru_eeprom_supported'Srinivasan Shanmugam
Expressions under 'else' branch under case 'CHIP_SIENNA_CICHLID' in function 'is_fru_eeprom_supported' are executed whenever the expression in 'if' is False. Otherwise, return from case occurs. Therefore, there is no need in 'else', and it has been removed. Fixes the following: WARNING: else is not generally useful after a break or return + return false; + } else { Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Remove else after return in 'dm_vblank_get_counter' & ↵Srinivasan Shanmugam
'amdgpu_dm_backlight_get_level' Expressions under 'else' branch in function 'dm_vblank_get_counter' & 'amdgpu_dm_backlight_get_level' are executed whenever the expression in 'if' is False. Otherwise, return from function occurs. Therefore, there is no need in 'else', and it has been removed. Fixes the following: WARNING: else is not generally useful after a break or return + return 0; + else { WARNING: else is not generally useful after a break or return + return convert_brightness_to_user(&caps, avg); + } else { Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Add -ENOMEM error handling when there is no memorySrinivasan Shanmugam
Return -ENOMEM, when there is no sufficient dynamically allocated memory Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Check APU flag to disable RASStanley.Yang
Only disable RAS by default for aqua vanjaram on APU platform. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: fix the indexing issue during rlcg access ctrl initShiwu Zhang
In case that the GET_INST() is used for looping, only loops for the times of actual num of xcc, otherwise GET_INST() will return the invalid index, a.k.a -1 And also remove the redundant mask checking in case of GET_INST() Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: add VISIBLE info in amdgpu_bo_print_infoPierre-Eric Pelloux-Prayer
This allows tools to distinguish between VRAM and visible VRAM. Use the opportunity to fix locking before accessing bo. v2: squash in unused variable fix Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdkfd: avoid svm dump when dynamic debug disabledAlex Sierra
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists from svm_range_debug_dump when dynamic debug is disabled. Otherwise, it could drop performance, specially with big number of SVM ranges. Make sure both svm_range_set_attr and svm_range_debug_dump functions are dynamically enabled to print svm_range_debug_dump debug traces. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Tested-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/radeon: ERROR: "foo * bar" should be "foo *bar"Ran Sun
Fix two occurrences of the checkpatch.pl error: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: open brace '{' following struct go on the same lineRan Sun
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/pm: open brace '{' following struct go on the same lineRan Sun
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd: open brace '{' following struct go on the same lineRan Sun
Fix the checkpatch error as open brace '{' following struct should go on the same line. Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Unlock on error path in ↵Dan Carpenter
dm_handle_mst_sideband_msg_ready_event() This error path needs to unlock the "aconnector->handle_mst_msg_ready" mutex before returning. Fixes: bb4fa525f327 ("drm/amd/display: Add polling method to handle MST reply packet") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: 3.2.244Aric Cyr
This version brings along following fixes: - Fix underflow issue on 175hz timing - Add interface to modify DMUB panel power options - Remove check for default eDP panel_mode - Add new sequence for 4-lane HBR3 on vendor specific retimers - Update DPG test pattern programming - Correct unit conversion for vstartup - Exit idle optimizations before attempt to access PHY - Refactor recout calculation with a more generic formula - Read down-spread percentage from lut to adjust dprefclk. - Don't apply FIFO resync W/A if rdivider = 0 - Prevent invalid pipe connections - Rearrange dmub_cmd defs order - Add VESA SCR case for default aux backlight - Guard DCN31 PHYD32CLK logic against chip family - Correct grammar mistakes Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Fix underflow issue on 175hz timingLeo Ma
[Why] Screen underflows happen on 175hz timing for 3 plane overlay case. [How] Based on dst y prefetch value clamp to equ or oto for bandwidth calculation. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Leo Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Add interface to modify DMUB panel power optionsPaul Hsieh
[Why] This option can vary depending on the panel and may be required to be called during sink detection phase before transmitter control. [How] Allow modify the bit depending on the eDP panel connected with a new interface. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Rearrange dmub_cmd defs orderAnthony Koo
- Rearranged defs order Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Anthony Koo <anthony.koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Remove check for default eDP panel_modeTaimur Hassan
[Why] DPCD read is skipped first time after driver initialization. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Fix style issues in amdgpu_gem.cSrinivasan Shanmugam
Fixes the following to align to linux coding style: WARNING: braces {} are not necessary for any arm of this statement WARNING: Missing a blank line after declarations ERROR: space prohibited before that close parenthesis ')' WARNING: unnecessary whitespace before a quoted newline WARNING: %LX is non-standard C, use %llX Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Add new sequence for 4-lane HBR3 on vendor specific retimersOvidiu Bunea
[Why] In some vendor specific retimer setups for downstream 4-lane HBR3 configuration, the sink will show severe corruption (horizontal shifting) and intermittent blanking. [How] Add new retimer programming sequence before clock recovery when 4 lanes are active. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Update DPG test pattern programmingWenjing Liu
[Why] Last ODM slice could be slightly larger than other slice because it can be including the residual. [How] Update DPG pattern programming sequence to use a different width for last odm slice. Reviewed-by: Chris Park <chris.park@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Correct unit conversion for vstartupReza Amini
[Why] vstartup is calculated to be a large number. It works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [How] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Reza Amini <reza.amini@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Exit idle optimizations before attempt to access PHYLeo Chen
[Why & How] DMUB may hang when powering down pixel clocks due to no dprefclk. It is fixed by exiting idle optimization before the attempt to access PHY. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Refactor recout calculation with a more generic formulaWenjing Liu
[Why] Current recout calculation has a few assumptions and implementation for MPO + ODM combine calculation is very specific. The equation has too many cases without enough comments to document the detail. [How] The change remove the following assumptions: 1. When MPO is enabled, we only allow ODM Combine 2:1 2. ODM Combine always has even segment width. 3. Secondary MPO plane's pipe_ctx copies pre_odm_pipe from its top pipe. The change applies a generic formula with more details in comment to document this solution so it is eaiser to learn and debug later. Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Read down-spread percentage from lut to adjust dprefclk.Martin Tsai
[Why] Panels show corruption with high refresh rate timings when ss is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Martin Tsai <martin.tsai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Don't apply FIFO resync W/A if rdivider = 0Alvin Lee
[Description] It is not valid to set the WDIVIDER value to 0, so do not re-write to DISPCLK_WDIVIDER if the current value is 0 (i.e., it is at it's initial value and we have not made any requests to change DISPCLK yet). Reviewed-by: Saaem Rizvi <syedsaaem.rizvi@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amd/display: Prevent invalid pipe connectionsEthan Bitnun
[Description] - Prevent ODM pipe connections between pipes that are not part of the same plane when adding a plane to context - Re-attach child pipes of ODM slice about to be disconnected to prevent any lost pipes with invalid tops/bottoms - We cannot split if head_pipe is not in ODM. Preventing this avoids creating an invalid context with an invalid pipe. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ethan Bitnun <ethan.bitnun@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Update ring scheduler info as neededLijo Lazar
Not all rings have scheduler associated. Only update scheduler data for rings with scheduler. It could result in out of bound access as total rings are more than those associated with particular IPs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-25drm/amdgpu: Enabling FW workaround through shared memory for VCN4_0_2sguttula
This patch will enable VCN FW workaround using DRM KEY INJECT WORKAROUND method, which is helping in fixing the secure playback. Signed-off-by: sguttula <Suresh.Guttula@amd.com> Reviewed-by: Leo Liu <leo.liiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-11 22:58:40 +0000