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2018-12-04ARM: dts: r8a7744-iwg20m: Enable SDHI0 controllerBiju Das
Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Add eMMC supportBiju Das
Add eMMC support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add MMC nodeBiju Das
Add MMC node to the DT of the r8a7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SDHI nodesBiju Das
Add SDHI nodes to the DT of the r8a7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add I2C and IIC supportBiju Das
Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add [H]SCIF{A|B} supportBiju Das
Describe [H]SCIF{|A|B} ports in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SMP supportBiju Das
Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Also add cpu1 phandle node to the PMU interrupt-affinity property. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add Ethernet AVB supportBiju Das
Add Ethernet AVB support for R8A7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add GPIO supportBiju Das
Describe GPIO blocks in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SYS-DMAC supportBiju Das
Describe SYS-DMAC0/1 in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1NBiju Das
Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Initial SoC device treeBiju Das
Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOMBiju Das
Add support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7743: Remove legacy "renesas,rcar-thermal" compatibilityGeert Uytterhoeven
The thermal hardware description for the RZ/G1M SoC was added to its DTS after the introduction of support for thermal zones, and included a thermal-zones node from the beginning. Hence there is no need to claim compatibility with "renesas,rcar-thermal", which would be needed only for backwards compatibility with kernels predating thermal zone support. Fixes: 6c76b4f7d89e89f0 ("ARM: dts: r8a7743: Add thermal device to DT") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: suniv: Add device tree for Lichee Pi NanoMesih Kilinc
Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-04ARM: dts: suniv: add initial DTSI file for F1C100sMesih Kilinc
F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-03arm64: dts: qcom: msm8996: Add CAMSS supportTodor Tomov
Add a node for the Camera Subsystem present on the Qualcomm MSM8996 SoC. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03arm64: dts: qcom: msm8996: Add VFE SMMU nodeTodor Tomov
Add VFE SMMU node. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03arm64: dts: qcom: Add pinctrls for camera sensorsTodor Tomov
Add pinctrls required for camera sensors: - power down signal; - reset signal; - camera external clock. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03arm64: dts: qcom: Add Camera Control Interface pinctrlsTodor Tomov
Add pinctrls required for Camera Control Interface. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03arm64: dts: qcom: msm8916: Add CAMSS supportTodor Tomov
Add a node for the Camera Subsystem present on the Qualcomm MSM8916 SoC. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03arm64: dts: qcom: msm8916: Add IOMMU sub-node for VFE context bankTodor Tomov
Add IOMMU sub-node for VFE secure context bank. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03arm64: dts: msm8916: Add all CPUs in cooling mapsViresh Kumar
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-03ARM: dts: pxa3xx: Add Raumfeld DTS filesDaniel Mack
This patch adds a set of DTS files that support all PXA3xx based Raumfeld audio hardware devices. Common nodes are factored out into 'common' and 'tuneable-clock' include files to keep the top-level DTS files smaller. Signed-off-by: Daniel Mack <daniel@zonque.org> [Robert: Reordered Makefile in alphabetical order] Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2018-12-03Merge tag 'qcom-dts-for-4.21' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.21 * Add entry for Qualcomm TSENS thermal drivers * Update msm8974 thermal entries * Fix msm8974 Hammerhead magnetometer gpios * Add SoC specific compatibles for SDHC nodes * Remove Arrow SD600 eval board * tag 'qcom-dts-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: qcom: Remove Arrow SD600 eval board ARM: dts: qcom: Add SoC-specific string for sdhci-msm-v4 nodes ARM: dts: qcom: msm8974-hammerhead: correct gpios property on magnetometer ARM: dts: msm8974: thermal: Add "qcom,sensors" property ARM: dts: msm8974: thermal: split address space into two MAINTAINERS: Add entry for Qualcomm TSENS thermal drivers Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03Merge tag 'qcom-arm64-for-4.21' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm ARM64 Updates for v4.21 * Add QCS404 base platform and nodes * Add QCS404 EVB boards * Add external SD and dependencies for MSM8998-mtp * Add default scm compatible for MSM8998 * Fix XO clk name on MSM8998 * Add prng-ee nodes for SDM845 and MSM8996 * Add ADC die temp node for pm8998 * Fix documentation on QCOM ADC sample * tag 'qcom-arm64-for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (34 commits) arm64: dts: qcom: msm8998: Fix compatible of scm node arm64: dts: qcom: msm8998: Add SDC2 control pins arm64: dts: qcom: msm8998-mtp: Add external SD arm64: dts: qcom: msm8998: Add SDCC2 arm64: dts: qcom: msm8998: correct xo clock name arm64: dts: qcom: pms405: Add pon and pwrkey nodes arm64: dts: qcom: qcs404: Use BAM DMA for serial uart2 arm64: dts: qcom: qcs404: Add BAM DMA node arm64: dts: qcom: qcs404: add prng-ee node arm64: dts: qcom: qcs404: Add remoteproc nodes arm64: dts: qcom: qcs404: Add scm firmware node arm64: dts: qcom: pms405: add gpios arm64: dts: qcom: pms405: add rtc node arm64: dts: qcom: qcs404: add spmi node arm64: dts: qcom: pms405: add spmi node arm64: dts: qcom: qcs404: Add sdcc1 node arm64: dts: qcom: qcs404: Add TLMM pinctrl node arm64: dts: qcom: qcs404: add smp2p nodes arm64: dts: qcom: qcs404: Add PMS405 RPM regulators arm64: dts: qcom: qcs404: Add RPM GLINK related nodes ... Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03ARM: mmp2: DT: be compatible with mrvl,mmp2Lubomir Rintel
There are more boards that can work with mmp2-dt than just Brownstone. The OLPC XO-1.75 device tree root is compatible with "mrvl,mmp2" only. The "mrvl,mmp2-brownstone" string is safe to remove: the Brownstone device tree contains the "mrvl,mmp2" compatible string too. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03Merge tag 'arm-soc/for-4.21/devicetree' of ↵Olof Johansson
https://github.com/Broadcom/stblinux into next/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 4.21, please pull the following: - Rafal relicenses a bunch of DTS files he wrote under the GPL 2.0+/MIT license and adds proper SPDX license tags in the process - Rene adds support for the Linksys EA6500 v2 Wi-Fi router based on BCM4708 plus two BCM4360 and BCM4331 radios - Phil documents and updates the vchiq mailbox compatible string in order to establish a correct agreement between the Raspberry Pi firmware and the ARM CPU's view of what an ARM CPU cache line size is, he also fixes the mailbox "reg" property to be correctly expressed in bytes - Stefan updates the Raspberry Pi Zero DTS files to use SPDX tags - Florian enables the SATA PHY and AHCI controller on the BCM63138 SoCs, he also does a bit of refactoring of aliases for the Northstar Plus DTS files * tag 'arm-soc/for-4.21/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: BCM5301X: Describe Northstar pins mux controller ARM: dts: BCM5301X: Add basic DT for Linksys EA6500 V2 ARM: dts: bcm2835-rpi-zero: Switch to SPDX identifier ARM: dts: bcm283x: Correct mailbox register sizes ARM: dts: bcm283x: Correct vchiq compatible string dt-bindings: soc: Document "brcm,bcm2836-vchiq" ARM: dts: NSP: Move aliases to bcm-nsp.dtsi ARM: dts: BCM53573: Relicense SoC file to the GPL 2.0+ / MIT ARM: dts: BCM63xx: Enable SATA AHCI and PHY for BCM963138DVT ARM: dts: BCM63xx: enable SATA PHY and AHCI controller ARM: dts: BCM53573: Relicense Tenda AC9 file to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense BCM47094 file to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense BCM47081/BCM4709 files to the GPL 2.0+ / MIT Signed-off-by: Olof Johansson <olof@lixom.net>
2018-12-03clk: imx: add imx7ulp clk driverA.s. Dong
i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. This driver only adds clock support in A7 domain. Note that most clocks required to be operated when gated, e.g. pll, pfd, pcc. And more special cases that scs/ddr/nic mux selecting different clock source requires that clock to be enabled first, then we need set CLK_OPS_PARENT_ENABLE flag for them properly. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: implement new clk_hw based APIsA.s. Dong
Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: make mux parent strings constA.s. Dong
As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of 'imx_clk_mux_flags' discards 'const' qualifier from pointer target type clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); ^ In file included from drivers/clk/imx/clk-imx7ulp.c:23:0: drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is of type 'const char * const*' ... Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03dt-bindings: clock: add imx7ulp clock binding docA.s. Dong
i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add imx7ulp composite clk supportA.s. Dong
The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add pfdv2 supportA.s. Dong
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add pllv4 supportA.s. Dong
pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag supportA.s. Dong
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b - Divide by 2. 010b - Divide by 3. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add gatable clock divider supportA.s. Dong
For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set rate when the clk is disabled will cache the rate request and only when the clk is enabled will the driver actually program the hardware to have the requested divider value. Similarly, when the clk is disabled we'll write a 0 there, but when the clk is enabled we'll restore whatever rate (divider) was chosen last. It does mean that recalc rate will be sort of odd, because when the clk is off it will return 0, and when the clk is on it will return the right rate. So to make things work, we'll need to return the cached rate in recalc rate when the clk is off and read the hardware when the clk is on. NOTE for the default off divider, the recalc rate will still return 0 as there's still no proper preset rate. Enable such divider will give user a reminder error message. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03ARM: dts: exynos: Add opp-suspend to DMC and leftbus devfreq OPPs on Exynos4Lukasz Luba
Mark as opp-suspend required devfreq Operating Performance Points to fix resuming issues on Exynos 4 boards. The patch is based on earlier work by Tobias Jakobi. Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Suggested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2018-12-03arm64: tegra: Add temperature sensor on P2888Thierry Reding
The P2888 processor module contains a TI TMP451 temperature sensor with two channels. These are used to measure the temperatures at different locations on the module. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Add gpio-keys on Jetson XavierThierry Reding
The power and force recovery buttons found on Jetson Xavier are hooked up to two Tegra GPIOs. The power button can also function as a wake-up source. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Add AON GPIO controller on Tegra194Thierry Reding
The AON GPIO controller is in an always-on power partition and typically provides pins for functions that need to always work, such as the power key for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: p2888: Enable on-die RTCThierry Reding
The on-die RTC isn't hooked up to a backup battery, so it isn't useful to track time across reboots, but as long as power remains enabled, it keeps track of time accurately and can be used to wake the system from sleep, for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Add RTC support on Tegra194Thierry Reding
The RTC on Tegra194 is very similar to the RTC on earlier generations. One notable exception is that the source clock is now the 32 kHz clock instead of a dedicated RTC clock and the RTC alarm is a wake event and can be used to wake the system from sleep. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Enable PMC wake events on Tegra194Thierry Reding
Wake events are a feature that allows the interrupt and GPIO controllers to be powered off as part of system sleep. The PMC which is always on is monitoring these wake events and can power up subsequent controllers as necessary to process them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: p3310: Enable on-die RTCThierry Reding
The on-die RTC isn't hooked up to a backup battery, so it isn't useful to track time across reboots, but as long as power remains enabled, it keeps track of time accurately and can be used to wake the system from sleep, for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Add RTC support on Tegra186Thierry Reding
The RTC on Tegra186 is very similar to the RTC on earlier generations. One notable exception is that the source clock is now the 32 kHz clock instead of a dedicated RTC clock and the RTC alarm is a wake event and can be used to wake the system from sleep. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Enable PMC wake events on Tegra186Thierry Reding
Wake events are a feature that allows the interrupt and GPIO controllers to be powered off as part of system sleep. The PMC which is always on is monitoring these wake events and can power up subsequent controllers as necessary to process them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Fix power key interrupt type on Jetson TX2Thierry Reding
In order for the correct interrupt type to be configured, the event action for the power key needs to be "asserted". Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: p2972: Enable the CPU, GPU and AUX thermal zonesThierry Reding
Enable these thermal zones to be able to monitor their temperatures and control the fan to cool down the system if necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03arm64: tegra: Add thermal zones on Tegra194Thierry Reding
The NVIDIA Tegra194 SoC defines six thermal zones. Define all of them in device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit (git 2.34.1) at 2025-09-11 21:48:04 +0000