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2016-02-27drm/radeon: Return -EPROBE_DEFER when amdkfd not loadedOded Gabbay
radeon must load only after amdkfd's loading has been completed. If that is not enforced, then radeon's call into amdkfd's functions will cause a kernel BUG. When radeon and amdkfd are built as kernel modules, that rule is enforced by the kernel's modules loading mechanism. When radeon and amdkfd are built inside the kernel image, that rule is enforced by ordering in the drm Makefile (amdkfd before radeon). Instead of using drm Makefile ordering, we can now use deferred loading as amdkfd now returns -EPROBE_DEFER in kgd2kfd_init() when it is not yet loaded. This patch defers radeon loading by propagating -EPROBE_DEFER to the kernel's drivers loading infrastructure. That will put radeon into the pending drivers list (see description in dd.c). Once amdkfd is loaded, a call to kgd2kfd_init() will return successfully and radeon will be able to load. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-27drm/amdkfd: Track when module's init is completeOded Gabbay
Current dependencies between amdkfd and radeon/amdgpu force the loading of amdkfd _before_ radeon and/or amdgpu are loaded. When all these kernel drivers are built as modules, this ordering is enforced by the kernel built-in mechanism of loading dependent modules. However, there is no such mechanism in case where all these drivers are compiled inside the kernel image (not as modules). The current way to enforce loading of amdkfd before radeon/amdgpu, is to put amdkfd before radeon/amdgpu in the drm Makefile, but that method is way too fragile. In addition, there is no kernel mechanism to check whether a kernel driver that is built inside the kernel image, has already been loaded. To solve this, this patch adds to kfd_module.c a new static variable, amdkfd_init_completed, that is set to 1 only when amdkfd's module initialization function has been completed (successfully). kgd2kfd_init(), which is the initialization function of the kgd-->kfd interface, and which is the first function in amdkfd called by radeon/amdgpu, will return successfully only if amdkfd_init_completed is equal 1. If amdkfd_init_completed is not equal to 1, kgd2kfd_init() will return -EPROBE_DEFER to signal radeon/amdgpu they need to defer their loading until amdkfd is loaded. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-26drm/i915: Execlists cannot pin a context without the objectChris Wilson
Given that the intel_lr_context_pin cannot succeed without the object, we cannot reach intel_lr_context_unpin() without first allocating that object - so we can remove the redundant test. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456485751-15213-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-02-26drm/i915: Reduce the pointer dance of i915_is_ggtt()Chris Wilson
The multiple levels of indirect do nothing but hinder the compiler and the pointer chasing turns to be quite painful but painless to fix. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456484600-11477-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-02-26drm/i915: Rename vma->*_list to *_link for consistencyChris Wilson
Elsewhere we have adopted the convention of using '_link' to denote elements in the list (and '_list' for the actual list_head itself), and that the name should indicate which list the link belongs to (and preferrably not just where the link is being stored). s/vma_link/obj_link/ (we iterate over obj->vma_list) s/mm_list/vm_link/ (we iterate over vm->[in]active_list) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2016-02-26drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)Chris Wilson
commit 09731280028ce03e6a27e1998137f1775a2839f3 Author: Imre Deak <imre.deak@intel.com> Date: Wed Feb 17 14:17:42 2016 +0200 drm/i915: Add helper to get a display power ref if it was already enabled left the rpm wakelock assertions unbalanced if CONFIG_PM was disabled as intel_runtime_pm_get_if_in_use() would return true without incrementing the local bookkeeping required for the assertions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> CC: Mika Kuoppala <mika.kuoppala@intel.com> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456434628-22574-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-02-26drm/i915/lrc: Only set RS ctx enable in ctx control reg if there is a RSMichel Thierry
The driver should only set the "RS context enable" bit in the context image if we plan to use the resource streamer. Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456393738-35608-1-git-send-email-michel.thierry@intel.com
2016-02-26drm/i915/gen9: Set value of Indirect Context Offset based on gen versionMichel Thierry
The cache line offset for the Indirect CS context (0x21C8) varies from gen to gen. v2: Move it into a function (Arun), use MISSING_CASE (Chris) v3: Rebased (catched by ci bat) Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456223509-6454-1-git-send-email-michel.thierry@intel.com
2016-02-26Merge branch 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu into ↵Dave Airlie
drm-next As previously discussed, this is my first pull request for the DCU DRM driver along with the change in MAINTAINERS. https://lkml.org/lkml/2016/1/7/26 The pull contains some code cleanup changes (e.g. removing all error handling for the regmap calls) and several fixes. * 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu: drm/fsl-dcu: fix register initialization drm/fsl-dcu: use mode flags for hsync/vsync polarity drm/fsl-dcu: fix alpha blending drm/fsl-dcu: mask all interrupts on initialization drm/fsl-dcu: handle initialization errors properly drm/fsl-dcu: avoid memory leak on errors drm/fsl-dcu: remove regmap return value checks drm/fsl-dcu: specify volatile registers drm: fsl-dcu: Fix no fb check bug MAINTAINERS: update for Freescale DCU DRM driver
2016-02-25drm/fsl-dcu: fix register initializationStefan Agner
The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for Vybrid) whereas the register enumeration start from 1 (1-10 for LS1021a and 1-9 for Vybrid). The loop started off from 0 for both iterations and initialized the number of layers inclusive, which is one layer too many. All extensively written registers seem to be unassigned, it seems that the write to those registers did not do any harm in practice. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: use mode flags for hsync/vsync polarityStefan Agner
The current default configuration is as follows: - Invert VSYNC signal (active LOW) - Invert HSYNC signal (active LOW) The mode flags allow to specify the required polarity per mode. Furthermore, none of the current driver settings is actually a standard polarity. This patch applies the current driver default polarities as explicit flags to the display which has been introduced with the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now also parses the flags field and applies the configuration accordingly, by using the following values as standard polarities: (e.g. when no flags are specified): - VSYNC signal not inverted (active HIGH) - HSYNC signal not inverted (active HIGH) Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: fix alpha blendingStefan Agner
Fix alpha blending by enabling alpha blending for the whole frame if a color mode with alpha channel is selected (DRM_FORMAT_ARGB*). Also support color modes without alpha channel (DRM_FORMAT_XRGB*) by just not enabling alpha blending on layer level. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: mask all interrupts on initializationStefan Agner
The state of the interrupt mask register on initialization is unknown, e.g. U-Boot could already used the DCU. So depending on the boot loader, the outcome of the interrupt mask register could be different. A defined state is much more preferable. Also, there is no value in keeping interrupts enabled which we don't need. Therefor, mask all interrupts on initialization. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: handle initialization errors properlyStefan Agner
If initialization fails (e.g. due to missing panel node or deferred probe) make sure to roll-back all operations and return the error code. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: avoid memory leak on errorsStefan Agner
Improve error handling during CRTC initialization. Especially avoid memory leaks in the primary plane initialization error path. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: remove regmap return value checksStefan Agner
It is not common to do regmap return value checks, especially not for memory mapped device. We can rule out most error returns since the conditions are static and we know they are ok (e.g. offset aligned to register stride). Also without proper error handling they are not really valuable for the user. Hence remove most of them. The check in the interrupt handler is worth keeping since a volatile register won't be readable in case register caching is still enabled. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: specify volatile registersStefan Agner
Since we are using cached registers, we need to specify volatile registers explicitly to avoid reading their value from the cache. This allows to read the correct interrupt status in fsl_dcu_drm_irq and clear the asserted bits only. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm: fsl-dcu: Fix no fb check bugMeng Yi
For state->fb or state->crtc may be NULL in fsl_dcu_drm_plane_atomic_check function, if so, return 0. Signed-off-by: Meng Yi <meng.yi@nxp.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25MAINTAINERS: update for Freescale DCU DRM driverStefan Agner
Promote myself as new maintainer of the Freescale DCU DRM driver. Acked-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/i915: Remove update_sprite_watermarks.Maarten Lankhorst
Commit 791a32be6eb2 ("drm/i915: Drop intel_update_sprite_watermarks") removes the use of this variable, but forgot to remove it. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455108583-29227-5-git-send-email-maarten.lankhorst@linux.intel.com
2016-02-25drm/tilcdc: Use devm_kzalloc() and devm_kcalloc() for private dataJyri Sarha
Use devm_kzalloc() and devm_kcalloc() for private data allocation at driver load time. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Initialize crtc->portJyri Sarha
Initialize port device node pointer in the tilcdc crtc. Fixes "Falling back to first CRTC" warning from tda998x driver. The tda998x encoder driver calls drm_of_find_possible_crtcs() to initialize possible_crtcs of struct drm_encoder. The crtc->port needs to be initialized for drm_of_find_possible_crtcs() to work. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Disable sync lost interrupt if it fires on every frameJyri Sarha
Disable the sync lost interrupt if it fires on every frame for 50 consecutive frames in a row. This is relatively sure sign of the sync lost interrupt being stuck and firing on every frame even if the display otherwise appears to work OK. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Add prints on sync lost and FIFO underrun interruptsJyri Sarha
Add ratelimited prints on sync lost and FIFO underrun interrupts. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Remove the duplicate LCDC_INT_ENABLE_SET_REG in registers[]Jyri Sarha
Removes the duplicate LCDC_INT_ENABLE_SET_REG-entry in registers array. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Fix interrupt enable/disable code for version 2 tilcdcJyri Sarha
Fix interrupt enable/disable code for version 2 tilcdc. In version 2 tilcdc there is a separate register for disabling interrupts. Writing 0 to enable registers bits does not have any effect. The interrupt clear register works the same way, writing 1 to specific bit disables the interrupt and writing 0 does not have any effect. The "bug" that is fixed here does not really do any harm since the interrupts are enabled only once in the power up and disabled before power down. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Do not update the next frame buffer close to vertical blankTomi Valkeinen
Do not update the next frame buffer close to vertical blank. This is to avoid situation when the frame changes between writing of LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: Get rid of complex ping-pong mechanismTomi Valkeinen
Get rid of complex ping-pong mechanism and replace it with simpler single buffer flipping code. The LCDC HW appears to be designed mainly static framebuffers in mind. There are two modes of operation, either static single buffer, or ping pong double buffering with two static buffers switching back and forth. Luckily the framebuffer start address is fetched only in the beginning of the frame and changing the address after that only takes effect after the next vertical blank. The page flipping code can simply write the address of the new framebuffer and the page is flipped automatically after the next vertical blank. Using the ping pong double buffering makes the flipping code way more complex and it does not provide any benefit, so it is better to switch to single buffer operation. There is still one problem in updating the framebuffer dma address on the fly. There are two registers defining the framebuffer dma area and things may break if the dma address is fetched in while the registers are are being updated. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: cleanup irq handlingTomi Valkeinen
Cleanup irq handling. Clear the irq status unconditionally and restructure the status bit conditions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: remove broken error handlingTomi Valkeinen
Remove broken error handling. The condition for handling the LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW could never be satisfied as the LCDC_SYNC_LOST interrupt is not enabled. Also the requirement to have both LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW fired at once before handling the error looks weird. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: split reset to a separate functionTomi Valkeinen
Split reset to a separate function and use usleep_range(250, 1000) instead of msleep(1) to to keep the reset bit on long enough. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch, changed mdelay(500) to usleep_range(250, 1000)] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: disable crtc on unloadTomi Valkeinen
Disable crtc on unload. Call tilcdc_crtc_dpms() with DRM_MODE_DPMS_OFF in the beginning of unload function. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: cleanup runtime PM handlingTomi Valkeinen
Cleanup runtime PM handling. Before the patch the usage of pm_runtime calls was inconsistent and hard to follow. After the update the pm_runtime calls are removed from set_scanout() and called around major operations that access the HW. After the patch the DPMS code does not have pm_runtime_forbid/allow calls any more and pm_runtime_irq_safe() is not set anymore. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: Allocate register storage based on the actual number registersJyri Sarha
Allocate suspend/resume register storage based on the actual number registers the driver is aware of. The static allocation for register storage had fallen behind badly. Reported-by: Michael Bode <michael@bumbleB.de> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: fix build error when !CONFIG_CPU_FREQGrygorii Strashko
Fix build error when !CONFIG_CPU_FREQ drivers/gpu/drm/tilcdc/tilcdc_drv.c: In function 'tilcdc_load': drivers/gpu/drm/tilcdc/tilcdc_drv.c:327:1: error: label 'fail_put_clk' defined but not used [-Werror=unused-label] fail_put_clk: ^ Signed-off-by: Grygorii Strashko <Grygorii.Strashko@linaro.org> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Implement dma-buf support for tilcdcJyri Sarha
There is nothing special about tilcdc HW when the video memory is concerned. Just using the standard drm helpers for implementation is enough. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: disable the lcd controller/dma engine when suspend invokedDarren Etheridge
The LCD controller must be deactivated and all DMA transactions stopped when the suspend power state is entered otherwise the PRCM causes the L3 bus to get stuck in transition state. This commit forces the lcdc to be shut down and waits for all pending DMA transactions to complete as part of the suspend handler for this driver. Signed-off-by: Darren Etheridge <detheridge@ti.com> Tested-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: make frame_done interrupt active at all timesDarren Etheridge
The frame_done interrupt was only being enabled when the vsync interrupts were being enabled by DRM. However the frame_done is used to determine if the LCD controller has successfully completed the raster_enable, raster_disable commands and the vsync interrupts are not always enabled during these operations. Signed-off-by: Darren Etheridge <detheridge@ti.com> Tested-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: fix kernel panic on suspend when no hdmi monitor connectedDarren Etheridge
On BeagleBone Black if no HDMI monitor is connected and suspend is requested a kernel panic will result: root@am335x-evm:~# echo mem > /sys/power/state [ 65.548710] PM: Syncing filesystems ... done. [ 65.631311] Freezing user space processes ... (elapsed 0.006 seconds) done. [ 65.648619] Freezing remaining freezable tasks ... (elapsed 0.005 seconds) done. [ 65.833500] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa30e004 [ 65.841692] Internal error: : 1028 [#1] SMP ARM <snip> [ 66.105287] [<c03765f0>] (platform_pm_suspend) from [<c037b6d4>] (dpm_run_callback+0x34/0x70) [ 66.114370] [<c037b6d4>] (dpm_run_callback) from [<c037ba84>] (__device_suspend+0x10c/0x2f4) [ 66.123357] [<c037ba84>] (__device_suspend) from [<c037d004>] (dpm_suspend+0x58/0x218) [ 66.131796] [<c037d004>] (dpm_suspend) from [<c008d948>] (suspend_devices_and_enter+0x9c/0x3c0) [ 66.141055] [<c008d948>] (suspend_devices_and_enter) from [<c008de7c>] (pm_suspend+0x210/0x24c) [ 66.150312] [<c008de7c>] (pm_suspend) from [<c008cabc>] (state_store+0x68/0xb8) [ 66.158103] [<c008cabc>] (state_store) from [<c02e9654>] (kobj_attr_store+0x14/0x20) [ 66.166355] [<c02e9654>] (kobj_attr_store) from [<c0185c70>] (sysfs_kf_write+0x4c/0x50) [ 66.174883] [<c0185c70>] (sysfs_kf_write) from [<c018926c>] (kernfs_fop_write+0xb4/0x150) [ 66.183598] [<c018926c>] (kernfs_fop_write) from [<c0122638>] (vfs_write+0xa8/0x180) [ 66.191846] [<c0122638>] (vfs_write) from [<c01229f8>] (SyS_write+0x40/0x8c) [ 66.199365] [<c01229f8>] (SyS_write) from [<c000e580>] (ret_fast_syscall+0x0/0x48) [ 66.207426] Code: e595c210 e5932000 e59cc000 e08c2002 (e592c000) This is because the lcdc module is not enabled when no monitor is detected to save power. However the suspend handler just blindly tries to save the lcdc state by copying out the pertinent registers. However module is off so no good things happen when you try and access it. This patch only saves off the registers if the module is enabled, and then only restores the registers on resume if they were saved off during suspend. Signed-off-by: Darren Etheridge <detheridge@ti.com> Tested-by: Dave Gerlach <d-gerlach@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: adopt pinctrl supportDave Gerlach
Update tilcdc driver to set the state of the pins to: - "default on resume - "sleep" on suspend By optionally putting the pins into sleep state in the suspend callback we can accomplish two things. - minimize current leakage from pins and thus save power, - prevent the IP from driving pins output in an uncontrolled manner, which may happen if the power domain drops the domain regulator. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: verify fb pitchTomi Valkeinen
LCDC hardware does not support fb pitch that is different (i.e. larger) than the screen size. The driver currently does no checks for this, and the results of too big pitch are are flickering and lower fps. This issue easily happens when using libdrm's modetest tool with non-32 bpp modes. As modetest always allocated 4 bytes per pixel, it implies a bigger pitch for 16 or 24 bpp modes. This patch adds a check to reject pitches the hardware cannot support. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: rewrite pixel clock calculationDarren Etheridge
Updating the tilcdc DRM driver code to calculate the LCD controller pixel clock more accurately. Based on a suggested implementation by Tomi Valkeinen. The current code does not work correctly and produces wrong results with many requested clock rates. It also oddly uses two different clocks, a display pll clock and a divider clock (child of display pll), instead of just using the clock coming to the lcdc. This patch removes the use of the display pll clock, and rewrites the code to calculate the clock rates. The idea is simply to request a clock rate of pixelclock*2, as the LCD controller has an internal divider which we set to 2. Signed-off-by: Darren Etheridge <detheridge@ti.com> [Rewrapped description] Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/i915: Kill off intel_crtc->atomic.wait_vblank, v6.Maarten Lankhorst
Currently we perform our own wait in post_plane_update, but the atomic core performs another one in wait_for_vblanks. This means that 2 vblanks are done when a fb is changed, which is a bit overkill. Merge them by creating a helper function that takes a crtc mask for the planes to wait on. The broadwell vblank workaround may look gone entirely but this is not the case. pipe_config->wm_changed is set to true when any plane is turned on, which forces a vblank wait. Changes since v1: - Removing the double vblank wait on broadwell moved to its own commit. Changes since v2: - Move out POWER_DOMAIN_MODESET handling to its own commit. Changes since v3: - Do not wait for vblank on legacy cursor updates. (Ville) - Move broadwell vblank workaround comment to page_flip_finished. (Ville) Changes since v4: - Compile fix, legacy_cursor_flip -> *_update. Changes since v5: - Kill brackets. - Add WARN_ON when wait_for_vblanks fails. - Remove extra newlines. - Split the checks whether vblank is needed to a separate function, with comments why a vblank is needed. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/56CD84DA.5030507@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2016-02-25drm/i915: Unify power domain handling.Maarten Lankhorst
Right now there's separate power domain handling for update_pipe and modesets. Unify this and only grab POWER_DOMAIN_MODESET once. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455108583-29227-3-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2016-02-25drm/i915: Pass crtc state to modeset_get_crtc_power_domains.Maarten Lankhorst
Use our newly created encoder_mask to iterate over the encoders. This makes it possible to get the crtc power domains from the crtc_state at any time, without any locks or having to look at the legacy state. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455108583-29227-2-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2016-02-25Merge branch 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev into drm-nextDave Airlie
rcar-du updates. * 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev: (281 commits) drm: rcar-du: Add tri-planar memory formats support drm: rcar-du: Add probe deferral debug messages drm: rcar-du: lvds: Add R-Car Gen3 support drm: rcar-du: lvds: Rename PLLEN bit to PLLON drm: rcar-du: lvds: Fix PLL frequency-related configuration drm: rcar-du: lvds: Avoid duplication of clock clamp code drm: rcar-du: Add R8A7795 device support drm: rcar-du: Output the DISP signal on the ODDF pin drm: rcar-du: Output the DISP signal on the DISP pin drm: rcar-du: Support up to 4 CRTCs drm: rcar-du: Drop LVDS double dependency on OF drm: rcar-du: Enable compilation on ARM64 drm: rcar-du: Fix compile warning on 64-bit platforms drm: rcar-du: Expose the VSP1 compositor through KMS planes drm: rcar-du: Move plane allocator to rcar_du_plane.c drm: rcar-du: Restart the DU group when a plane source changes drm: rcar-du: Add VSP1 compositor support drm: rcar-du: Add VSP1 support to the planes allocator drm: rcar-du: Refactor plane setup drm: rcar-du: Compute plane DDCR4 register value directly ...
2016-02-23drm: rcar-du: Add tri-planar memory formats supportLaurent Pinchart
Those formats are supported on Gen3 only. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Add probe deferral debug messagesLaurent Pinchart
Print a message when the HDMI I2C slave encoder can't be found to help debugging probe deferral issues. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Add R-Car Gen3 supportKoji Matsuoka
The LVDS encoder differs slightly in Gen3 SoCs in its PLL configuration. Add support for the Gen3 LVDS PLL parameters and startup procedure. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Rename PLLEN bit to PLLONLaurent Pinchart
The bit is named PLLON in the datasheet, rename it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
generated by cgit (git 2.34.1) at 2025-09-12 03:06:23 +0000