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2022-09-29kbuild: unify two modpost invocationsMasahiro Yamada
Currently, modpost is executed twice; first for vmlinux, second for modules. This commit merges them. Current build flow ================== 1) build obj-y and obj-m objects 2) link vmlinux.o 3) modpost for vmlinux 4) link vmlinux 5) modpost for modules 6) link modules (*.ko) The build steps 1) through 6) are serialized, that is, modules are built after vmlinux. You do not get benefits of parallel builds when scripts/link-vmlinux.sh is being run. New build flow ============== 1) build obj-y and obj-m objects 2) link vmlinux.o 3) modpost for vmlinux and modules 4a) link vmlinux 4b) link modules (*.ko) In the new build flow, modpost is invoked just once. vmlinux and modules are built in parallel. One exception is CONFIG_DEBUG_INFO_BTF_MODULES=y, where modules depend on vmlinux. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu>
2022-09-28Merge branch 'uniphier/dt' into arm/dtArnd Bergmann
Updates from Kunihiko Hayashi via email: "Update devicetree sources for UniPhier armv8 SoCs to remove dtschema warnings, add support existing features that haven't yet been described, and replace constants with macros." * uniphier/dt: arm64: dts: uniphier: Add L2 cache node arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node arm64: dts: uniphier: Fix opp-table node name for LD20 arm64: dts: uniphier: Add USB-device support for PXs3 reference board arm64: dts: uniphier: Add ahci controller nodes for PXs3 arm64: dts: uniphier: Use GIC interrupt definitions arm64: dts: uniphier: Rename gpio-hog nodes arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller arm64: dts: uniphier: Rename pvtctl node to thermal-sensor ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep node ARM: dts: uniphier: Move interrupt-parent property to each child node in uniphier-support-card ARM: dts: uniphier: Add ahci controller nodes for PXs2 ARM: dts: uniphier: Add ahci controller nodes for Pro4 ARM: dts: uniphier: Use GIC interrupt definitions ARM: dts: uniphier: Rename gpio-hog node ARM: dts: uniphier: Rename usb-glue node for USB3 to usb-controller ARM: dts: uniphier: Rename usb-phy node for USB2 to usb-controller ARM: dts: uniphier: Rename pvtctl node to thermal-sensor
2022-09-28arm64: dts: uniphier: Add L2 cache nodeKunihiko Hayashi
Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy information because the following warning was issued. cacheinfo: Unable to detect cache hierarchy for CPU 0 Early cacheinfo failed, ret = -2 Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie nodeKunihiko Hayashi
The generic platform driver pcie-designware-plat.c doesn't work for UniPhier PCIe host controller, because the controller has some necessary initialization sequence for the controller-specific logic. Currently the controller doesn't use "snps,dw-pcie" compatible, so this is no longer needed. Remove the compatible string from the pcie node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-10-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Fix opp-table node name for LD20Kunihiko Hayashi
To fix dtbs_check warning: uniphier-ld20-akebi96.dt.yaml: opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$' From schema: Documentation/devicetree/bindings/opp/opp-v2.yaml Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-9-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Add USB-device support for PXs3 reference boardKunihiko Hayashi
PXs3 reference board can change each USB port 0 and 1 to device mode with jumpers. Prepare devicetree sources for USB port 0 and 1. This specifies dr_mode, pinctrl, and some quirks and removes nodes for unused phys and vbus-supply properties. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-8-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Add ahci controller nodes for PXs3Kunihiko Hayashi
Add ahci core controller and glue layer nodes including reset-controller and sata-phy. This supports for PXs3 and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-7-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Use GIC interrupt definitionsKunihiko Hayashi
Use human-readable definitions for GIC interrupt type and flag, instead of hard-coding the numbers. No functional change. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-6-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename gpio-hog nodesKunihiko Hayashi
According to gpio-hog schema, should add the suffix "-hog" to the node names including gpio-hog to fix the following warning. uniphier-ld11-ref.dtb: gpio@55000000: 'xirq0' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml This applies to the devicetre for LD11, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-5-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controllerKunihiko Hayashi
This "usb-glue" stands for an external controller associated with USB core, however, this is not common. So rename to "usb-controller". Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-4-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controllerKunihiko Hayashi
Actual phy nodes are each child node. The parent node should be usb-controller node as a representation of the phy integration. This applies to the devicetree for LD11 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-3-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep nodeKunihiko Hayashi
The generic platform driver pcie-designware-plat.c doesn't work for UniPhier PCIe endpoint controller, because the controller has some necessary initialization sequence for the controller-specific logic. Currently the controller doesn't use "snps,dw-pcie-ep" compatible, so this is no longer needed. Remove the compatible string from the pcie-ep node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-10-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Move interrupt-parent property to each child node in ↵Kunihiko Hayashi
uniphier-support-card The dtschema warning: uniphier-ld11-ref.dt.yaml: system-bus@58c00000: 'interrupt-parent' does not match any of the regexes: '^.*@[1-5],[1-9a-f][0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-9-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Add ahci controller nodes for PXs2Kunihiko Hayashi
Add ahci core controller and glue layer nodes including reset-controller and sata-phy. This supports for PXs2 and the boards without PXs2 vodka board that doesn't implement any SATA connectors. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-8-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Add ahci controller nodes for Pro4Kunihiko Hayashi
Add ahci controller, glue layer, and clock nodes for Pro4 SoC. The glue layer includes reset and phy, and the clock node is used for handling ahci clocks on SoC-glue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-7-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Use GIC interrupt definitionsKunihiko Hayashi
Use human-readable definitions for GIC interrupt type and flag, instead of hard-coding the numbers. No functional change. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-6-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename gpio-hog nodeKunihiko Hayashi
According to gpio-hog schema, should add the suffix "-hog" to the node names including gpio-hog to fix the following warning. uniphier-pro4-ref.dtb: gpio@55000000: 'xirq2' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml This applies to the devicetree for LD4, LD6b, Pro4 and sLD8 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-5-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename usb-glue node for USB3 to usb-controllerKunihiko Hayashi
This "usb-glue" stands for an external controller associated with USB core, however, this is not common. So rename to "usb-controller". Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-4-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename usb-phy node for USB2 to usb-controllerKunihiko Hayashi
Actual phy nodes are each child node. The parent node should be usb-controller node as a representation of the phy integration. This applies to the devicetree for Pro4 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-3-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28drm/i915/gt: Perf_limit_reasons are only available for Gen11+Ashutosh Dixit
Register GT0_PERF_LIMIT_REASONS (0x1381a8) is available only for Gen11+. Therefore ensure perf_limit_reasons sysfs files are created only for Gen11+. Otherwise on Gen < 5 accessing these files results in the following oops: <1> [88.829420] BUG: unable to handle page fault for address: ffffc90000bb81a8 <1> [88.829438] #PF: supervisor read access in kernel mode <1> [88.829447] #PF: error_code(0x0000) - not-present page This patch is a backport of the drm-tip commit 0d2d201095e9 ("drm/i915: Perf_limit_reasons are only available for Gen11+") to drm-intel-fixes. The backport is not identical to the original, it only includes the sysfs portions of if. The debugfs portion is not available in drm-intel-fixes so has not been backported. Bspec: 20008 Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/6863 Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces") Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220919162401.2077713-1-ashutosh.dixit@intel.com (backported from commit 0d2d201095e9f141d6a9fb44320afce761f8b5c2)
2022-09-28ARM: remove check for CONFIG_DEBUG_LL_SER3Paul Bolle
A check for CONFIG_DEBUG_LL_SER3 was added in v2.5.43. But the related symbol DEBUG_LL_SER3 was already removed in v2.5.8. This check has always evaluated to false. Remove it. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28firmware/psci: Add debugfs support to ease debuggingDmitry Baryshkov
To ease debugging of PSCI supported features, add debugfs file called 'psci' describing PSCI and SMC CC versions, enabled features and options. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20220926110758.666922-1-dmitry.baryshkov@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28firmware/psci: Print a warning if PSCI doesn't accept PC modeDmitry Baryshkov
The function psci_pd_try_set_osi_mode() will print an error if enabling OSI mode fails. To ease debugging PSCI issues print corresponding message if switching to PC mode fails too. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220926110249.666813-1-dmitry.baryshkov@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'memory-controller-drv-6.1-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v6.1, part 2 Improvements in Synopsys DesignWare Universal Multi-Protocol Memory Controller Devicetree bindings. The bindings are being split into one related to Synopsys core and into quite different derivative Zynq A05 DDR Memory Controller. Extend the Synopsys bindings with additional properties to match upcoming new device support (Baikal-T1 support). * tag 'memory-controller-drv-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support Link: https://lore.kernel.org/r/20220926105023.119781-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'v6.1-rockchip-drivers2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers Some binding additions for rk3128 and rv1126 * tag 'v6.1-rockchip-drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: soc: rockchip: grf: add rockchip,rk3128-grf dt-bindings: arm: rockchip: pmu: add rockchip,rk3128-pmu dt-bindings: soc: rockchip: Document RV1126 pmugrf dt-bindings: soc: rockchip: Document RV1126 grf Link: https://lore.kernel.org/r/3790767.LM0AJKV5NW@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'v6.1-rockchip-defconfig64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/defconfig Enable Synopsys DWC MSHC (sdhci) driver in the defconfig. * tag 'v6.1-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: defconfig: Enable Synopsys DWC MSHC driver Link: https://lore.kernel.org/r/1989419.QkHrqEjB74@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'aspeed-6.1-defconfig' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/defconfig ASPEED defconfig updates for 6.1 - A long awaited sync to make the config closer to that used by OpenBMC machines - Enable PECI to provide defconfig coverage for the subsystem * tag 'aspeed-6.1-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: config: aspeed_g5: Enable PECI ARM: configs: aspeed_g4: Remove appended DTB and ATAG ARM: configs: aspeed: Refresh defconfigs ARM: config: aspeed: Enable namespaces ARM: configs: aspeed_g4: Enable IPV6 options ARM: configs: aspeed_g4: Enable OCC and NBD drivers ARM: configs: aspeed_g5: Enable MCTP stack ARM: configs: aspeed_g5: Add PL2303 USB serial driver ARM: configs: aspeed_g5: Add TPM TIS I2C driver ARM: configs: aspeed_g5: Add mp5023 driver ARM: configs: aspeed: Add support for USB flash drives Link: https://lore.kernel.org/r/CACPK8XeLzL3hT8fwVw9fV7Ccduz_PNhZn_67z2yXefCEha6jJg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: aspeed: Kconfig: Fix indentationJuerg Haefliger
The convention for indentation seems to be a single tab. Help text is further indented by an additional two whitespaces. Fix the lines that violate these rules. Signed-off-by: Juerg Haefliger <juergh@canonical.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220523060532.7864-1-juergh@canonical.com Link: https://lore.kernel.org/r/20220928025926.2592030-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: Drop CMDLINE_* dependency on ATAGSGeert Uytterhoeven
On arm32, the configuration options to specify the kernel command line type depend on ATAGS. However, the actual CMDLINE cofiguration option does not depend on ATAGS, and the code that handles this is not specific to ATAGS (see drivers/of/fdt.c:early_init_dt_scan_chosen()). Hence users who desire to override the kernel command line on arm32 must enable support for ATAGS, even on a pure-DT system. Other architectures (arm64, loongarch, microblaze, nios2, powerpc, and riscv) do not impose such a restriction. Hence drop the dependency on ATAGS. Fixes: bd51e2f595580fb6 ("ARM: 7506/1: allow for ATAGS to be configured out when DT support is selected") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: Drop CMDLINE_FORCE dependency on !ARCH_MULTIPLATFORMGeert Uytterhoeven
On older platforms that boot an image with an appended DTB, or where the boot loader has no support for updating chosen/bootargs, it is common to rely on CMDLINE_FORCE. While a fixed command line can make the kernel unbootable on other platforms, it is not guaranteed to cause that. E.g. all Renesas boards use the same chosen/bootargs in upstream DTS, which works fine if your DHCP server hands out proper nfsroot parameters. Fixes: 84fc863606239d8b ("ARM: make ARCH_MULTIPLATFORM user-visible") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: s3c: remove orphan declarations from arch/arm/mach-s3c/devs.hGaosheng Cui
s3c64xx_device_spi1 and s3c64xx_device_spi2 were removed by commit f1ba938e4f98 ("spi: s3c64xx: Delete unused boardfile helpers"), so remove the declaration, too. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220914034615.1240860-3-cuigaosheng1@huawei.com Link: https://lore.kernel.org/r/20220926104354.118578-3-krzysztof.kozlowski@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: exynos: correct s5k6a3 reset polarity on Midas familyDmitry Torokhov
According to s5k6a3 driver code, the reset line for the chip appears to be active low. This also matches the typical polarity of reset lines in general. Let's fix it up as having correct polarity in DTS is important when the driver will be switched over to gpiod API. Fixes: b4fec64758ab ("ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220913164104.203957-1-dmitry.torokhov@gmail.com Link: https://lore.kernel.org/r/20220926104354.118578-2-krzysztof.kozlowski@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'aspeed-6.1-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt ASPEED device tree updates for 6.1 - New machines * AMD's DaytonaX AST2600 BMC, for the amd64 server * Ampre's Mt. Mitchell AST2600 BMC, for the AmpereOne arm64 server - Fixes and updates for bletchley, mtjade, yosemitev2 and the ast2600-evb * tag 'aspeed-6.1-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: ast2600-evb-a1: Add compatible ARM: dts: aspeed: ast2600evb: Fix compatible string ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers ARM: dts: aspeed-g6: Enable more UART controllers ARM: dts: aspeed: yosemitev2: Disable the EEPROM driver ARM: dts: aspeed: Add AMD DaytonaX BMC dt-bindings: arm: aspeed: document AMD DaytonaX ARM: dts: aspeed: Yosemite V2: Enable OCP debug card ARM: dts: aspeed: mtjade: Remove gpio-keys entries ARM: dts: aspeed: Add device tree for Ampere's Mt. Mitchell BMC dt-bindings: arm: aspeed: document Ampere Mt.Mitchell BMC compatibles ARM: dts: aspeed: bletchley: Remove hdc1080 node ARM: dts: aspeed: bletchley: Add USB debug card IPMB node ARM: dts: aspeed: ast2600-evb: Update I2C devices Link: https://lore.kernel.org/r/CACPK8Xepnci+f+7Pi1jtXod8Jmt+OnJYfDRENjiP-xDBQwFCVg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'v6.1-rockchip-dts64-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt RK3399-Nanopi-R4S-enterprise as variant board, Gru-Scarlet SKU variants, DSI support for rk356x, display-gamma-control for rk3399, display output for quartz64-b and rk3566-roc-pc, hdmi supplies for rk3399-roc-pc, some pinctrl improvements for the px30-evb and a number of changes to bring rk3399 rock4 and rock-pi4 structure closer to names used in schematics. * tag 'v6.1-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: use pin constant for reset-gpios on px30-evb arm64: dts: rockchip: add pinctrl for mipi-pdn pin on px30-evb arm64: dts: rockchip: set max drive-strength for cif_clkout_m0 on px30-evb arm64: dts: rockchip: add avdd-0v9-supply and avdd-1v8-supply on rk3399 rock 4c and pi4 arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4 arm64: dts: rockchip: fix regulator name on rk3399-rock-4 arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4c-plus arm64: dts: rockchip: fix regulator structure on rk3399-rock-4c-plus arm64: dts: rockchip: connect vcca_1v8 to APIO5_VDD on rk3399-rock-4c-plus arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x arm64: dts: rockchip: Enable HDMI and GPU on quartz64-b arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise Edition dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise Edition arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30 arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants arm64: dts: rockchip: enable gamma control on RK3399 arm64: dts: rockchip: Enable video output on rk3566-roc-pc Link: https://lore.kernel.org/r/38114097.10thIPus4b@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocksHan Xu
There is no dedicate parent clock for QSPI so SET_RATE_PARENT flag should not be used. For instance, the default parent clock for QSPI is pll2_bus, which is also the parent clock for quite a few modules, such as MMDC, once GPMI NAND set clock rate for EDO5 mode can cause system hang due to pll2_bus rate changed. Fixes: f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API") Signed-off-by: Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/20220915150959.3646702-1-han.xu@nxp.com Tested-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-28m68k: Rework BI_VIRT_RNG_SEED as BI_RNG_SEEDJason A. Donenfeld
This is useful on !virt platforms for kexec, so change things from BI_VIRT_RNG_SEED to be BI_RNG_SEED, and simply remove BI_VIRT_RNG_SEED because it only ever lasted one release, and nothing is broken by not having it. At the same time, keep a comment noting that it's been removed, so that ID isn't reused. In addition, we previously documented 2-byte alignment, but 4-byte alignment is actually necessary, so update that comment. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Fixes: a1ee38ab1a75 ("m68k: virt: Use RNG seed from bootinfo block") Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20220927130835.1629806-2-Jason@zx2c4.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-09-28m68k: Process bootinfo records before saving themJason A. Donenfeld
The RNG seed boot record is memzeroed after processing, in order to preserve forward secrecy. By saving the bootinfo for procfs prior to that, forward secrecy is violated, since it becomes possible to recover past states. So, save the bootinfo block only after first processing them. Fixes: a1ee38ab1a75 ("m68k: virt: Use RNG seed from bootinfo block") Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20220927130835.1629806-1-Jason@zx2c4.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-09-28i2c: microchip: pci1xxxx: Add driver for I2C host controller in ↵Tharun Kumar P
multifunction endpoint of pci1xxxx switch Microchip pci1xxxx is an unmanaged PCIe3.1a Switch for Consumer, Industrial and Automotive applications. This switch has multiple downstream ports. In one of the Switch's Downstream port, there is a multifunction endpoint for peripherals which includes an I2C host controller. The I2C function in the endpoint operates at 100KHz, 400KHz and 1 MHz and has buffer depth of 128 bytes. This patch provides the I2C controller driver for the I2C function of the switch. Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-09-28KVM: x86/svm/pmu: Rewrite get_gp_pmc_amd() for more counters scalabilityLike Xu
If the number of AMD gp counters continues to grow, the code will be very clumsy and the switch-case design of inline get_gp_pmc_amd() will also bloat the kernel text size. The target code is taught to manage two groups of MSRs, each representing a different version of the AMD PMU counter MSRs. The MSR addresses of each group are contiguous, with no holes, and there is no intersection between two sets of addresses, but they are discrete in functionality by design like this: [Group A : All counter MSRs are tightly bound to all event select MSRs ] MSR_K7_EVNTSEL0 0xc0010000 MSR_K7_EVNTSELi 0xc0010000 + i ... MSR_K7_EVNTSEL3 0xc0010003 MSR_K7_PERFCTR0 0xc0010004 MSR_K7_PERFCTRi 0xc0010004 + i ... MSR_K7_PERFCTR3 0xc0010007 [Group B : The counter MSRs are interleaved with the event select MSRs ] MSR_F15H_PERF_CTL0 0xc0010200 MSR_F15H_PERF_CTR0 (0xc0010200 + 1) ... MSR_F15H_PERF_CTLi (0xc0010200 + 2 * i) MSR_F15H_PERF_CTRi (0xc0010200 + 2 * i + 1) ... MSR_F15H_PERF_CTL5 (0xc0010200 + 2 * 5) MSR_F15H_PERF_CTR5 (0xc0010200 + 2 * 5 + 1) Rewrite get_gp_pmc_amd() in this way: first determine which group of registers is accessed, then determine if it matches its requested type, applying different scaling ratios respectively, and finally get pmc_idx to pass into amd_pmc_idx_to_pmc(). Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-8-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/svm/pmu: Direct access pmu->gp_counter[] to implement amd_*_to_pmc()Like Xu
Access PMU counters on AMD by directly indexing the array of general purpose counters instead of translating the PMC index to an MSR index. AMD only supports gp counters, there's no need to translate a PMC index to an MSR index and back to a PMC index. Opportunistically apply array_index_nospec() to reduce the attack surface for speculative execution and remove the dead code. Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-7-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Avoid using PEBS perf_events for normal countersLike Xu
The check logic in the pmc_resume_counter() to determine whether a perf_event is reusable is partial and flawed, especially when it comes to a pseudocode sequence (contrived, but valid) like: - enabling a counter and its PEBS bit - enable global_ctrl - run workload - disable only the PEBS bit, leaving the global_ctrl bit enabled In this corner case, a perf_event created for PEBS can be reused by a normal counter before it has been released and recreated, and when this normal counter overflows, it triggers a PEBS interrupt (precise_ip != 0). To address this issue, reprogram all affected counters when PEBS_ENABLE change and reuse a counter if and only if PEBS exactly matches precise. Fixes: 79f3e3b58386 ("KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter") Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-4-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Refactor PERF_GLOBAL_CTRL update helper for reuse by PEBSLike Xu
Extract the "global ctrl" specific bits out of global_ctrl_changed() so that the helper only deals with reprogramming general purpose counters, and rename the helper accordingly. PEBS needs the same logic, i.e needs to reprogram counters associated when PEBS_ENABLE bits are toggled, and will use the helper in a future fix. No functional change intended. Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-4-likexu@tencent.com [sean: split to separate patch, write changelog] Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Don't generate PEBS records for emulated instructionsLike Xu
KVM will accumulate an enabled counter for at least INSTRUCTIONS or BRANCH_INSTRUCTION hw event from any KVM emulated instructions, generating emulated overflow interrupt on counter overflow, which in theory should also happen when the PEBS counter overflows but it currently lacks this part of the underlying support (e.g. through software injection of records in the irq context or a lazy approach). In this case, KVM skips the injection of this BUFFER_OVF PMI (effectively dropping one PEBS record) and let the overflow counter move on. The loss of a single sample does not introduce a loss of accuracy, but is easily noticeable for certain specific instructions. This issue is expected to be addressed along with the issue of PEBS cross-mapped counters with a slow-path proposal. Fixes: 79f3e3b58386 ("KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter") Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-3-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Avoid setting BIT_ULL(-1) to pmu->host_cross_mapped_maskLike Xu
In the extreme case of host counters multiplexing and contention, the perf_event requested by the guest's pebs counter is not allocated to any actual physical counter, in which case hw.idx is bookkept as -1, resulting in an out-of-bounds access to host_cross_mapped_mask. Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-2-likexu@tencent.com [sean: expand comment to explain how a negative idx can be encountered] Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: selftests: Don't set reserved bits for invalid Hyper-V hypercall numberVitaly Kuznetsov
Bits 27 through 31 in Hyper-V hypercall 'control' are reserved (see HV_HYPERCALL_RSVD0_MASK) but '0xdeadbeef' includes them. This causes KVM to return HV_STATUS_INVALID_HYPERCALL_INPUT instead of the expected HV_STATUS_INVALID_HYPERCALL_CODE. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Link: https://lore.kernel.org/all/87fsgjol20.fsf@redhat.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: selftests: Load RAX with -EFAULT before Hyper-V hypercallVipin Sharma
Load RAX with -EFAULT prior to making a Hyper-V hypercall so that tests can't get false negatives due to the compiler coincidentally loading the "right" value into RAX, i.e. to ensure that _KVM_ and not the compiler is correctly clearing RAX on a successful hypercall. Note, initializing *hv_status (in C code) to -EFAULT is not sufficient to avoid false negatives, as the compiler can still "clobber" RAX and thus load garbage into *hv_status if the hypercall faults (or if KVM doesn't set RAX). Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Vipin Sharma <vipinsh@google.com> Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Link: https://lore.kernel.org/r/20220922062451.2927010-1-vipinsh@google.com [sean: move to separate patch, massage changelog] Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: selftests: Check result in hyperv_features for successful hypercallsVipin Sharma
Commit cc5851c6be86 ("KVM: selftests: Use exception fixup for #UD/#GP Hyper-V MSR/hcall tests") introduced a wrong guest assert in guest_hcall(). It is not checking the successful hypercall results and only checks the result when a fault happens. GUEST_ASSERT_2(!hcall->ud_expected || res == hcall->expect, hcall->expect, res); Correct the assertion by only checking results of the successful hypercalls. This issue was observed when this test started failing after building it in Clang. Above guest assert statement fails because "res" is not equal to "hcall->expect" when "hcall->ud_expected" is true. "res" gets some garbage value in Clang from the RAX register. In GCC, RAX is 0 because it using RAX for @output_address in the asm statement and resetting it to 0 before using it as output operand in the same asm statement. Clang is not using RAX for @output_address. Fixes: cc5851c6be86 ("KVM: selftests: Use exception fixup for #UD/#GP Hyper-V MSR/hcall tests") Signed-off-by: Vipin Sharma <vipinsh@google.com> Suggested-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Jim Mattson <jmattson@google.com> Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Link: https://lore.kernel.org/r/20220922062451.2927010-1-vipinsh@google.com [sean: wrap changelog at ~75 chars, move -EFAULT change to separate patch] Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-29kbuild: move vmlinux.o rule to the top MakefileMasahiro Yamada
Move the build rules of vmlinux.o out of scripts/link-vmlinux.sh to clearly separate 1) pre-modpost, 2) modpost, 3) post-modpost stages. This will make further refactoring possible. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu>
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