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2023-04-12media: rc: gpio-ir-recv: Fix support for wake-upFlorian Fainelli
The driver was intended from the start to be a wake-up source for the system, however due to the absence of a suitable call to device_set_wakeup_capable(), the device_may_wakeup() call used to decide whether to enable the GPIO interrupt as a wake-up source would never happen. Lookup the DT standard "wakeup-source" property and call device_init_wakeup() to ensure the device is flagged as being wakeup capable. Reported-by: Matthew Lear <matthew.lear@broadcom.com> Fixes: fd0f6851eb46 ("[media] rc: Add support for GPIO based IR Receiver driver") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
2023-04-12dt-bindings: media: gpio-ir-receiver: Document wakeup-souce propertyFlorian Fainelli
The GPIO IR receiver can be used as a wake-up source for the system, document that. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
2023-04-11Merge branch '40GbE' of ↵Jakub Kicinski
git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue Tony Nguyen says: ==================== iavf: fix racing in VLANs Ahmed Zaki says: This patchset mainly fixes a racing issue in the iavf where the number of VLANs in the vlan_filter_list might be more than the PF limit. To fix that, we get rid of the cvlans and svlans bitmaps and keep all the required info in the list. The second patch adds two new states that are needed so that we keep the VLAN info while the interface goes DOWN: -- DISABLE (notify PF, but keep the filter in the list) -- INACTIVE (dev is DOWN, filter is removed from PF) Finally, the current code keeps each state in a separate bit field, which is error prone. The first patch refactors that by replacing all bits with a single enum. The changes are minimal where each bit change is replaced with the new state value. * '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue: iavf: remove active_cvlans and active_svlans bitmaps iavf: refactor VLAN filter states ==================== Link: https://lore.kernel.org/r/20230407210730.3046149-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-04-11Merge tag 'for-net-2023-04-10' of ↵Jakub Kicinski
git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth Luiz Augusto von Dentz says: ==================== bluetooth pull request for net: - Fix not setting Dath Path for broadcast sink - Fix not cleaning up on LE Connection failure - SCO: Fix possible circular locking dependency - L2CAP: Fix use-after-free in l2cap_disconnect_{req,rsp} - Fix race condition in hidp_session_thread - btbcm: Fix logic error in forming the board name - btbcm: Fix use after free in btsdio_remove * tag 'for-net-2023-04-10' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth: Bluetooth: L2CAP: Fix use-after-free in l2cap_disconnect_{req,rsp} Bluetooth: Set ISO Data Path on broadcast sink Bluetooth: hci_conn: Fix possible UAF Bluetooth: SCO: Fix possible circular locking dependency sco_sock_getsockopt Bluetooth: SCO: Fix possible circular locking dependency on sco_connect_cfm bluetooth: btbcm: Fix logic error in forming the board name. Bluetooth: btsdio: fix use after free bug in btsdio_remove due to race condition Bluetooth: Fix race condition in hidp_session_thread Bluetooth: Fix printing errors if LE Connection times out Bluetooth: hci_conn: Fix not cleaning up on LE Connection failure ==================== Link: https://lore.kernel.org/r/20230410172718.4067798-1-luiz.dentz@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-04-12dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBCMarek Vasut
Add DT compatible for Data Modul i.MX8M Plus eDM SBC board. This is an evaluation board for various custom display units. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-12dt-bindings: arm: fsl: Add chargebyte TarragonStefan Wahren
This adds the compatibles for the chargebyte Tarragon boards. Signed-off-by: Stefan Wahren <stefan.wahren@chargebyte.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-12dt-bindings: vendor-prefixes: add chargebyteStefan Wahren
chargebyte supplies hardware and software products for all aspects of charging communication. https://chargebyte.com/ Signed-off-by: Stefan Wahren <stefan.wahren@chargebyte.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-11scsi: ses: Handle enclosure with just a primary component gracefullyJiri Kosina
This reverts commit 3fe97ff3d949 ("scsi: ses: Don't attach if enclosure has no components") and introduces proper handling of case where there are no detected secondary components, but primary component (enumerated in num_enclosures) does exist. That fix was originally proposed by Ding Hui <dinghui@sangfor.com.cn>. Completely ignoring devices that have one primary enclosure and no secondary one results in ses_intf_add() bailing completely scsi 2:0:0:254: enclosure has no enumerated components scsi 2:0:0:254: Failed to bind enclosure -12ven in valid configurations such even on valid configurations with 1 primary and 0 secondary enclosures as below: # sg_ses /dev/sg0 3PARdata SES 3321 Supported diagnostic pages: Supported Diagnostic Pages [sdp] [0x0] Configuration (SES) [cf] [0x1] Short Enclosure Status (SES) [ses] [0x8] # sg_ses -p cf /dev/sg0 3PARdata SES 3321 Configuration diagnostic page: number of secondary subenclosures: 0 generation code: 0x0 enclosure descriptor list Subenclosure identifier: 0 [primary] relative ES process id: 0, number of ES processes: 1 number of type descriptor headers: 1 enclosure logical identifier (hex): 20000002ac02068d enclosure vendor: 3PARdata product: VV rev: 3321 type descriptor header and text list Element type: Unspecified, subenclosure id: 0 number of possible elements: 1 The changelog for the original fix follows ===== We can get a crash when disconnecting the iSCSI session, the call trace like this: [ffff00002a00fb70] kfree at ffff00000830e224 [ffff00002a00fba0] ses_intf_remove at ffff000001f200e4 [ffff00002a00fbd0] device_del at ffff0000086b6a98 [ffff00002a00fc50] device_unregister at ffff0000086b6d58 [ffff00002a00fc70] __scsi_remove_device at ffff00000870608c [ffff00002a00fca0] scsi_remove_device at ffff000008706134 [ffff00002a00fcc0] __scsi_remove_target at ffff0000087062e4 [ffff00002a00fd10] scsi_remove_target at ffff0000087064c0 [ffff00002a00fd70] __iscsi_unbind_session at ffff000001c872c4 [ffff00002a00fdb0] process_one_work at ffff00000810f35c [ffff00002a00fe00] worker_thread at ffff00000810f648 [ffff00002a00fe70] kthread at ffff000008116e98 In ses_intf_add, components count could be 0, and kcalloc 0 size scomp, but not saved in edev->component[i].scratch In this situation, edev->component[0].scratch is an invalid pointer, when kfree it in ses_intf_remove_enclosure, a crash like above would happen The call trace also could be other random cases when kfree cannot catch the invalid pointer We should not use edev->component[] array when the components count is 0 We also need check index when use edev->component[] array in ses_enclosure_data_process ===== Reported-by: Michal Kolar <mich.k@seznam.cz> Originally-by: Ding Hui <dinghui@sangfor.com.cn> Cc: stable@vger.kernel.org Fixes: 3fe97ff3d949 ("scsi: ses: Don't attach if enclosure has no components") Signed-off-by: Jiri Kosina <jkosina@suse.cz> Link: https://lore.kernel.org/r/nycvar.YFH.7.76.2304042122270.29760@cbobk.fhfr.pm Tested-by: Michal Kolar <mich.k@seznam.cz> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2023-04-11Documentation: firmware: Clarify firmware path usageFlorian Fainelli
Newline characters will be taken into account for the firmware search path parameter, warn users about that and provide an example using 'echo -n' such that it clarifies the typical use of that parameter. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20230402135423.3235-1-f.fainelli@gmail.com Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2023-04-11docs/mm: Physical Memory: Fix grammarKim Phillips
it's -> its referenced to by -> referenced by Signed-off-by: Kim Phillips <kim.phillips@amd.com> Reviewed-by: Mike Rapoport (IBM) <rppt@kernel.org> Link: https://lore.kernel.org/r/20230331165254.207526-1-kim.phillips@amd.com Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2023-04-11drm/amdgpu: Enable GFX11 SDMA context empty interruptGraham Sider
Enable SDMA queue empty context switching. SDMA context switch due to quantum programming no longer done here (as of sdma v6), so re-name sdma_v6_0_ctx_switch_enable to sdma_v6_0_ctxempty_int_enable to reflect this. Also program SDMAx_QUEUEx_SCHEDULE_CNTL for context switch due to quantum in KFD. Set to amdgpu_sdma_phase_quantum (defaults to 32 i.e. 3200us). Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdkfd: Check PCIe atomics support on GFX11 to set CP_HQD_HQ_STATUS0[29]Sreekant Somasekharan
CP_HQD_HQ_STATUS0[29] bit will be used by CPFW to acknowledge whether PCIe atomics are supported. The default value of this bit is set to 0. Driver will check whether PCIe atomics are supported and set the bit to 1 if supported. This will force CPFW to use real atomic ops. If the bit is not set, CPFW will default to read/modify/write using the firmware itself. This is applicable only to GFX11 RS64 CP with MEC FW >= 509. If MEC FW < 509 and for all GFX11 F32 CP, PCIe atomics needs to be supported else it will skip the device. This commit also involves moving amdgpu_amdkfd_device_probe() function call after per-IP early_init loop in amdgpu_device_ip_early_init() function so as to check for RS64 enabled device. Signed-off-by: Sreekant Somasekharan <sreekant.somasekharan@amd.com> Reviewed-by: Graham Sider <Graham.Sider@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Add logging for DP link traning Test Pattern SeqeuncesSrinivasan Shanmugam
Add some more logging for DP link traning test pattern seqeunces for better debugging. Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: correct ras enabled flagStanley.Yang
XGMI RAS should be according to the gmc xgmi physical nodes number, XGMI RAS should not be enabled if xgmi num_physical_nodes is zero. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: fix unexpected block idStanley.Yang
Aldebaran supports VCN and JPEG RAS, it reports unexpected block id message during VCN and JPEG RAS initialization if VCN and JPEG block id not defined. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: use sdma_v6 single packet invalidationPierre-Eric Pelloux-Prayer
This achieves the same result as the sequence used in emit_flush_gpu_tlb but the invalidation is now a single packet instead of the 3 packets required to implement reg_write_reg_wait. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display : Log DP link training downspread infoSrinivasan Shanmugam
Update the existing log with DP LT downspread info: [Downstream devices shall support down spreading of the link clock. The down-spread amplitude shall either be disabled (0.0%) or up to 0.5%, as written by the upstream device to the DOWNSPREAD_CTRL register (DPCD 00107h). The modulation frequency range shall be 30 to 33 kHz] Besides, fix checkpatch warning: CHECK: Alignment should match open parenthesis Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: remove unused matching_stream_ptrs variableTom Rix
clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_enc_cfg.c:625:6: error: variable 'matching_stream_ptrs' set but not used [-Werror,-Wunused-but-set-variable] int matching_stream_ptrs = 0; ^ This variable is not used so remove it. Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: set variables dml*_funcs storage-class-specifier to staticTom Rix
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:44:24: warning: symbol 'dml20_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:51:24: warning: symbol 'dml20v2_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:58:24: warning: symbol 'dml21_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:65:24: warning: symbol 'dml30_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:72:24: warning: symbol 'dml31_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:79:24: warning: symbol 'dml314_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:86:24: warning: symbol 'dml32_funcs' was not declared. Should it be static? These variables are only used in one file so should be static. Cleanup whitespace, use tabs consistently for indents. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: set variables aperture_default_system and ↵Tom Rix
context0_default_system storage-class-specifier to static smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:758:10: warning: symbol 'aperture_default_system' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:759:10: warning: symbol 'context0_default_system' was not declared. Should it be static? These variables are only used in one file so should be static. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: set variable dcn3_14_soc storage-class-specifier to staticTom Rix
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.c:100:37: warning: symbol 'dcn3_14_soc' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: Fix warningsLijo Lazar
Fix below warning due to incompatible types in conditional operator ../pm/swsmu/smu13/smu_v13_0_6_ppt.c:315:17: sparse: sparse: incompatible types in conditional expression (different base types): Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Link: https://lore.kernel.org/oe-kbuild-all/202303082135.NjdX1Bij-lkp@intel.com/ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/pm: correct SMU13.0.7 max shader clock reportingHoratio Zhang
Correct the max shader clock reporting on SMU 13.0.7. Signed-off-by: Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/pm: correct SMU13.0.7 pstate profiling clock settingsHoratio Zhang
Correct the pstate standard/peak profiling mode clock settings for SMU13.0.7. Signed-off-by: Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: refine get gpu clock counter methodTong Liu01
[why] regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and unaccessible under sriov. The clock counter high bit may update during reading process. [How] Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sriov. Refine get gpu clock counter method to make the result more precise. Signed-off-by: Tong Liu01 <Tong.Liu01@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: optimize redundant code in umc_v6_7YiPeng Chai
Optimize redundant code in umc_v6_7. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: Fix sdma v4 sw fini errorlyndonli
Fix sdma v4 sw fini error for sdma 4.2.2 to solve the following general protection fault [ +0.108196] general protection fault, probably for non-canonical address 0xd5e5a4ae79d24a32: 0000 [#1] PREEMPT SMP PTI [ +0.000018] RIP: 0010:free_fw_priv+0xd/0x70 [ +0.000022] Call Trace: [ +0.000012] <TASK> [ +0.000011] release_firmware+0x55/0x80 [ +0.000021] amdgpu_ucode_release+0x11/0x20 [amdgpu] [ +0.000415] amdgpu_sdma_destroy_inst_ctx+0x4f/0x90 [amdgpu] [ +0.000360] sdma_v4_0_sw_fini+0xce/0x110 [amdgpu] Signed-off-by: lyndonli <Lyndon.Li@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: DROP redundant drm_prime_sg_to_dma_addr_arrayShane Xiao
For DMA-MAP userptr on other GPUs, the dma address array will be populated in amdgpu_ttm_backend_bind. Remove the redundant call from the driver. v2: update the comment Signed-off-by: Shane Xiao <shane.xiao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: optimize redundant code in umc_v8_10YiPeng Chai
Optimize redundant code in umc_v8_10 Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11amd/amdgpu: Inherit coherence flags base on original BO flagsShane Xiao
For SG BO to DMA-map userptrs on other GPUs, the SG BO need inherit MTYPEs in PTEs from original BO. If we set the flags, the device can be coherent with the CPUs and other GPUs. v2: 1. Drop unnecessary flags check 2. Remove local variable align Signed-off-by: Shane Xiao <shane.xiao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/pm: Fix incorrect comment about Vangogh power cap supportGuilherme G. Piccoli
The comment mentions that power1 cap attributes are not supported on Vangogh, but the opposite is indeed valid: for APUs, only Vangogh is supported. While at it, also fixed the Renoir comment below (thanks Melissa for noticing that!). Cc: Lijo Lazar <lijo.lazar@amd.com> Cc: Melissa Wen <mwen@igalia.com> Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: Add userptr bo support for mGPUs when iommu is onShane Xiao
For userptr bo with iommu on, multiple GPUs use same system memory dma mapping address when both adev and bo_adev are in identity mode or in the same iommu group. If RAM direct map to one GPU, other GPUs can share the original BO in order to reduce dma address array usage when RAM can direct map to these GPUs. However, we should explicit check whether RAM can direct map to all these GPUs. This patch fixes a potential issue that where RAM is direct mapped on some but not all GPUs. v2: 1. Update comment 2. Add helper function reuse_dmamap Signed-off-by: Shane Xiao <shane.xiao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/amdgpu: Drop the hang limit parameterSrinivasan Shanmugam
The driver doesn't resubmit jobs on hangs any more, hence drop the hang limit parameter - amdgpu_job_hang_limit, wherever it is used. Suggested-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Kent Russell <kent.russell@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Fix potential null dereferenceIgor Artemiev
The adev->dm.dc pointer can be NULL and dereferenced in amdgpu_dm_fini() without checking. Add a NULL pointer check before calling dc_dmub_srv_destroy(). Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 9a71c7d31734 ("drm/amd/display: Register DMUB service with DC") Signed-off-by: Igor Artemiev <Igor.A.Artemiev@mcst.ru> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: 3.2.230Aric Cyr
This DC version brings along: - FW Release 0.0.161.0 - Improvements on FPO/FAMS - Correction to DML calculation - Fix to multiple clock related issues Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd: Fix an out of bounds error in BIOS parserMario Limonciello
The array is hardcoded to 8 in atomfirmware.h, but firmware provides a bigger one sometimes. Deferencing the larger array causes an out of bounds error. commit 4fc1ba4aa589 ("drm/amd/display: fix array index out of bound error in bios parser") fixed some of this, but there are two other cases not covered by it. Fix those as well. Reported-by: erhard_f@mailbox.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=214853 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2473 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: [FW Promotion] Release 0.0.161.0Anthony Koo
- Add command to idle opt. - Rename d3 entry event and add idle trigger param on notify event. - Add bit to fw boot status to notify status when hardware is powered up. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Improve robustness of FIXED_VS link training at DP1 ratesMichael Strauss
[WHY] New sequence for transparent mode DP1.x link training was provided by LTTPR vendor [HOW] Implement new FIXED_VS sequence, increase LT retry count to minimize any potential intermittent lightup failures Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeuedYifan Zha
[Why] As MES KIQ is dequeued, tell RLC that KIQ is inactive [How] Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status In addition, driver can halt MES under SRIOV when unloading driver v2: Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Horace Chen <horace.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: add dscclk instance offset checkCharlene Liu
[why] based on dscclk instance offset check conditiona program dscclk Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: On clock init, maintain DISPCLK freqAlvin Lee
[Description] - On init if a display is connected, we need to maintain the DISPCLK frequency - Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced) - Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged - However, add option to do a full pipe power down (including link) which will also avoid audio related issues - Disabled for the time being on dcn32 Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Add FPO + VActive supportAlvin Lee
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and the second display is able to switch in VACTIVE with a given amount of margin Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Correct DML calculation to follow HW SPECPaul Hsieh
[Why] In 2560x1600@240p eDP panel, driver use lowest voltage level to play 1080p video cause underflow. According to HW SPEC, the senario should use high voltage level. [How] ChromaPre value is zero when bandwidth validation. Correct ChromaPre calculation. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: prep work for root clock optimization enablement for DCN314Hamza Mahfooz
To enable root clock optimizations, we need a number of register writes and need to account for the difference in DPSTREAMCLK between DCN31 and DCN314. To prevent issues, add a number of register writes to DCCG_MASK_SH_LIST_DCN314_COMMON(), and define dccg314_init() which is mostly in alignment with dccg31_init() but accounts for the new DPSTREAMCLK sequence. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: add scaler control for dcn32Zhikai Zhai
[WHY] It will introduce the extra warnning log on some asic that doesn't register [HOW] Add the register on dcn32 Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: Clear FAMS flag if FAMS doesn't reduce vlevelAlvin Lee
[Description] - If we find that applying FAMS doesn't reduce the voltage level, we will not use it - Ensure to clear the stream flags indicating FAMS if we hit this case Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: Add MES KIQ dequeue in MES hw finiYifan Zha
[Why] Need dequeue MES KIQ under SRIOV when unloading driver [How] Modify mes_v11_0_kiq_dequeue_sched which was used to dequeue MES SCHED to support veriable pipe. Add MES KIQ dequeue in hw fini Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Horace Chen <horace.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/display: remove unused average_render_time_in_us and i variablesTom Rix
clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15: error: variable 'average_render_time_in_us' set but not used [-Werror,-Wunused-but-set-variable] unsigned int average_render_time_in_us = 0; ^ This variable is not used so remove it, which caused i to be unused so remove that as well. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amdgpu: add new parameters in v11_structArvind Yadav
Added some new parameters defined for the gfx usermode queues use cases in the v11_mqd_struct. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian Koenig <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Arvind Yadav <Arvind.Yadav@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-11drm/amd/amdgpu: introduce gc_*_mes_2.bin v2Jack Xiao
To avoid new mes fw running with old driver, rename mes schq fw to gc_*_mes_2.bin. v2: add MODULE_FIRMWARE declaration v3: squash in fixup patch Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-24 14:43:17 +0000