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2025-05-09dt-bindings: soc: qcom,rpm: add missing clock-controller nodeDmitry Baryshkov
On Qualcomm platforms in addition to regulators the RPM also provides clocks via the child clock-controller node. Describe it properly in the schema. Fixes: 872f91b5ea72 ("clk: qcom: Add support for RPM Clocks") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-1-bcedd1406790@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-09soc: qcom: smem: Update max processor countUnnathi Chalicheemala
Update max processor count to reflect the number of co-processors on upcoming SoC. Signed-off-by: Unnathi Chalicheemala <unnathi.chalicheemala@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250424-smem_count-v1-1-931cf68f71a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-09firmware: qcom: tzmem: disable sm7150 platformDanila Tikhonov
The SHM bridge makes the SM7150 devices reset while probing the RMTFS (in qcom_scm_assign_mem()). Blacklist the SHM Bridge on corresponding platforms using SoC-level compat string. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250422213137.80366-13-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-09soc: qcom: pd-mapper: Add support for SM7150Jens Reidel
SM7150 protection domains are the same as SC7180, with the subtle difference that SM7150 has a CDSP. Signed-off-by: Jens Reidel <adrian@mainlining.org> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250422213137.80366-11-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-09soc: qcom: pmic_glink_altmode: fix spurious DP hotplug eventsJohan Hovold
The PMIC GLINK driver is currently generating DisplayPort hotplug notifications whenever something is connected to (or disconnected from) a port regardless of the type of notification sent by the firmware. These notifications are forwarded to user space by the DRM subsystem as connector "change" uevents: KERNEL[1556.223776] change /devices/platform/soc@0/ae00000.display-subsystem/ae01000.display-controller/drm/card0 (drm) ACTION=change DEVPATH=/devices/platform/soc@0/ae00000.display-subsystem/ae01000.display-controller/drm/card0 SUBSYSTEM=drm HOTPLUG=1 CONNECTOR=36 DEVNAME=/dev/dri/card0 DEVTYPE=drm_minor SEQNUM=4176 MAJOR=226 MINOR=0 On the Lenovo ThinkPad X13s and T14s, the PMIC GLINK firmware sends two identical notifications with orientation information when connecting a charger, each generating a bogus DRM hotplug event. On the X13s, two such notification are also sent every 90 seconds while a charger remains connected, which again are forwarded to user space: port = 1, svid = ff00, mode = 255, hpd_state = 0 payload = 01 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 00 Note that the firmware only sends on of these when connecting an ethernet adapter. Fix the spurious hotplug events by only forwarding hotplug notifications for the Type-C DisplayPort service id. This also reduces the number of uevents from four to two when an actual DisplayPort altmode device is connected: port = 0, svid = ff01, mode = 2, hpd_state = 0 payload = 00 01 02 00 f2 0c 01 ff 03 00 00 00 00 00 00 00 port = 0, svid = ff01, mode = 2, hpd_state = 1 payload = 00 01 02 00 f2 0c 01 ff 43 00 00 00 00 00 00 00 Fixes: 080b4e24852b ("soc: qcom: pmic_glink: Introduce altmode support") Cc: stable@vger.kernel.org # 6.3 Cc: Bjorn Andersson <andersson@kernel.org> Reported-by: Clayton Craft <clayton@craftyguy.net> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Clayton Craft <clayton@craftyguy.net> Link: https://lore.kernel.org/r/20250324132448.6134-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-09soc: qcom: smp2p: Fix fallback to qcom,ipc parseBarnabás Czémán
mbox_request_channel() returning value was changed in case of error. It uses returning value of of_parse_phandle_with_args(). It is returning with -ENOENT instead of -ENODEV when no mboxes property exists. Fixes: 24fdd5074b20 ("mailbox: use error ret code of of_parse_phandle_with_args()") Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Stephan Gerhold <stephan.gerhold@linaro.org> # msm8939 Link: https://lore.kernel.org/r/20250421-fix-qcom-smd-v1-2-574d071d3f27@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-09Merge tag 'renesas-drivers-for-v6.16-tag2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v6.16 (take two) - Cover all R-Car drivers in the ARM/RISC-V/RENESAS ARCHITECTURE maintainer entry, - Identify the Renesas RZ/V2N (R9A09G056) SoC. * tag 'renesas-drivers-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoC MAINTAINERS: Generalize ARM/RISC-V/RENESAS ARCHITECTURE Link: https://lore.kernel.org/r/cover.1746798752.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'amd-tee-for-v6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers AMD-TEE driver updates for v6.16 - Sort header includes - Use pr_fmt * tag 'amd-tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: amdtee: Sort header includes amdtee: Use pr_fmt for messages Link: https://lore.kernel.org/r/20250509065833.GB4188600@rayden Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'hisi-drivers-for-6.16' of https://github.com/hisilicon/linux-hisi ↵Arnd Bergmann
into soc/drivers HiSilicon driver updates for v6.16 - Simplify PCC shared memory region handling in HCCS driver * tag 'hisi-drivers-for-6.16' of https://github.com/hisilicon/linux-hisi: soc: hisilicon: kunpeng_hccs: Simplify PCC shared memory region handling Link: https://lore.kernel.org/r/681D9FC4.6080508@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'memory-controller-drv-6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers Memory controller drivers for v6.16 1. Mediatek: Add support for MT6893 MTK SMI. 2. STM32: Add new driver for STM32 Octo Memory Manager (OMM), which manages muxing between two OSPI busses. 3. Several cleanups and minor improvements (OMAP GPMC, Kconfig entries, BT1 L2). * tag 'memory-controller-drv-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: MAINTAINERS: add entry for STM32 OCTO MEMORY MANAGER driver memory: Add STM32 Octo Memory Manager driver dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller bus: firewall: Fix missing static inline annotations for stubs memory: bt1-l2-ctl: replace scnprintf() with sysfs_emit() memory: mtk-smi: Add support for Dimensity 1200 MT6893 SMI dt-bindings: memory: mtk-smi: Add support for MT6893 memory: tegra: Do not enable by default during compile testing memory: Simplify 'default' choice in Kconfig memory: omap-gpmc: remove GPIO set() and direction_output() callbacks memory: omap-gpmc: use the dedicated define for GPIO direction Link: https://lore.kernel.org/r/20250508093451.55755-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'memory-controller-drv-renesas-6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers Renesas memory controller drivers for v6.16 Improvements and new device support for the Renesas RPC IF memory controller driver: 1. Minor cleanup and improvements. 2. Refactor the driver to accommodate for newly added Renesas RZ/G3E support: - Acquire two resets instead of only one, - Add RZ/G3E xSPI support with different register layout and its own, new interface for Renesas SPI. * tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: renesas-rpc-if: Add missing static keyword memory: renesas-rpc-if: Add RZ/G3E xSPI support memory: renesas-rpc-if: Add wrapper functions memory: renesas-rpc-if: Add regmap to struct rpcif_info memory: renesas-rpc-if: Use devm_reset_control_array_get_exclusive() memory: renesas-rpc-if: Move rpc-if reg definitions dt-bindings: memory: Document RZ/G3E support memory: renesas-rpc-if: Move rpcif_info definitions near to the user memory: renesas-rpc-if: Fix RPCIF_DRENR_CDB macro error Link: https://lore.kernel.org/r/20250508090749.51379-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'scmi-updates-6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers Arm SCMI updates for v6.16 1. Quirk framework to handle buggy firmware With SCMI gaining broader adoption across arm64 platforms, it's increasingly important to address how we consistently manage out-of-spec SCMI firmware already deployed in the field. This change introduces a lightweight quirk framework built around static_keys, enabling developers to: - Define quirks and their match criteria, which can include: o A list of compatibles ({ comp, comp2, NULL }) o Vendor ID / Sub-Vendor ID o Firmware implementation version ranges ([Min_Vers, Max_Vers]) Matching proceeds from the most specific (longest match) to the least specific. NULL entries are treated as wildcards (i.e., match any value). This flexibility allows matching very specific combinations or just a general compatible string. The quirk code blocks/snippets implementing the workaround are placed near their intended usage and guarded by a static_key that's tied to the quirk. Once the SCMI core stack is initialized and retrieves platform info via the base protocol, any matching quirks will have their associated static_keys enabled. 2. Quirk for Qualcomm X1E platforms On some Qualcomm X1E platforms, such as the Lenovo ThinkPad T14s, the SCMI firmware fails to set the FastChannel support bit for PERF_LEVEL_GET, yet it crashes when the driver attempts to fall back to standard messaging which is clearly out-of-spec behavior. To work around this, the new SCMI quirk framework is used to unconditionally enable FC initialization for this firmware version. In the future, once the fixed firmware version is identified, an upper version bound can be added to the quirk match criteria. Alternatively, matching can be further restricted using a SoC-specific compatible string if always enabling FC proves problematic elsewhere. 3. Support for NXP i.MX LMM/CPU vendor protocol extensions The i.MX95 System Manager (SM) implements Logical Machine Management (LMM) and a CPU protocol to manage Logical Machines (LM) and CPUs (e.g., M7). These changes integrate the vendor-specific protocol extensions implementing the LMM and CPU protocols for the i.MX95, facilitating standardized communication between the operating system and the platform's firmware, which will be used by remoteproc drivers. The changes also include the necessary device tree bindings. 4. Miscellaneous cleanups/changes These mainly include polling support in SCMI raw mode. The cleanups centralize error logging for SCMI device creation into a single helper function, consolidate the device matching logic into a single function, and ensure that devices must have a name for registration—removing support for unnamed devices when matching drivers and devices for probing. Transport devices are now excluded from bus matching, and the correct assignment of the parent device for the arm-scmi platform device is ensured in the transport drivers. * tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: firmware: arm_scmi: quirk: Force perf level get fastchannel firmware: arm_scmi: quirk: Fix CLOCK_DESCRIBE_RATES triplet firmware: arm_scmi: Add common framework to handle firmware quirks firmware: arm_scmi: Ensure that the message-id supports fastchannel MAINTAINERS: add entry for i.MX SCMI extensions firmware: imx: Add i.MX95 SCMI CPU driver firmware: imx: Add i.MX95 SCMI LMM driver firmware: arm_scmi: imx: Add i.MX95 CPU Protocol firmware: arm_scmi: imx: Add i.MX95 LMM protocol dt-bindings: firmware: Add i.MX95 SCMI LMM and CPU protocol firmware: arm_scmi: imx: Add LMM and CPU documentation firmware: arm_scmi: Add polling support to raw mode firmware: arm_scmi: Exclude transport devices from bus matching firmware: arm_scmi: Assign correct parent to arm-scmi platform device firmware: arm_scmi: Refactor error logging from SCMI device creation to single helper firmware: arm_scmi: Refactor device matching logic to eliminate duplication firmware: arm_scmi: Ensure scmi_devices are always matched by name as well Link: https://lore.kernel.org/r/20250507134713.49039-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'mtk-soc-for-v6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers MediaTek driver updates for v6.16 This brings some cleanups to the MediaTek DVFSRC driver, commonizing the bandwidth constraints platform data, and also adds support for the DVFSRC hardware found in the MediaTek Dimensity 1200 MT6893 SoC. * tag 'mtk-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: soc: mediatek: mtk-dvfsrc: remove an unused variable soc: mediatek: mtk-dvfsrc: Add support for Dimensity 1200 MT6893 soc: mediatek: mtk-dvfsrc: Rename and move bw constraints data dt-bindings: soc: mediatek: dvfsrc: Add support for MT6893 Link: https://lore.kernel.org/r/20250506091736.125733-2-angelogioacchino.delregno@collabora.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'arm-soc/for-6.16/drivers' of https://github.com/Broadcom/stblinux ↵Arnd Bergmann
into soc/drivers This pull request contains Broadcom SoC driver updates for 6.16, please pull the following: - Ovidiu updates the brcmstb_gisb driver to use the dev_groups instead of manually adding those * tag 'arm-soc/for-6.16/drivers' of https://github.com/Broadcom/stblinux: bus: brcmstb_gisb: use dev_groups to register attribute groups Link: https://lore.kernel.org/r/20250505165810.1948927-3-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'samsung-drivers-6.16' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers Samsung SoC drivers for v6.16 Several improvements to Exynos ACPM (Alive Clock and Power Manager) driver: 1. Handle communication timeous better. 2. Avoid sleeping, so users (PMIC) can still transfer during system shutdown. 3. Fix reading longer messages from them firmware. 4. Deferred probe improvements. 5. Model the user of ACPM - PMIC - a as child device and export devm_acpm_get_by_node() for such use case. * tag 'samsung-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: firmware: exynos-acpm: Correct kerneldoc and use typical np argument name firmware: exynos-acpm: introduce devm_acpm_get_by_node() firmware: exynos-acpm: populate devices from device tree data firmware: exynos-acpm: silence EPROBE_DEFER error on boot firmware: exynos-acpm: fix reading longer results dt-bindings: firmware: google,gs101-acpm-ipc: add PMIC child node firmware: exynos-acpm: allow use during system shutdown firmware: exynos-acpm: use ktime APIs for timeout detection Link: https://lore.kernel.org/r/20250501103541.13795-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'renesas-drivers-for-v6.16-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v6.16 - Enable all Renesas SoCs by default when ARCH_RENESAS is set, which will allow up to remove all individual Renesas SoC entries from the various defconfigs, - Initial support for the Renesas RZ/V2N (R9A09G056) SoC. * tag 'renesas-drivers-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC soc: renesas: Kconfig: Enable SoCs by default when ARCH_RENESAS is set Link: https://lore.kernel.org/r/cover.1745582592.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09dt-bindings: reset: Add compatible for Amlogic A4/A5 Reset ControllerZelong Dong
Add compatibles for Amlogic A4 and A5 reset controllers, which fall back to 'amlogic,meson-s4-reset'. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240918074211.8067-2-zelong.dong@amlogic.com Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com> Link: https://lore.kernel.org/r/20250411-a4-a5-reset-v6-1-89963278c686@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-09soc: fsl: qe: remove unused qe_ic_from_irq functionTom Rix
clang with W=1 reports drivers/soc/fsl/qe/qe_ic.c:235:29: error: unused function 'qe_ic_from_irq' [-Werror,-Wunused-function] The use of this function was removed with commit d7c2878cfcfa ("soc: fsl: qe: remove unused qe_ic_set_* functions") Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20230320125202.1721775-1-trix@redhat.com Link: https://lore.kernel.org/all/1619002613-18216-1-git-send-email-jiapeng.chong@linux.alibaba.com/ [krzk: Adjust commit msg] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-09soc: ti: wkup_m3_ipc: Use dev_err_probeAlexander Stein
During probe the mailbox channel might not yet be available. Use dev_err_probe to silence this deferred probe error message: wkup_m3_ipc 44e11324.wkup_m3_ipc: IPC Request for A8->M3 Channel failed! -517 Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20250509093652.1866566-1-alexander.stein@ew.tq-group.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09soc: imx8m: Dump higher 64bits UIDPeng Fan
i.MX8MP UID is actually 128bits and partitioned into two parts. The 1st 64bits are at 0x410 and 0x420, and 2nd 64bits are at 0xE00 and 0xE10. Dump the whole 128bits for i.MX8MP, by set soc_uid as an array with two u64. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09soc: imx8m: Introduce soc_uid hookPeng Fan
Cleanup code by introducing soc_uid hook, i.MX8MQ/M/N could reuse one function imx8m_soc_uid, i.MX8MP could have its own one. With this patch, it will easy to add 128bits UID support for i.MX8MP. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09soc: imx8m: Cleanup with adding imx8m_soc_[un]preparePeng Fan
There is a common flow to i.MX8M family, map OCOTP register base and enable ocotp clk first before read Unique ID from OCOTP. So introduce imx8m_soc_prepare to do ioremap and enable the ocotp clk, and introduce imx8m_soc_unprepare to disable the clk and do iounmap. With this patch, no need to spread the ioremap and clk handling in each soc_revision hook. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-08memory: renesas-rpc-if: Add missing static keywordBiju Das
Fix the below sparse warnings: symbol 'rpcif_impl' was not declared. Should it be static? symbol 'xspi_impl' was not declared. Should it be static? Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505072013.1EqwjtaR-lkp@intel.com/ Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250507162146.140494-1-biju.das.jz@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-07soc: qcom: pmic_glink: enable UCSI on sc8280xpJohan Hovold
Commit ad3dd9592b2a ("soc: qcom: pmic_glink: disable UCSI on sc8280xp") disabled UCSI shortly after it had been enabled to fix a regression that was observed on the Lenovo ThinkPad X13s. Specifically, disconnecting an external display would trigger a system error and hypervisor reset but no one cared enough to track down the bug at the time. The same issue was recently observed on X Elite machines, and commit f47eba045e6c ("usb: typec: ucsi: Set orientation as none when connector is unplugged") worked around the underlying issue by setting the connector orientation to 'none' on disconnect events to avoid having the PHY driver crash the machine in one orientation. Enable UCSI support also on sc8280xp now that the DisplayPort disconnect crashes are gone. Cc: Abel Vesa <abel.vesa@linaro.org> Cc: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250326124944.6338-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-07MAINTAINERS: add entry for STM32 OCTO MEMORY MANAGER driverPatrice Chotard
Add myself as STM32 OCTO MEMORY MANAGER maintainer. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-3-1548736fd9d2@foss.st.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-07memory: Add STM32 Octo Memory Manager driverPatrice Chotard
Octo Memory Manager driver (OMM) manages: - the muxing between 2 OSPI busses and 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 - the split of the memory area shared between the 2 OSPI instances. - chip select selection override. - the time between 2 transactions in multiplexed mode. - check firewall access. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-2-1548736fd9d2@foss.st.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-07dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controllerPatrice Chotard
Add bindings for STM32 Octo Memory Manager (OMM) controller. OMM manages: - the muxing between 2 OSPI busses and 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 - the split of the memory area shared between the 2 OSPI instances. - chip select selection override. - the time between 2 transactions in multiplexed mode. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-1-1548736fd9d2@foss.st.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-07bus: firewall: Fix missing static inline annotations for stubsKrzysztof Kozlowski
Stubs in the header file for !CONFIG_STM32_FIREWALL case should be both static and inline, because they do not come with earlier declaration and should be inlined in every unit including the header. Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: stable@vger.kernel.org Fixes: 5c9668cfc6d7 ("firewall: introduce stm32_firewall framework") Link: https://lore.kernel.org/r/20250507092121.95121-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-07memory: bt1-l2-ctl: replace scnprintf() with sysfs_emit()Salah Triki
Documentation/filesystems/sysfs.rst mentions that show() should only use sysfs_emit() or sysfs_emit_at() when formating the value to be returned to user space. So replace scnprintf() with sysfs_emit(). Signed-off-by: Salah Triki <salah.triki@gmail.com> Link: https://lore.kernel.org/r/aBkw_p9GkH2fm2UJ@pc Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-07soc: sophgo: cv1800: rtcsys: New driver (handling RTC only)Alexander Sverdlin
Add driver for Sophgo CV1800 series SoC RTC subsystem. The RTC module comprises a 32kHz oscillator, Power-on-Reset (PoR) sub-module, HW state machine to control chip power-on, power-off and reset. Furthermore, the 8051 subsystem is located within RTCSYS including associated SRAM block. This patch only populates RTC sub-device. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250315224921.3627852-3-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-07dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 seriesJingbao Qiu
Add RTC devicetree binding for Sophgo CV1800 series SoC. The device is called RTC, but contains control registers of other HW blocks in its address space, most notably of Power-on-Reset (PoR) module, DW8051 IP (MCU core), accompanying SRAM, hence putting it in SoC subsystem. Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250315224921.3627852-2-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-07soc: sophgo: sg2044: Add support for SG2044 TOP syscon deviceInochi Amaoto
The SG2044 TOP device provide PLL clock function in its area. Add a mfd definition for it. Link: https://lore.kernel.org/r/20250418020325.421257-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-06firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14Aleksandrs Vinarskis
Allow particular machine accessing eg. efivars. Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Link: https://lore.kernel.org/r/20250426130203.37659-4-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-06firmware: ti_sci: Convert CPU latency constraint from us to msKendall Willis
Fix CPU resume latency constraint units sent to device manager through the TI SCI API. The device manager expects CPU resume latency to be in msecs which is passed in with the TI SCI API [1]. CPU latency constraints are set in userspace using the PM QoS framework which uses usecs as the unit. Since PM QoS uses usecs for units and the device manager expects msecs as the unit, TI SCI needs to convert from usecs to msecs before passing to device manager. [1] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/lpm.html#tisci-msg-lpm-set-latency-constraint Cc: stable@vger.kernel.org Fixes: a7a15754c7f7 ("firmware: ti_sci: add CPU latency constraint management") Signed-off-by: Kendall Willis <k-willis@ti.com> Link: https://lore.kernel.org/r/20250428205336.2947118-1-k-willis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06firmware: arm_scmi: quirk: Force perf level get fastchannelJohan Hovold
The Qualcomm SCP firmware in X1E machines like the Lenovo ThinkPad T14s does not set the FastChannel supported attribute bit for PERF_LEVEL_GET but crashes when falling back to regular messaging. Use the new SCMI quirk framework to force FastChannel initialisation for this implementation. Note that we can add an upper bound on the version matching when we learn which version has a fix (or limit matching using a SoC compatible string in the unlikely event that always enabling FC causes trouble somewhere). Link: https://lore.kernel.org/lkml/Z4Dt8E7C6upVtEGV@hovoldconsulting.com/ Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Message-Id: <20250430135146.5154-1-johan+linaro@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-05-06firmware: arm_scmi: quirk: Fix CLOCK_DESCRIBE_RATES tripletCristian Marussi
Convert an existing quirk in CLOCK_DESCRIBE_RATES parsing to the new quirk framework. This is a sort of a peculiar quirk since it matches any platform and any firmware. Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Message-Id: <20250429141108.406045-4-cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-05-06firmware: arm_scmi: Add common framework to handle firmware quirksCristian Marussi
Add a common framework to describe SCMI quirks and associate them with a specific platform or a specific set of SCMI firmware versions. All the matching SCMI quirks will be enabled when the SCMI core stack probes and after all the needed SCMI firmware versioning information was retrieved using the base protocol. Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Message-Id: <20250429141108.406045-3-cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-05-06firmware: arm_scmi: Ensure that the message-id supports fastchannelSibi Sankar
Currently the perf and powercap protocol relies on the protocol domain attributes, which just ensures that one fastchannel per domain, before instantiating fastchannels for all possible message-ids. Fix this by ensuring that each message-id supports fastchannel before initialization. Logs: | scmi: Failed to get FC for protocol 13 [MSG_ID:6 / RES_ID:0] - ret:-95. Using regular messaging | scmi: Failed to get FC for protocol 13 [MSG_ID:6 / RES_ID:1] - ret:-95. Using regular messaging | scmi: Failed to get FC for protocol 13 [MSG_ID:6 / RES_ID:2] - ret:-95. Using regular messaging CC: stable@vger.kernel.org Reported-by: Johan Hovold <johan+linaro@kernel.org> Closes: https://lore.kernel.org/lkml/ZoQjAWse2YxwyRJv@hovoldconsulting.com/ Fixes: 6f9ea4dabd2d ("firmware: arm_scmi: Generalize the fast channel support") Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> [Cristian: Modified the condition checked to establish support or not] Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Message-Id: <20250429141108.406045-2-cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-05-05ARM: vt8500: MAINTAINERS: Include vt8500 soc driver in maintainers entryKrzysztof Kozlowski
Include the SoC hwinfo/soc information driver in VT8500 maintainers entry. Link: https://lore.kernel.org/r/20250504173125.104419-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-05dt-bindings: reset: sophgo: Add SG2044 bindings.Inochi Amaoto
The SG2044 shares the same reset controller as SG2042, so it is just enough to use the compatible string of SG2042 as a basis. Add compatible string for the reset controller of SG2044. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250413223507.46480-6-inochiama@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-05-05MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driverLad Prabhakar
Add a new MAINTAINERS entry for the Renesas RZ/V2H(P) USB2PHY Port Reset driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20250415195131.281060-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-05-05reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)Lad Prabhakar
Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC. Enable control of USB2.0 PHY reset and power-down operations, including assert and deassert functionalities for the PHY. Leverage device tree (OF) data to support future SoCs with similar USB2PHY hardware but varying register configurations. Define initialization values and control register settings to ensure flexibility for upcoming platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-05-05dt-bindings: reset: Document RZ/V2H(P) USB2PHY resetLad Prabhakar
Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset controller. This block manages the reset and power-down of the USB 2.0 PHY, which is used in both host and function modes. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20250415195131.281060-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-05-05reset: Add devm_reset_control_array_get_exclusive_released()Patrice Chotard
Add the released variant of devm_reset_control_array_get_exclusive(). Needed by spi-smt32-ospi driver as same reset line is ulso used by stm32-omm driver. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20250411-b4-upstream_ospi_reset_update-v2-1-4de7f5dd2a91@foss.st.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-05-05soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoCLad Prabhakar
Add SoC identification for the RZ/V2N SoC using the System Controller (SYS) block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-05MAINTAINERS: Generalize ARM/RISC-V/RENESAS ARCHITECTUREUwe Kleine-König
Triggered by noticing that the pwm-rcar driver isn't covered by the Renesas maintainer entry, add this driver to it. Instead of adding it explicitly, just add a file regex for "rcar" (and drop the one entry that gets redundant by that). Looking at the output of $ git ls-files | grep rcar only shows files related to that architecture, so no X: line is currently needed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250404080045.367845-2-u.kleine-koenig@baylibre.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-04soc: Add VIA/WonderMedia SoC identification driverAlexey Charkov
Add a small SOC bus driver to parse the chip ID and revision made available on VIA/WonderMedia SoCs via their system configuration controller's SCC_ID register. This is intended to select appropriate sets of on-chip device quirks at runtime, as it has been found that even within the same SoC version there can be register-incompatible differences, such as with the SDMMC controller on WM8505 rev. A0-A1 vs. rev. A2. The list of SoC versions is compiled from various vendor source dumps and not all of them have corresponding mainline driver support. Some of them also have been seen with varying on-chip markings while sharing the same hardware chip ID's (as is the case with e.g. WM8850 vs. WM8950). In such cases the selection of names to use here among those seen in various source dumps and chip markings was arbitrary. Suggested by Krzysztof at [1] - thanks a lot! [1] https://lore.kernel.org/all/14de236b-e2a7-4bde-986d-1e5ffddd01b4@kernel.org/ Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250503-wmt-soc-driver-v3-2-2daa9056fa10@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-04dt-bindings: hwinfo: Add VIA/WonderMedia SoC identificationAlexey Charkov
VIA/WonderMedia SoC's have a chip ID register inside their system configuration controller space, which can be used to identify appropriate hardware quirks at runtime. Add binding for it. Signed-off-by: Alexey Charkov <alchark@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250503-wmt-soc-driver-v3-1-2daa9056fa10@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-01memory: renesas-rpc-if: Add RZ/G3E xSPI supportBiju Das
Add support for RZ/G3E xSPI. Compared to RPC-IF, it can support writes on memory-mapped area. Introduce struct rpcif_impl for holding the function pointers and data to handle the differences between xspi and rpc-if interface. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250424090000.136804-7-biju.das.jz@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-01memory: renesas-rpc-if: Add wrapper functionsBiju Das
Even though XSPI and RPCIF has different register layout, reuse the code by adding wrapper functions to support both XSPI and RPC-IF. While at it, replace error check for pm_runtime_resume_and_get(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250424090000.136804-6-biju.das.jz@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-27 20:54:20 +0000