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2023-04-18ASoC: cs35l56: Updates for B0 siliconMark Brown
Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>: These patches make some small changes to align with the B0 silicon revision.
2023-04-18dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775pBartosz Golaszewski
Add a compatible for the Power Domain Controller on SA8775p platforms. Increase the number of PDC pin mappings. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230417094635.302344-1-brgl@bgdev.pl Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18dt-bindings: reset: remove stih415/stih416 resetAlain Volmat
Remove the stih415 and stih416 reset dt-bindings since those two platforms are no more supported. Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230416200442.61554-1-avolmat@me.com Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127Alain Volmat
Remove compatible for stih415/stih416 and stid127 which are no more supported. Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20230416195857.61284-1-avolmat@me.com Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18dt-bindings: irqchip: sti: remove stih415/stih416 and stid127Alain Volmat
Remove bindings for the stih415/stih416/stid127 since they are not supported within the kernel anymore. Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230416190950.18929-1-avolmat@me.com Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18Merge tag 'mmc-v6.3-rc3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "MMC host: - sdhci_am654: Fix support for UHS-I SDR12 and SDR25 speed modes MEMSTICK: - Fix memory leak if card device never gets registered" * tag 'mmc-v6.3-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: memstick: fix memory leak if card device is never registered mmc: sdhci_am654: Set HIGH_SPEED_ENA for SDR12 and SDR25
2023-04-18KVM: arm64: Make vcpu flag updates non-preemptibleMarc Zyngier
Per-vcpu flags are updated using a non-atomic RMW operation. Which means it is possible to get preempted between the read and write operations. Another interesting thing to note is that preemption also updates flags, as we have some flag manipulation in both the load and put operations. It is thus possible to lose information communicated by either load or put, as the preempted flag update will overwrite the flags when the thread is resumed. This is specially critical if either load or put has stored information which depends on the physical CPU the vcpu runs on. This results in really elusive bugs, and kudos must be given to Mostafa for the long hours of debugging, and finally spotting the problem. Fix it by disabling preemption during the RMW operation, which ensures that the state stays consistent. Also upgrade vcpu_get_flag path to use READ_ONCE() to make sure the field is always atomically accessed. Fixes: e87abb73e594 ("KVM: arm64: Add helpers to manipulate vcpu flags among a set") Reported-by: Mostafa Saleh <smostafa@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230418125737.2327972-1-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2023-04-18i2c: xiic: xiic_xfer(): Fix runtime PM leak on error pathLars-Peter Clausen
The xiic_xfer() function gets a runtime PM reference when the function is entered. This reference is released when the function is exited. There is currently one error path where the function exits directly, which leads to a leak of the runtime PM reference. Make sure that this error path also releases the runtime PM reference. Fixes: fdacc3c7405d ("i2c: xiic: Switch from waitqueue to completion") Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2023-04-18i2c: cadence: cdns_i2c_master_xfer(): Fix runtime PM leak on error pathLars-Peter Clausen
The cdns_i2c_master_xfer() function gets a runtime PM reference when the function is entered. This reference is released when the function is exited. There is currently one error path where the function exits directly, which leads to a leak of the runtime PM reference. Make sure that this error path also releases the runtime PM reference. Fixes: 1a351b10b967 ("i2c: cadence: Added slave support") Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2023-04-18irqchip/gic-v3: Add Rockchip 3588001 erratum workaroundSebastian Reichel
Rockchip RK3588/RK3588s GIC600 integration does not support the sharability feature. Rockchip assigned Erratum ID #3588001 for this issue. Note, that the 0x0201743b ID is not Rockchip specific and thus there is an extra of_machine_is_compatible() check. The flags are named FORCE_NON_SHAREABLE to be vendor agnostic, since apparently similar integration design errors exist in other platforms and they can reuse the same flag. Co-developed-by: XiaoDong Huang <derrick.huang@rock-chips.com> Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Co-developed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: Lucas Tanure <lucas.tanure@collabora.com> Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230418142109.49762-2-sebastian.reichel@collabora.com
2023-04-18sparc: Use of_property_read_bool() for boolean propertiesRob Herring
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Link: https://lore.kernel.org/r/20230310144700.1541345-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18sparc: Use of_property_present() for testing DT property presenceRob Herring
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Link: https://lore.kernel.org/r/20230310144659.1541247-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18spi: spi-cadence: Add Slave mode supportMark Brown
Merge series from Srinivas Goud <srinivas.goud@amd.com>: Currently SPI Cadence controller works in Master mode only. Update driver to support Slave mode and also Full duplex transfer support in Slave mode
2023-04-18bus: mvebu-mbus: Remove open coded "ranges" parsingRob Herring
"ranges" is a standard property, and we have common helper functions for parsing it, so let's use them. Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Gregory Clement <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20230216181204.2895676-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-04-18ASoC: cs35l56: Rename mixer source defines for SoundWire DP1Richard Fitzgerald
Rename the mixer source defines from CS35L56_INPUT_SRC_SWIRE_RXn to CS35L56_INPUT_SRC_SWIRE_DP1_CHANNELn to match the latest datasheet. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230418144309.1100721-5-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18ASoC: cs35l56: Remove SDW2RX1 mixer sourceRichard Fitzgerald
The mixer source index value for SDW2RX1 is different between A1 and B0 silicon. As the driver doesn't provide a DAI for SDW2 just remove it as a mixer source option. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230418144309.1100721-4-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18ASoC: cs35l56: Remove SDW1 TX5 and TX6Richard Fitzgerald
Reduce SDW1 to 4 channels and remove the controls for SDW1 TX5 and TX6. The TX5 and TX6 channels have been removed from B0 silicon. There is no need to support them on A1 silicon. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230418144309.1100721-3-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18ASoC: cs35l56: Update comment on masking of EINT20 interruptsRichard Fitzgerald
EINT20 contains wake-source interrupts and also interface-blocked interrupts, which all default to unmasked after reset or wake. The comment in cs35l56_init() only mentioned the wake interrupts. Update the comment so it's clear that it's intentional to also mask the *_BLOCKED interrupts. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230418144309.1100721-2-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18f2fs: add has_enough_free_secs()Yangtao Li
Replace !has_not_enough_free_secs w/ has_enough_free_secs. BTW avoid nested 'if' statements in f2fs_balance_fs(). Signed-off-by: Yangtao Li <frank.li@vivo.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
2023-04-18f2fs: relax sanity check if checkpoint is corruptedJaegeuk Kim
1. extent_cache - let's drop the largest extent_cache 2. invalidate_block - don't show the warnings Reviewed-by: Chao Yu <chao@kernel.org> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
2023-04-18f2fs: refactor f2fs_gc to call checkpoint in urgent conditionJaegeuk Kim
The major change is to call checkpoint, if there's not enough space while having some prefree segments in FG_GC case. Reviewed-by: Chao Yu <chao@kernel.org> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
2023-04-18cpufreq: use correct unit when verify cur freqSanjay Chandrashekara
cpufreq_verify_current_freq checks() if the frequency returned by the hardware has a slight delta with the valid frequency value last set and returns "policy->cur" if the delta is within "1 MHz". In the comparison, "policy->cur" is in "kHz" but it's compared against HZ_PER_MHZ. So, the comparison range becomes "1 GHz". Fix this by comparing against KHZ_PER_MHZ instead of HZ_PER_MHZ. Fixes: f55ae08c8987 ("cpufreq: Avoid unnecessary frequency updates due to mismatch") Signed-off-by: Sanjay Chandrashekara <sanjayc@nvidia.com> [ sumit gupta: Commit message update ] Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-18ACPI: LPSS: Add 80862289 ACPI _HID for second PWM controller on Cherry TrailHans de Goede
On some Cherry Trail devices the second PWM controller uses 80862289 as ACPI _HID, rather then using 80862288 as is done for both controllers on most models. Add the missing 80862289 ACPI _HID, note this uses its own lpss_device_desc, without ".setup = bsw_pwm_setup" so that the pwm_lookup is not added for it. On devices where both controllers use the 80862288 _HID bsw_pwm_setup() does a UID check to avoid registering the lookup for the second controller but that will not work here. Adding the missing id fixes the second PWM controller no longer working after the entire LPSS1 island has been in D3 at least once, which causes the contents of the LPSS private registers to get lost. Adding the _HID makes acpi_lpss restore these when the controller moves from D3 to D0. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-18ACPI: bus: Ensure that notify handlers are not running after removalRafael J. Wysocki
Currently, acpi_device_remove_notify_handler() may return while the notify handler being removed is still running which may allow the module holding that handler to be torn down prematurely. Address this issue by making acpi_device_remove_notify_handler() wait for the handling of all the ACPI events in progress to complete before returning. Fixes: 5894b0c46e49 ("ACPI / scan: Move bus operations and notification routines to bus.c") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-18ACPI: bus: Add missing braces to acpi_sb_notify()Rafael J. Wysocki
As per the kernel coding style. No functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-18dt-bindings: remoteproc: Drop unneeded quotesRob Herring
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327170114.4102315-1-robh@kernel.org
2023-04-18Merge tag 'arm-fixes-6.3-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "There are a number of updates for devicetree files for Qualcomm, Rockchips, and NXP i.MX platforms, addressing mistakes in the DT contents: - Wrong GPIO polarity on some boards - Lower SD card interface speed for better stability - Incorrect power supply, clock, pmic, cache properties - Disable broken hbr3 on sc7280-herobrine - Devicetree warning fixes The only other changes are: - A regression fix for the Amlogic performance monitoring unit driver, along with two related DT changes. - imx_v6_v7_defconfig enables PCI support again. - Trivial fixes for tee, optee and psci firmware drivers, addressing compiler warning and error output" * tag 'arm-fixes-6.3-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits) firmware/psci: demote suspend-mode warning to info level arm64: dts: qcom: sc7280: remove hbr3 support on herobrine boards ARM: imx_v6_v7_defconfig: Fix unintentional disablement of PCI arm64: dts: rockchip: correct panel supplies on some rk3326 boards arm64: dts: rockchip: use just "port" in panel on RockPro64 arm64: dts: rockchip: use just "port" in panel on Pinebook Pro ARM: dts: imx6ull-colibri: Remove unnecessary #address-cells/#size-cells ARM: dts: imx7d-remarkable2: Remove unnecessary #address-cells/#size-cells arm64: dts: imx8mp-verdin: correct off-on-delay arm64: dts: imx8mm-verdin: correct off-on-delay arm64: dts: imx8mm-evk: correct pmic clock source arm64: dts: qcom: sc8280xp-pmics: fix pon compatible and registers arm64: dts: rockchip: Remove non-existing pwm-delay-us property arm64: dts: rockchip: Add clk_rtc_32k to Anbernic xx3 Devices tee: Pass a pointer to virt_to_page() perf/amlogic: adjust register offsets arm64: dts: meson-g12-common: resolve conflict between canvas & pmu arm64: dts: meson-g12-common: specify full DMC range arm64: dts: imx8mp: fix address length for LCDIF2 riscv: dts: canaan: drop invalid spi-max-frequency ...
2023-04-18Merge tag 'mvebu-arm64-6.4-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/arm mvebu arm64 for 6.4 (part 1) turris-mox-rwtm firmware: - prevent modification at runtime of the kobj_type struct * tag 'mvebu-arm64-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: firmware: turris-mox-rwtm: make kobj_type structure constant Link: https://lore.kernel.org/r/878repzfbp.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18ARM: mv78xx0: fix entries for gpios, buttons and usb portsJeremy J. Peper
Original code was largely copy-pasted from the reference board code, correct values to reflect the hardware actually present in the TS-WXL. Signed-off-by: Jeremy J. Peper <jeremy@jeremypeper.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18ARM: mv78xx0: add code to enable XOR and CRYPTO engines on mv78xx0Jeremy J. Peper
Adding missing code/values required to enable the XOR and CESA engines for this SoC Signed-off-by: Jeremy J. Peper <jeremy@jeremypeper.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18ARM: mv78xx0: set the correct driver for the i2c RTCJeremy J. Peper
Original code was largely copy-pasted from the reference board code, adjust to use the actual RTC chip present on the TS-WXL. Signed-off-by: Jeremy J. Peper <jeremy@jeremypeper.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18ARM: mv78xx0: adjust init logic for ts-wxl to reflect single core devJeremy J. Peper
Original code was largely copy-pasted from the reference board code, adjust pcie initialiazation to reflect the TS-WXL using the single-core variant of this SoC. Correct pcie_port_size to be a power of 2 as required. Signed-off-by: Jeremy J. Peper <jeremy@jeremypeper.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18selftests/proc: Assert clock_gettime(CLOCK_BOOTTIME) VS /proc/uptime ↵Frederic Weisbecker
monotonicity The first field of /proc/uptime relies on the CLOCK_BOOTTIME clock which can also be fetched from clock_gettime() API. Improve the test coverage while verifying the monotonicity of CLOCK_BOOTTIME accross both interfaces. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20230222144649.624380-9-frederic@kernel.org
2023-04-18selftests/proc: Remove idle time monotonicity assertionsFrederic Weisbecker
Due to broken iowait task counting design (cf: comments above get_cpu_idle_time_us() and nr_iowait()), it is not possible to provide the guarantee that /proc/stat or /proc/uptime display monotonic idle time values. Remove the assertions that verify the related wrong assumption so that testers and maintainers don't spend more time on that. Reported-by: Yu Liao <liaoyu15@huawei.com> Reported-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20230222144649.624380-8-frederic@kernel.org
2023-04-18MAINTAINERS: Remove stale email addressFrederic Weisbecker
Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230222144649.624380-7-frederic@kernel.org
2023-04-18timers/nohz: Remove middle-function __tick_nohz_idle_stop_tick()Frederic Weisbecker
There is no need for the __tick_nohz_idle_stop_tick() function between tick_nohz_idle_stop_tick() and its implementation. Remove that unnecessary step. Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230222144649.624380-6-frederic@kernel.org
2023-04-18timers/nohz: Add a comment about broken iowait counter update raceFrederic Weisbecker
The per-cpu iowait task counter is incremented locally upon sleeping. But since the task can be woken to (and by) another CPU, the counter may then be decremented remotely. This is the source of a race involving readers VS writer of idle/iowait sleeptime. The following scenario shows an example where a /proc/stat reader observes a pending sleep time as IO whereas that pending sleep time later eventually gets accounted as non-IO. CPU 0 CPU 1 CPU 2 ----- ----- ------ //io_schedule() TASK A current->in_iowait = 1 rq(0)->nr_iowait++ //switch to idle // READ /proc/stat // See nr_iowait_cpu(0) == 1 return ts->iowait_sleeptime + ktime_sub(ktime_get(), ts->idle_entrytime) //try_to_wake_up(TASK A) rq(0)->nr_iowait-- //idle exit // See nr_iowait_cpu(0) == 0 ts->idle_sleeptime += ktime_sub(ktime_get(), ts->idle_entrytime) As a result subsequent reads on /proc/stat may expose backward progress. This is unfortunately hardly fixable. Just add a comment about that condition. Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230222144649.624380-5-frederic@kernel.org
2023-04-18timers/nohz: Protect idle/iowait sleep time under seqcountFrederic Weisbecker
Reading idle/IO sleep time (eg: from /proc/stat) can race with idle exit updates because the state machine handling the stats is not atomic and requires a coherent read batch. As a result reading the sleep time may report irrelevant or backward values. Fix this with protecting the simple state machine within a seqcount. This is expected to be cheap enough not to add measurable performance impact on the idle path. Note this only fixes reader VS writer condition partitially. A race remains that involves remote updates of the CPU iowait task counter. It can hardly be fixed. Reported-by: Yu Liao <liaoyu15@huawei.com> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230222144649.624380-4-frederic@kernel.org
2023-04-18timers/nohz: Only ever update sleeptime from idle exitFrederic Weisbecker
The idle and IO sleeptime statistics appearing in /proc/stat can be currently updated from two sites: locally on idle exit and remotely by cpufreq. However there is no synchronization mechanism protecting concurrent updates. It is therefore possible to account the sleeptime twice, among all the other possible broken scenarios. To prevent from breaking the sleeptime accounting source, restrict the sleeptime updates to the local idle exit site. If there is a delta to add since the last update, IO/Idle sleep time readers will now only compute the delta without actually writing it back to the internal idle statistic fields. This fixes a writer VS writer race. Note there are still two known reader VS writer races to handle. A subsequent patch will fix one. Reported-by: Yu Liao <liaoyu15@huawei.com> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230222144649.624380-3-frederic@kernel.org
2023-04-18timers/nohz: Restructure and reshuffle struct tick_schedFrederic Weisbecker
Restructure and group fields by access in order to optimize cache layout. While at it, also add missing kernel doc for two fields: @last_jiffies and @idle_expires. Reported-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230222144649.624380-2-frederic@kernel.org
2023-04-18Merge tag 'mvebu-dt64-6.4-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.4 (part 1) Enlarge PCI memory window on Machiatobin (Armada 7040 based) Add supoport for the GL.iNet GL-MV1000 (Armada 3700 based) Add missing phy-mode on the cn9310 Align thermal node names with bindings * tag 'mvebu-dt64-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM64: dts: marvell: cn9310: Add missing phy-mode arm64: dts: marvell: add DTS for GL.iNet GL-MV1000 arm64: dts: marvell: align thermal node names with bindings arm64: dts: marvell: mochabin: enlarge PCI memory window Link: https://lore.kernel.org/r/87bkjlzfcw.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18Merge tag 'mvebu-dt-6.4-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt for 6.4 (part 1) Add missing phy-mode and fixed links for kirkwood, orion5 and Armada (370, XP, 38x) SoCs * tag 'mvebu-dt-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: dts: armada: Add missing phy-mode and fixed links ARM: dts: orion5: Add missing phy-mode and fixed links ARM: dts: kirkwood: Add missing phy-mode and fixed links Link: https://lore.kernel.org/r/87edohzfeg.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18spi: spi-cadence: Add support for Slave modeSrinivas Goud
Currently SPI Cadence controller works only in Master mode. Updated interrupt handler for Full duplex transfer in Slave mode. Interrupt handler rely on the TX empty interrupt even for Slave mode transfer due to below HW limitation. HW limitation: AR 65885 - SPI Controller Might Not Update RX_NEMPTY Flag, Showing Incorrect Status Of The Receive FIFO SPI Slave mode works in the following manner: 1. One transfer can be finished only after all transfer->len data been transferred to master device. 2. Slave device only accepts transfer->len data. Any data longer than this from master device will be dropped. Any data shorter than this from master will cause SPI to be stuck due to the above behavior. 3. The stale data present in RXFIFO will be dropped in unprepared hardware transfer function. Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> Link: https://lore.kernel.org/r/1681825625-10265-3-git-send-email-srinivas.goud@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18spi: spi-cadence: Switch to spi_controller structureSrinivas Goud
Replace spi_master structure with spi_controller structure. spi_controller structure provides interface support for both SPI master and slave controller. Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> Link: https://lore.kernel.org/r/1681825625-10265-2-git-send-email-srinivas.goud@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-04-18Merge tag 'v6.4-rockchip-dts64-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt On the Rock5b a fix the newly added rtc node and cpu-regulators for the big cluster. Volume-keys (via adc) for the Pinephone Pro, display support for the Anbernic RG353. As well as gpio-ranges for rk356x and fixes for the audio-codec node-names on two boards. * tag 'v6.4-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x arm64: dts: rockchip: add panel to Anbernic RG353 series Link: https://lore.kernel.org/r/5144826.MHq7AAxBmi@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18ARM: config: Update Vexpress defconfigLinus Walleij
The Versatile Express should conform to standard contemporary kernel features: add NO_HZ_FULL and HIGH_RES_TIMERS. Also add the AFS flash partitions as these are used on the platform. The removed SCHED_DEBUG is due to Kconfig changes. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230418082427.186677-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-18Merge tag 'opp-updates-6.4' of ↵Rafael J. Wysocki
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm into pm-opp Pull OPP updates for 6.4 from Viresh Kumar: "- Use of_property_present() for testing DT property presence (Rob Herring). - Add set_required_opps() callback to the 'struct opp_table', to make the code paths cleaner (Viresh Kumar)." * tag 'opp-updates-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: OPP: Move required opps configuration to specialized callback OPP: Handle all genpd cases together in _set_required_opps() opp: Use of_property_present() for testing DT property presence
2023-04-18thermal: intel: int340x: Add DLVR support for RFIM controlSrinivas Pandruvada
Add support for DLVR (Digital Linear Voltage Regulator) attributes, which can be used to control RFIM. Here instead of "fivr" another directory "dlvr" is created with DLVR attributes: /sys/bus/pci/devices/0000:00:04.0/dlvr ├── dlvr_freq_mhz ├── dlvr_freq_select ├── dlvr_hardware_rev ├── dlvr_pll_busy ├── dlvr_rfim_enable └── dlvr_spread_spectrum_pct └── dlvr_control_mode └── dlvr_control_lock Attributes dlvr_freq_mhz (RO): Current DLVR PLL frequency in MHz. dlvr_freq_select (RW): Sets DLVR PLL clock frequency. dlvr_hardware_rev (RO): DLVR hardware revision. dlvr_pll_busy (RO): PLL can't accept frequency change when set. dlvr_rfim_enable (RW): 0: Disable RF frequency hopping, 1: Enable RF frequency hopping. dlvr_control_mode (RW): Specifies how frequencies are spread. 0: Down spread, 1: Spread in Center. dlvr_control_lock (RW): 1: future writes are ignored. dlvr_spread_spectrum_pct (RW) A write to this register updates the DLVR spread spectrum percent value. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> [ rjw: Subject edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-18tick/common: Align tick period with the HZ tick.Sebastian Andrzej Siewior
With HIGHRES enabled tick_sched_timer() is programmed every jiffy to expire the timer_list timers. This timer is programmed accurate in respect to CLOCK_MONOTONIC so that 0 seconds and nanoseconds is the first tick and the next one is 1000/CONFIG_HZ ms later. For HZ=250 it is every 4 ms and so based on the current time the next tick can be computed. This accuracy broke since the commit mentioned below because the jiffy based clocksource is initialized with higher accuracy in read_persistent_wall_and_boot_offset(). This higher accuracy is inherited during the setup in tick_setup_device(). The timer still fires every 4ms with HZ=250 but timer is no longer aligned with CLOCK_MONOTONIC with 0 as it origin but has an offset in the us/ns part of the timestamp. The offset differs with every boot and makes it impossible for user land to align with the tick. Align the tick period with CLOCK_MONOTONIC ensuring that it is always a multiple of 1000/CONFIG_HZ ms. Fixes: 857baa87b6422 ("sched/clock: Enable sched clock early") Reported-by: Gusenleitner Klaus <gus@keba.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/20230406095735.0_14edn3@linutronix.de Link: https://lore.kernel.org/r/20230418122639.ikgfvu3f@linutronix.de
2023-04-18spi: cadence-quadspi: fix suspend-resume implementationsDhruva Gole
The cadence QSPI driver misbehaves after performing a full system suspend resume: ... spi-nor spi0.0: resume() failed ... This results in a flash connected via OSPI interface after system suspend- resume to be unusable. fix these suspend and resume functions. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230417091027.966146-3-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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