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2018-12-06ARM: dts: sunxi: h3/h5: Add clock accuracy for external oscillatorsChen-Yu Tsai
The H3 datasheet specifies a tolerance range for the external oscillators used. Add them to the device tree as the clock accuracy. The internal oscillator is left unchanged, as it will be removed later. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-12-06ARM: imx: update the cpu power up timing setting on i.mx6sxAnson Huang
The sw2iso count should cover ARM LDO ramp-up time, the MAX ARM LDO ramp-up time may be up to more than 100us on some boards, this patch sets sw2iso to 0xf (~384us) which is the reset value, and it is much more safe to cover different boards, since we have observed that some customer boards failed with current setting of 0x2. Fixes: 05136f0897b5 ("ARM: imx: support arm power off in cpuidle for i.mx6sx") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-05ARM: dts: r8a7744-iwg20m: Add SPI NOR supportBiju Das
Add support for the SPI NOR device used to boot up the system to the iWave RZ/G1N Qseven System On Module DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-05arm64: dts: renesas: r8a77995: draak: Add backlightLaurent Pinchart
Add the backlight device for the LVDS1 output, in preparation for panel support. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-05ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOMBiju Das
The iWave RZ/G1N board is almost identical to RZ/G1M. cmt and rwdt modules are SoC specific and should be part of board dts rather than SoM dtsi. By moving these nodes to the common dtsi it allows cmt and rwdt to be enabled on both of these boards with less lines of code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-05arm64: dts: qcom: sdm845: Add UART nodesMatthias Kaehlcke
This adds nodes for all possible UARTs to sdm845.dtsi. By default only configure the RX/TX lines with pinctrl. Boards that use UARTs with flow control can overwrite the configuration in the <board>.dtsi. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-12-05arm64: dts: mt8173: Add GCE nodeHoulong Wei
This patch adds the device node of the GCE hardware for CMDQ module. Signed-off-by: Houlong Wei <houlong.wei@mediatek.com> Signed-off-by: HS Liao <hs.liao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-12-05ARM: dts: sun8i: a33: Drop audio codec oversampling rate to 128 fsChen-Yu Tsai
The current oversampling rate of 512 means that for 48 kHz 16 bit stereo, the MCLK is running at the same rate as the module clock, so there is no head room to support higher sampling rates. The codec however supports up to 192 kHz for playback. This patch drops the oversampling rate from 512 to 128, so that 192 kHz audio can be played back directly without downsampling. Ideally we should be using different oversampling rates for different sampling rates, but that's not possible without a platform-specific machine driver. Fixes: 870f1bd1f5e9 ("ARM: dts: sun8i: Add audio codec, dai and card for A33") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05arm64: dts: allwinner: a64: Add Video Engine nodePaul Kocialkowski
This adds the Video Engine node for the A64. Since it can map the whole DRAM range, there is no particular need for a reserved memory node (unlike platforms preceding the A33). Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05arm64: dts: allwinner: a64: Add support for the SRAM C1 sectionPaul Kocialkowski
Add the description for the SRAM C1 section to the A64 device-tree. Since there is no entry for this section in the A64 manual, the base address and size were only verified to be consistent empirically. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05ARM: dts: sun8i: h3: Remove unnecessary reserved memory nodePaul Kocialkowski
Just like on the A33, the video engine on the H3 can map any address in memory, so there is no particular need to have reserved memory at a fixed address. As a result, remove the reserved memory node and let the kernel allocate the CMA pool wherever it sees fit. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05ARM: dts: sun8i: a33: Remove unnecessary reserved memory nodePaul Kocialkowski
While we believed that the memory for the video engine had to be kept in the first 256 MiBs of DRAM, this is no longer true starting with the A33 and any address can be mapped. As a result, remove the reserved memory node and let the kernel allocate the CMA pool wherever it sees fit. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05ARM: dts: imx7d-pico: Describe the Wifi clockFabio Estevam
The Wifi chip should be clocked by a 32kHz clock coming from i.MX7D CLKO2 output pin, so describe the pinmux and clock hierarchy in the device tree to allow the Wifi chip to be properly clocked. Managed to successfully test Wifi with such change. Used the standard nvram.txt file provided by TechNexion, which selects an external 32kHz clock for the Wifi chip by default. Fixes: 99a52450c707 ("ARM: dts: imx7d-pico: Add Wifi support") Suggested-by: Arend van Spriel <arend.vanspriel@broadcom.com> Tested-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-04ARM: dts: meson: meson8b: add the CPU OPP tablesMartin Blumenstingl
The values are taken from Amlogic's 3.10 kernel sources. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson: meson8: add the CPU OPP tableMartin Blumenstingl
The values are taken from Amlogic's 3.10 kernel sources. Their sources have a "meson8m2_n200_2G.dtd" which defines a different voltage table: - 0.86V for 96MHz - (values in between omitted) - 1.14V for 1.992GHz The reason for this is simply the hardware design because the voltage regulator on this board is has a minimum output of 0.86V and a maximum output of 1.14V. The recommended settings are added with this patch instead of using the values that are only valid for one board. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson8b: add the Cortex-A5 global timerMartin Blumenstingl
The Meson8b SoC is using four Cortex-A5 cores. These come with an ARM global timer. This adds the Cortex-A5 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson8b: add the ARM TWD timerMartin Blumenstingl
The Meson8B SoC is using four ARM Cortex-A5 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on this SoC. Suggested-by: Carlo Caione <carlo@endlessm.com> [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson8: add the Cortex-A9 global timerMartin Blumenstingl
The Meson8 and Meson8m2 SoCs are using four Cortex-A9 cores. These come with an ARM global timer. This adds the Cortex-A9 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson8: add the ARM TWD timerMartin Blumenstingl
The Meson8 and Meson8m2 SoC are using four ARM Cortex-A9 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on these two SoCs. Suggested-by: Carlo Caione <carlo@endlessm.com> [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripheralsMartin Blumenstingl
The public Meson8b (S805) datasheet describes a memory region called "A9 Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a simple-bus node and move all peripherals that are part of this memory region. This makes the .dts a bit easier to read. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04Merge tag 'meson-clk-headers-4.21-1' of git://github.com/BayLibre/clk-meson ↵Kevin Hilman
into v4.21/dt Update for meson clocks bindings targeted at v4.21: - Export Meson8b CPU post dividers * tag 'meson-clk-headers-4.21-1' of git://github.com/BayLibre/clk-meson: dt-bindings: clock: meson8b: export the CPU post dividers
2018-12-04ARM: dts: r8a7744: Add PCIe Controller device nodeBiju Das
Add a device node for the PCIe controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add xhci supportBiju Das
Add a device node for the xhci controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add MSIOF[012] supportBiju Das
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add QSPI supportBiju Das
Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DBBiju Das
This patch adds support for the camera daughter board which is connected to iWave's RZ/G1N Qseven carrier board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add TPU supportBiju Das
Add TPU support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add PWM SoC supportBiju Das
Add the definitions for pwm[0123456] to the SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add IPMMU DT nodesBiju Das
Add the six IPMMU instances found in the r8a7744 to DT with a disabled status. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add VSP supportBiju Das
Add VSP support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: add VIN dt supportBiju Das
Add VIN[012] support to SoC dt. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add CMT SoC specific supportBiju Das
Add CMT[01] support to SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add thermal device to DTBiju Das
This patch instantiates the thermal sensor module with thermal-zone support. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add IRQC supportBiju Das
Describe the IRQC interrupt controller in the r8a7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add CAN supportBiju Das
Add the definitions for can0 and can1 to the r8a7744 SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add audio supportBiju Das
Add sound support for the RZ/G1N SoC (a.k.a. R8A7744). This work is based on similar work done on the R8A7743 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add RWDT nodeBiju Das
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodesBiju Das
Add usb dmac and hsusb device nodes on RZ/G1N SoC dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: USB 2.0 host supportBiju Das
Describe internal PCI bridge devices, USB phy device and link PCI USB devices to USB phy. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Enable SDHI0 controllerBiju Das
Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20m: Add eMMC supportBiju Das
Add eMMC support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add MMC nodeBiju Das
Add MMC node to the DT of the r8a7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SDHI nodesBiju Das
Add SDHI nodes to the DT of the r8a7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add I2C and IIC supportBiju Das
Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add [H]SCIF{A|B} supportBiju Das
Describe [H]SCIF{|A|B} ports in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SMP supportBiju Das
Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Also add cpu1 phandle node to the PMU interrupt-affinity property. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add Ethernet AVB supportBiju Das
Add Ethernet AVB support for R8A7744 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add GPIO supportBiju Das
Describe GPIO blocks in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744: Add SYS-DMAC supportBiju Das
Describe SYS-DMAC0/1 in the R8A7744 device tree. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-04ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1NBiju Das
Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit (git 2.34.1) at 2025-09-11 18:32:14 +0000