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2019-09-03mt76: mt76x0e: don't use hw encryption for MT7630EStanislaw Gruszka
Since 41634aa8d6db ("mt76: only schedule txqs from the tx tasklet") I can observe firmware hangs on MT7630E on station mode: tx stop functioning after minor activity (rx keep working) and on module unload device fail to stop with messages: [ 5446.141413] mt76x0e 0000:06:00.0: TX DMA did not stop [ 5449.176764] mt76x0e 0000:06:00.0: TX DMA did not stop Loading module again results in failure to associate with AP. Only machine power off / power on cycle can make device work again. It's unclear why commit 41634aa8d6db causes the problem, but it is related to HW encryption. Since issue is a firmware hang, that is super hard to debug, just disable HW encryption as fix for the issue. Fixes: 41634aa8d6db ("mt76: only schedule txqs from the tx tasklet") Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2019-09-03Merge tag 'renesas-arm64-dt-for-v5.4-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM64 DT updates for v5.4 (take two) - Sort nodes in various SoC and board DTSes, - HDMI sound for HiHope RZ/G2M and R-Car M3-N Salvator-X(S) boards, - Limit EtherAVB to 100Mbps on the Ebisu and Draak boards, - Small fixes and improvements. * tag 'renesas-arm64-dt-for-v5.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits) arm64: dts: renesas: Update 'vsps' properties for readability arm64: dts: renesas: r8a77965-salvator-x(s): Enable HDMI sound arm64: dts: renesas: r8a774c0: Fix register range of display node arm64: dts: renesas: r8a77970: Sort nodes arm64: dts: renesas: r8a7796: Sort nodes arm64: dts: renesas: r8a774c0: Sort nodes arm64: dts: renesas: r8a774c0: cat874: Sort nodes arm64: dts: renesas: r8a774a1: Sort nodes arm64: dts: renesas: r8a77980: Fix IPMMU-VC0 base address arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps arm64: dts: renesas: hihope-common: Add HDMI audio support arm64: dts: renesas: r8a774c0: cat874: Add definition for 12V regulator arm64: dts: renesas: r8a774c0: Point LVDS0 to its companion LVDS1 arm64: dts: renesas: r8a77995: Sort nodes arm64: dts: renesas: r8a77995: draak: Sort nodes arm64: dts: renesas: r8a77990: Sort nodes arm64: dts: renesas: r8a77990: ebisu: Sort nodes arm64: dts: renesas: r8a77980: v3hsk: Sort nodes arm64: dts: renesas: r8a77980: condor: Sort nodes arm64: dts: renesas: r8a77970: v3msk: Sort nodes ... Link: https://lore.kernel.org/r/20190823123643.18799-4-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'renesas-arm-dt-for-v5.4-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.4 - Fix HSCIF PM Domain on R-Car H1, - PMU support for RZ/G1C. * tag 'renesas-arm-dt-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: dts: r8a77470: Add PMU device node ARM: dts: r8a7779: Use SYSC "always-on" PM Domain for HSCIF Link: https://lore.kernel.org/r/20190823123643.18799-2-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03iommu: Don't use sme_active() in generic codeJoerg Roedel
Switch to the generic function mem_encrypt_active() because sme_active() is x86 specific and can't be called from generic code on other platforms than x86. Fixes: 2cc13bb4f59f ("iommu: Disable passthrough mode when SME is active") Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-09-03Merge tag 'amlogic-dt64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.4 Highlights - new SoCs (G12B family): S922X, A311D - new SoCs (SM1 family): S905X3 - new board: SEI Robotics SEI610 (SM1/S905X3) - new board: Khadas VIM3 (G12B/A311D) - DVFS/CPUfreq support on G12[AB] family * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits) arm64: dts: add support for SM1 based SEI Robotics SEI610 dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings dt-bindings: arm: amlogic: add SM1 bindings arm64: dts: meson-g12b-odroid-n2: enable DVFS arm64: dts: meson-g12b-khadas-vim3: add initial device-tree dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml arm64: dts: amlogic: g12 CPU timers stop in suspend arm64: dts: meson-g12b: support a311d and s922x cpu operating points dt-bindings: arm: amlogic: add support for the Khadas VIM3 dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC arm64: dts: meson: add video decoder entries arm64: dts: meson-gx: add video decoder entry dt-bindings: media: amlogic,vdec: add default compatible arm64: dts: meson: add ethernet fifo sizes arm64: dts: meson-g12b: add cpus OPP tables arm64: dts: meson-g12a: enable DVFS on G12A boards arm64: dts: meson-g12a: add cpus OPP table arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi ... Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'amlogic-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.4 Highlights - odroid-c1: use MAC address from efuse - add VDD_EE regulator to several boards * tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: odroidc1: use the MAC address stored in the eFuse ARM: dts: meson8b: mxq: add the VDDEE regulator ARM: dts: meson8b: odroidc1: add the VDDEE regulator ARM: dts: meson8b: ec100: add the VDDEE regulator ARM: dts: meson8b: add the PWM_D output pin ARM: dts: meson8b: add ethernet fifo sizes Link: https://lore.kernel.org/r/7hzhk3bi96.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'socfpga_dts_updates_for_v5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.4 - Add reset properties for various peripherals - QSPI OCP and DMA on Arria10 - DMA on Agilex/Stratix10 - Update NAND controller bindings to match driver update - Add NAND controller to Stratix10 - VINING FPGA board fixups - Update button mapping - Adjust GMAC1 clock and TXD skew settings - Add missing reset-names for dma controller * tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: add missing reset-names for dma ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA ARM: dts: socfpga: Fix up button mapping on VINING FPGA arm64: dts: stratix10: Add NAND device node ARM: dts: socfpga: update to new Denali NAND binding arm64: dts: agilex/stratix10: Add reset properties for DMA ARM: dts: socfpga: add reset properties for DMA ARM: dts: socfpga: add the QSPI OCP reset property on arria10 Link: https://lore.kernel.org/r/20190819141659.26414-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'v5.4-rockchip-dts64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt PWM-Fan and nor-flash for the RockPro64, a better display mode for the Kevin Chromebook and a new board the Leez P710 SBC. * tag 'v5.4-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC arm64: dts: rockchip: enable internal SPI flash for RockPro64. arm64: dts: rockchip: Add PWM fan for RockPro64 arm64: dts: rockchip: Specify override mode for kevin panel Link: https://lore.kernel.org/r/20190819141659.26414-1-dinguyen@kernel.org Link: https://lore.kernel.org/r/2362486.gYoCZEsBuK@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03iommu/vt-d: Remove global page flush supportJacob Pan
Global pages support is removed from VT-d spec 3.0. Since global pages G flag only affects first-level paging structures and because DMA request with PASID are only supported by VT-d spec. 3.0 and onward, we can safely remove global pages support. For kernel shared virtual address IOTLB invalidation, PASID granularity and page selective within PASID will be used. There is no global granularity supported. Without this fix, IOTLB invalidation will cause invalid descriptor error in the queued invalidation (QI) interface. Fixes: 1c4f88b7f1f9 ("iommu/vt-d: Shared virtual address in scalable mode") Reported-by: Sanjay K Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-09-03iommu/arm-smmu-v3: Fix build error without CONFIG_PCI_ATSYueHaibing
If CONFIG_PCI_ATS is not set, building fails: drivers/iommu/arm-smmu-v3.c: In function arm_smmu_ats_supported: drivers/iommu/arm-smmu-v3.c:2325:35: error: struct pci_dev has no member named ats_cap; did you mean msi_cap? return !pdev->untrusted && pdev->ats_cap; ^~~~~~~ ats_cap should only used when CONFIG_PCI_ATS is defined, so use #ifdef block to guard this. Fixes: bfff88ec1afe ("iommu/arm-smmu-v3: Rework enabling/disabling of ATS for PCI masters") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2019-09-03Merge tag 'v5.4-rockchip-dts32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt A lot more love for Veyron devices with cleanups in the display and wifi areas and also a 100ms speedup as a delay isn't needed anymore. New boards are Tiger and Fievel from the Veyron family and the Mecer Xtreme Mini S6, which I think is the first consumer-grade rk3229-based device in the kernel. * tag 'v5.4-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: add device tree for Mecer Xtreme Mini S6 Revert "ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators" ARM: dts: rockchip: Add pin names for rk3288-veyron fievel ARM: dts: rockchip: A few fixes for veyron-{fievel,tiger} ARM: dts: rockchip: Cleanup style around assignment operator ARM: dts: rockchip: add veyron-tiger board ARM: dts: rockchip: add veyron-fievel board dt-bindings: ARM: dts: rockchip: Add bindings for rk3288-veyron-{fievel,tiger} ARM: dts: rockchip: consolidate veyron panel and backlight settings ARM: dts: rockchip: move rk3288-veryon display settings into a separate file ARM: dts: rockchip: Limit WiFi TX power on rk3288-veyron-jerry ARM: dts: rockchip: Specify rk3288-veyron-minnie's display timings ARM: dts: rockchip: Specify rk3288-veyron-chromebook's display timings Link: https://lore.kernel.org/r/1611583.rKl1eQBRh8@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'samsung-dt-5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.4 1. Add AHCI to Exynos5250, 2. Add camera and GPU power domains to Exynos5422, 3. Minor cleanup. * tag 'samsung-dt-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add CAM power domain to Exynos5422/5800 ARM: dts: exynos: Add G3D power domain to Exynos542x ARM: dts: exynos: Move MSC power domain to the right (sorted) place ARM: dts: exynos: Add port map to Exynos5250 AHCI node ARM: dts: exynos: Use space after '=' in exynos4412-itop-scp-core Link: https://lore.kernel.org/r/20190816163042.6604-2-krzk@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'omap-for-v5.4/soc-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc SoC changes for omap variants for v5.4 The first change moves platform-specific asm-offsets.h to arch/arm/mach-omap2 to fix iessu with parallel build with CONFIG_IKHEADERS, and the second change removes a useless kfree. Note that the first change causes a trivial merge conflict with the iommu changes for arch/arm/mach-omap2/Makefile. * tag 'omap-for-v5.4/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Delete an unnecessary kfree() call in omap_hsmmc_pdata_init() ARM: OMAP2+: move platform-specific asm-offset.h to arch/arm/mach-omap2 Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'at91-5.4-soc' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc AT91 SoC for 5.4 - MAINTAINERS updates - a generated headers parallel build fix * tag 'at91-5.4-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: mailmap: map old company name to new one @microchip.com MAINTAINERS: at91: remove the TC entry MAINTAINERS: at91: Collect all pinctrl/gpio drivers in same entry ARM: at91: move platform-specific asm-offset.h to arch/arm/mach-at91 Link: https://lore.kernel.org/r/20190825203222.GA22800@piout.net Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'imx-soc-5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc i.MX SoC changes for 5.4: - Drop AR8031 PHY TX delay adjusting from i.MX7D machine code, as it's superfluous due to the recent changes to Atheros AT803X driver. - Select TIMER_IMX_SYS_CTR for arm64 ARCH_MXC platform, since the system counter is needed as broadcast timer for cpuidle support. * tag 'imx-soc-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: stop adjusting ar8031 phy tx delay arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms Link: https://lore.kernel.org/r/20190825153237.28829-2-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'aspeed-5.4-arch' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/soc ASPEED architecture updates for 5.4 This adds support for the new ASPEED AST2600 BMC SoC. * tag 'aspeed-5.4-arch' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: ARM: aspeed: Enable SMP boot ARM: aspeed: Add ASPEED AST2600 architecture ARM: aspeed: Select timer in each SoC dt-bindings: arm: cpus: Add ASPEED SMP Link: https://lore.kernel.org/r/CACPK8Xc1aSp5fXL3cEzC9SJsCXG2JwsSPpQrW3a09dkvhCyHHA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'vexpress-update-5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/soc ARMv7 Vexpress update for v5.4 Single cleanup patch handling type checks using cppcheck tool (bitwise shift by more than 31 on a 32 bit type) * tag 'vexpress-update-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: ARM: vexpress: Cleanup cppcheck shifting warning Link: https://lore.kernel.org/r/20190814172441.26143-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03s390/base: remove unused s390_base_mcck_handlerVasily Gorbik
s390_base_mcck_handler was used during system reset if diag308 set was not available. But after commit d485235b0054 ("s390: assume diag308 set always works") is a dead code and could be removed. Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2019-09-03s390/sclp: Fix bit checked for has_siplPhilipp Rudo
Fixes: c9896acc7851 ("s390/ipl: Provide has_secure sysfs attribute") Cc: stable@vger.kernel.org # 5.2+ Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Philipp Rudo <prudo@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
2019-09-03spi: spi-fsl-dspi: Fix race condition in TCFQ/EOQ interruptVladimir Oltean
When the driver is working in TCFQ/EOQ mode (i.e. interacts with the SPI controller's FIFOs directly) the following sequence of operations happens: - The first byte of the tx buffer gets pushed to the TX FIFO (dspi->len gets decremented). This triggers the train of interrupts that handle the rest of the bytes. - The dspi_interrupt handles a TX confirmation event. It reads the newly available byte from the RX FIFO, checks the dspi->len exit condition, and if there's more to be done, it kicks off the next interrupt in the train by writing the next byte to the TX FIFO. Now the problem is that the wait queue is woken up one byte too early, because dspi->len becomes 0 as soon as the byte has been pushed into the TX FIFO. Its interrupt has not yet been processed and the RX byte has not been put from the FIFO into the buffer. Depending on the timing of the wait queue wakeup vs the handling of the last dspi_interrupt, it can happen that the main SPI message pump thread has already returned back into the spi_device driver. When the rx buffer is on stack (which it can be, because in this mode, the DSPI doesn't do DMA), the last interrupt will perform a memory write into an rx buffer that has been freed. This manifests as stack corruption. The solution is to only wake up the wait queue when dspi_rxtx says so, i.e. after it has processed the last TX confirmation interrupt and collected the last RX byte. Fixes: c55be3059159 ("spi: spi-fsl-dspi: Use poll mode in case the platform IRQ is missing") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20190903105708.32273-1-olteanv@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-03spi: uniphier: introduce polling modeKeiji Hayashibara
Introduce new polling mode for short size transfer. Either the estimated transfer time is estimated to exceed 200us, or polling loop actually exceeds 200us, it switches to irq mode. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Link: https://lore.kernel.org/r/1567488661-11428-4-git-send-email-hayashibara.keiji@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-03spi: uniphier: remove unnecessary codeKeiji Hayashibara
This commit removed if() because priv->is_save_param is always true. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Link: https://lore.kernel.org/r/1567488661-11428-3-git-send-email-hayashibara.keiji@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-03spi: uniphier: fix wrong register overwriteKeiji Hayashibara
When it changes the spi mode, the register is overwritten incorrectly. This commit fixes this register overwrite. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Link: https://lore.kernel.org/r/1567488661-11428-2-git-send-email-hayashibara.keiji@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-03regulator: add missing 'static inline' to a helper's stubBartosz Golaszewski
The build fails when CONFIG_REGULATOR is not selected because the stub for regulator_bulk_set_supply_names() is missing the 'static inline' attribute. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Link: https://lore.kernel.org/r/20190902151332.28058-1-brgl@bgdev.pl Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-03irqdomain: Add the missing assignment of domain->fwnode for named fwnodeDexuan Cui
Recently device pass-through stops working for Linux VM running on Hyper-V. git-bisect shows the regression is caused by the recent commit 467a3bb97432 ("PCI: hv: Allocate a named fwnode ..."), but the root cause is that the commit d59f6617eef0 forgets to set the domain->fwnode for IRQCHIP_FWNODE_NAMED*, and as a result: 1. The domain->fwnode remains to be NULL. 2. irq_find_matching_fwspec() returns NULL since "h->fwnode == fwnode" is false, and pci_set_bus_msi_domain() sets the Hyper-V PCI root bus's msi_domain to NULL. 3. When the device is added onto the root bus, the device's dev->msi_domain is set to NULL in pci_set_msi_domain(). 4. When a device driver tries to enable MSI-X, pci_msi_setup_msi_irqs() calls arch_setup_msi_irqs(), which uses the native MSI chip (i.e. arch/x86/kernel/apic/msi.c: pci_msi_controller) to set up the irqs, but actually pci_msi_setup_msi_irqs() is supposed to call msi_domain_alloc_irqs() with the hbus->irq_domain, which is created in hv_pcie_init_irq_domain() and is associated with the Hyper-V chip hv_msi_irq_chip. Consequently, the irq line is not properly set up, and the device driver can not receive any interrupt. Fixes: d59f6617eef0 ("genirq: Allow fwnode to carry name information only") Fixes: 467a3bb97432 ("PCI: hv: Allocate a named fwnode instead of an address-based one") Reported-by: Lili Deng <v-lide@microsoft.com> Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/PU1P153MB01694D9AF625AC335C600C5FBFBE0@PU1P153MB0169.APCP153.PROD.OUTLOOK.COM
2019-09-03x86/mm: Remove the unused set_memory_wt() functionChristoph Hellwig
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190826075558.8125-5-hch@lst.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03x86/mm: Remove set_pages_x() and set_pages_nx()Christoph Hellwig
These wrappers don't provide a real benefit over just using set_memory_x() and set_memory_nx(). Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190826075558.8125-4-hch@lst.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03x86/mm: Remove the unused set_memory_array_*() functionsChristoph Hellwig
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190826075558.8125-3-hch@lst.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03x86/mm: Unexport set_memory_x() and set_memory_nx()Christoph Hellwig
No module currently messed with clearing or setting the execute permission of kernel memory, and none really should. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20190826075558.8125-2-hch@lst.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03Merge tag 'v5.3-rc7' into x86/mm, to pick up fixesIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03perf/x86: Make more stuff staticValdis Klētnieks
When building with C=2, sparse makes note of a number of things: arch/x86/events/intel/rapl.c:637:30: warning: symbol 'rapl_attr_update' was not declared. Should it be static? arch/x86/events/intel/cstate.c:449:30: warning: symbol 'core_attr_update' was not declared. Should it be static? arch/x86/events/intel/cstate.c:457:30: warning: symbol 'pkg_attr_update' was not declared. Should it be static? arch/x86/events/msr.c:170:30: warning: symbol 'attr_update' was not declared. Should it be static? arch/x86/events/intel/lbr.c:276:1: warning: symbol 'lbr_from_quirk_key' was not declared. Should it be static? And they can all indeed be static. Signed-off-by: Valdis Kletnieks <valdis.kletnieks@vt.edu> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/128059.1565286242@turing-police Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/uclamp: Always use 'enum uclamp_id' for clamp_id valuesPatrick Bellasi
The supported clamp indexes are defined in 'enum clamp_id', however, because of the code logic in some of the first utilization clamping series version, sometimes we needed to use 'unsigned int' to represent indices. This is not more required since the final version of the uclamp_* APIs can always use the proper enum uclamp_id type. Fix it with a bulk rename now that we have all the bits merged. Signed-off-by: Patrick Bellasi <patrick.bellasi@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Michal Koutny <mkoutny@suse.com> Acked-by: Tejun Heo <tj@kernel.org> Cc: Alessio Balsini <balsini@android.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Joel Fernandes <joelaf@google.com> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Perret <quentin.perret@arm.com> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Steve Muckle <smuckle@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Todd Kjos <tkjos@google.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lkml.kernel.org/r/20190822132811.31294-7-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/uclamp: Update CPU's refcount on TG's clamp changesPatrick Bellasi
On updates of task group (TG) clamp values, ensure that these new values are enforced on all RUNNABLE tasks of the task group, i.e. all RUNNABLE tasks are immediately boosted and/or capped as requested. Do that each time we update effective clamps from cpu_util_update_eff(). Use the *cgroup_subsys_state (css) to walk the list of tasks in each affected TG and update their RUNNABLE tasks. Update each task by using the same mechanism used for cpu affinity masks updates, i.e. by taking the rq lock. Signed-off-by: Patrick Bellasi <patrick.bellasi@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Michal Koutny <mkoutny@suse.com> Acked-by: Tejun Heo <tj@kernel.org> Cc: Alessio Balsini <balsini@android.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Joel Fernandes <joelaf@google.com> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Perret <quentin.perret@arm.com> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Steve Muckle <smuckle@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Todd Kjos <tkjos@google.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lkml.kernel.org/r/20190822132811.31294-6-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/uclamp: Use TG's clamps to restrict TASK's clampsPatrick Bellasi
When a task specific clamp value is configured via sched_setattr(2), this value is accounted in the corresponding clamp bucket every time the task is {en,de}qeued. However, when cgroups are also in use, the task specific clamp values could be restricted by the task_group (TG) clamp values. Update uclamp_cpu_inc() to aggregate task and TG clamp values. Every time a task is enqueued, it's accounted in the clamp bucket tracking the smaller clamp between the task specific value and its TG effective value. This allows to: 1. ensure cgroup clamps are always used to restrict task specific requests, i.e. boosted not more than its TG effective protection and capped at least as its TG effective limit. 2. implement a "nice-like" policy, where tasks are still allowed to request less than what enforced by their TG effective limits and protections Do this by exploiting the concept of "effective" clamp, which is already used by a TG to track parent enforced restrictions. Apply task group clamp restrictions only to tasks belonging to a child group. While, for tasks in the root group or in an autogroup, system defaults are still enforced. Signed-off-by: Patrick Bellasi <patrick.bellasi@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Michal Koutny <mkoutny@suse.com> Acked-by: Tejun Heo <tj@kernel.org> Cc: Alessio Balsini <balsini@android.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Joel Fernandes <joelaf@google.com> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Perret <quentin.perret@arm.com> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Steve Muckle <smuckle@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Todd Kjos <tkjos@google.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lkml.kernel.org/r/20190822132811.31294-5-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/uclamp: Propagate system defaults to the root groupPatrick Bellasi
The clamp values are not tunable at the level of the root task group. That's for two main reasons: - the root group represents "system resources" which are always entirely available from the cgroup standpoint. - when tuning/restricting "system resources" makes sense, tuning must be done using a system wide API which should also be available when control groups are not. When a system wide restriction is available, cgroups should be aware of its value in order to know exactly how much "system resources" are available for the subgroups. Utilization clamping supports already the concepts of: - system defaults: which define the maximum possible clamp values usable by tasks. - effective clamps: which allows a parent cgroup to constraint (maybe temporarily) its descendants without losing the information related to the values "requested" from them. Exploit these two concepts and bind them together in such a way that, whenever system default are tuned, the new values are propagated to (possibly) restrict or relax the "effective" value of nested cgroups. When cgroups are in use, force an update of all the RUNNABLE tasks. Otherwise, keep things simple and do just a lazy update next time each task will be enqueued. Do that since we assume a more strict resource control is required when cgroups are in use. This allows also to keep "effective" clamp values updated in case we need to expose them to user-space. Signed-off-by: Patrick Bellasi <patrick.bellasi@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Michal Koutny <mkoutny@suse.com> Acked-by: Tejun Heo <tj@kernel.org> Cc: Alessio Balsini <balsini@android.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Joel Fernandes <joelaf@google.com> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Perret <quentin.perret@arm.com> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Steve Muckle <smuckle@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Todd Kjos <tkjos@google.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lkml.kernel.org/r/20190822132811.31294-4-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/uclamp: Propagate parent clampsPatrick Bellasi
In order to properly support hierarchical resources control, the cgroup delegation model requires that attribute writes from a child group never fail but still are locally consistent and constrained based on parent's assigned resources. This requires to properly propagate and aggregate parent attributes down to its descendants. Implement this mechanism by adding a new "effective" clamp value for each task group. The effective clamp value is defined as the smaller value between the clamp value of a group and the effective clamp value of its parent. This is the actual clamp value enforced on tasks in a task group. Since it's possible for a cpu.uclamp.min value to be bigger than the cpu.uclamp.max value, ensure local consistency by restricting each "protection" (i.e. min utilization) with the corresponding "limit" (i.e. max utilization). Do that at effective clamps propagation to ensure all user-space write never fails while still always tracking the most restrictive values. Signed-off-by: Patrick Bellasi <patrick.bellasi@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Michal Koutny <mkoutny@suse.com> Acked-by: Tejun Heo <tj@kernel.org> Cc: Alessio Balsini <balsini@android.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Joel Fernandes <joelaf@google.com> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Perret <quentin.perret@arm.com> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Steve Muckle <smuckle@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Todd Kjos <tkjos@google.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lkml.kernel.org/r/20190822132811.31294-3-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/uclamp: Extend CPU's cgroup controllerPatrick Bellasi
The cgroup CPU bandwidth controller allows to assign a specified (maximum) bandwidth to the tasks of a group. However this bandwidth is defined and enforced only on a temporal base, without considering the actual frequency a CPU is running on. Thus, the amount of computation completed by a task within an allocated bandwidth can be very different depending on the actual frequency the CPU is running that task. The amount of computation can be affected also by the specific CPU a task is running on, especially when running on asymmetric capacity systems like Arm's big.LITTLE. With the availability of schedutil, the scheduler is now able to drive frequency selections based on actual task utilization. Moreover, the utilization clamping support provides a mechanism to bias the frequency selection operated by schedutil depending on constraints assigned to the tasks currently RUNNABLE on a CPU. Giving the mechanisms described above, it is now possible to extend the cpu controller to specify the minimum (or maximum) utilization which should be considered for tasks RUNNABLE on a cpu. This makes it possible to better defined the actual computational power assigned to task groups, thus improving the cgroup CPU bandwidth controller which is currently based just on time constraints. Extend the CPU controller with a couple of new attributes uclamp.{min,max} which allow to enforce utilization boosting and capping for all the tasks in a group. Specifically: - uclamp.min: defines the minimum utilization which should be considered i.e. the RUNNABLE tasks of this group will run at least at a minimum frequency which corresponds to the uclamp.min utilization - uclamp.max: defines the maximum utilization which should be considered i.e. the RUNNABLE tasks of this group will run up to a maximum frequency which corresponds to the uclamp.max utilization These attributes: a) are available only for non-root nodes, both on default and legacy hierarchies, while system wide clamps are defined by a generic interface which does not depends on cgroups. This system wide interface enforces constraints on tasks in the root node. b) enforce effective constraints at each level of the hierarchy which are a restriction of the group requests considering its parent's effective constraints. Root group effective constraints are defined by the system wide interface. This mechanism allows each (non-root) level of the hierarchy to: - request whatever clamp values it would like to get - effectively get only up to the maximum amount allowed by its parent c) have higher priority than task-specific clamps, defined via sched_setattr(), thus allowing to control and restrict task requests. Add two new attributes to the cpu controller to collect "requested" clamp values. Allow that at each non-root level of the hierarchy. Keep it simple by not caring now about "effective" values computation and propagation along the hierarchy. Update sysctl_sched_uclamp_handler() to use the newly introduced uclamp_mutex so that we serialize system default updates with cgroup relate updates. Signed-off-by: Patrick Bellasi <patrick.bellasi@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Michal Koutny <mkoutny@suse.com> Acked-by: Tejun Heo <tj@kernel.org> Cc: Alessio Balsini <balsini@android.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Joel Fernandes <joelaf@google.com> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: Paul Turner <pjt@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Perret <quentin.perret@arm.com> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Steve Muckle <smuckle@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Todd Kjos <tkjos@google.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lkml.kernel.org/r/20190822132811.31294-2-patrick.bellasi@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/topology: Improve load balancing on AMD EPYC systemsMatt Fleming
SD_BALANCE_{FORK,EXEC} and SD_WAKE_AFFINE are stripped in sd_init() for any sched domains with a NUMA distance greater than 2 hops (RECLAIM_DISTANCE). The idea being that it's expensive to balance across domains that far apart. However, as is rather unfortunately explained in: commit 32e45ff43eaf ("mm: increase RECLAIM_DISTANCE to 30") the value for RECLAIM_DISTANCE is based on node distance tables from 2011-era hardware. Current AMD EPYC machines have the following NUMA node distances: node distances: node 0 1 2 3 4 5 6 7 0: 10 16 16 16 32 32 32 32 1: 16 10 16 16 32 32 32 32 2: 16 16 10 16 32 32 32 32 3: 16 16 16 10 32 32 32 32 4: 32 32 32 32 10 16 16 16 5: 32 32 32 32 16 10 16 16 6: 32 32 32 32 16 16 10 16 7: 32 32 32 32 16 16 16 10 where 2 hops is 32. The result is that the scheduler fails to load balance properly across NUMA nodes on different sockets -- 2 hops apart. For example, pinning 16 busy threads to NUMA nodes 0 (CPUs 0-7) and 4 (CPUs 32-39) like so, $ numactl -C 0-7,32-39 ./spinner 16 causes all threads to fork and remain on node 0 until the active balancer kicks in after a few seconds and forcibly moves some threads to node 4. Override node_reclaim_distance for AMD Zen. Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Mel Gorman <mgorman@techsingularity.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Cc: Suravee.Suthikulpanit@amd.com Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Thomas.Lendacky@amd.com Cc: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20190808195301.13222-3-matt@codeblueprint.co.uk Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03arch, ia64: Make NUMA select SMPMatt Fleming
While it does make sense to allow CONFIG_NUMA and !CONFIG_SMP in theory, it doesn't make much sense in practice. Follow other architectures and make CONFIG_NUMA select CONFIG_SMP. The motivation for this patch is to allow a new NUMA variable to be initialised in kernel/sched/topology.c. Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mel Gorman <mgorman@techsingularity.net> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@surriel.com> Cc: Suravee.Suthikulpanit@amd.com Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Thomas.Lendacky@amd.com Cc: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20190808195301.13222-2-matt@codeblueprint.co.uk Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched, perf: MAINTAINERS update, add submaintainers and reviewersPeter Zijlstra
The below entries are a little unorthodox; I've not found other entries in MAINTAINER that subdivide responsibilities like this, and certainly the lovely get_maintainers.pl script will not get it, but I'm thinking to a human it should be plenty clear and we're all very good at ignoring email anyway. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Juri Lelli <juri.lelli@redhat.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Acked-by: Vincent Guittot <vincent.guittot@linaro.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Ben Segall <bsegall@google.com> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mel Gorman <mgorman@suse.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03Merge branch 'linux-5.3' of git://github.com/skeggsb/linux into drm-fixesDave Airlie
Single nouveau firmware fix. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv5uGLgDY8V8pWgEH0-YhkCEgvHE=NZ1W_m0gJaoFPuQ0g@mail.gmail.com
2019-09-03x86/math64: Provide a sane mul_u64_u32_div() implementation for x86_64Peter Zijlstra
On x86_64 we can do a u64 * u64 -> u128 widening multiply followed by a u128 / u64 -> u64 division to implement a sane version of mul_u64_u32_div(). Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03sched/fair: Don't assign runtime for throttled cfs_rqLiangyan
do_sched_cfs_period_timer() will refill cfs_b runtime and call distribute_cfs_runtime to unthrottle cfs_rq, sometimes cfs_b->runtime will allocate all quota to one cfs_rq incorrectly, then other cfs_rqs attached to this cfs_b can't get runtime and will be throttled. We find that one throttled cfs_rq has non-negative cfs_rq->runtime_remaining and cause an unexpetced cast from s64 to u64 in snippet: distribute_cfs_runtime() { runtime = -cfs_rq->runtime_remaining + 1; } The runtime here will change to a large number and consume all cfs_b->runtime in this cfs_b period. According to Ben Segall, the throttled cfs_rq can have account_cfs_rq_runtime called on it because it is throttled before idle_balance, and the idle_balance calls update_rq_clock to add time that is accounted to the task. This commit prevents cfs_rq to be assgined new runtime if it has been throttled until that distribute_cfs_runtime is called. Signed-off-by: Liangyan <liangyan.peng@linux.alibaba.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Reviewed-by: Ben Segall <bsegall@google.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: shanpeic@linux.alibaba.com Cc: stable@vger.kernel.org Cc: xlpang@linux.alibaba.com Fixes: d3d9dc330236 ("sched: Throttle entities exceeding their allowed bandwidth") Link: https://lkml.kernel.org/r/20190826121633.6538-1-liangyan.peng@linux.alibaba.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-09-03ALSA: hda/realtek - Enable internal speaker & headset mic of ASUS UX431FLJian-Hong Pan
Original pin node values of ASUS UX431FL with ALC294: 0x12 0xb7a60140 0x13 0x40000000 0x14 0x90170110 0x15 0x411111f0 0x16 0x411111f0 0x17 0x90170111 0x18 0x411111f0 0x19 0x411111f0 0x1a 0x411111f0 0x1b 0x411111f0 0x1d 0x4066852d 0x1e 0x411111f0 0x1f 0x411111f0 0x21 0x04211020 1. Has duplicated internal speakers (0x14 & 0x17) which makes the output route become confused. So, the output volume cannot be changed by setting. 2. Misses the headset mic pin node. This patch disables the confusing speaker (NID 0x14) and enables the headset mic (NID 0x19). Link: https://lore.kernel.org/r/20190902100054.6941-1-jian-hong@endlessm.com Signed-off-by: Jian-Hong Pan <jian-hong@endlessm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-09-02netfilter: nft_socket: fix erroneous socket assignmentFernando Fernandez Mancera
The socket assignment is wrong, see skb_orphan(): When skb->destructor callback is not set, but skb->sk is set, this hits BUG(). Link: https://bugzilla.redhat.com/show_bug.cgi?id=1651813 Fixes: 554ced0a6e29 ("netfilter: nf_tables: add support for native socket matching") Signed-off-by: Fernando Fernandez Mancera <ffmancera@riseup.net> Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
2019-09-02netfilter: bridge: Drops IPv6 packets if IPv6 module is not loadedLeonardo Bras
A kernel panic can happen if a host has disabled IPv6 on boot and have to process guest packets (coming from a bridge) using it's ip6tables. IPv6 packets need to be dropped if the IPv6 module is not loaded, and the host ip6tables will be used. Signed-off-by: Leonardo Bras <leonardo@linux.ibm.com> Acked-by: Florian Westphal <fw@strlen.de> Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
2019-09-02configfs: new object reprsenting tree fragmentsAl Viro
Refcounted, hangs of configfs_dirent, created by operations that add fragments to configfs tree (mkdir and configfs_register_{subsystem,group}). Will be used in the next commit to provide exclusion between fragment removal and ->show/->store calls. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-09-02configfs_register_group() shouldn't be (and isn't) called in rmdirable partsAl Viro
revert cc57c07343bd "configfs: fix registered group removal" It was an attempt to handle something that fundamentally doesn't work - configfs_register_group() should never be done in a part of tree that can be rmdir'ed. And in mainline it never had been, so let's not borrow trouble; the fix was racy anyway, it would take a lot more to make that work and desired semantics is not clear. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-09-02configfs: stash the data we need into configfs_buffer at open timeAl Viro
simplifies the ->read()/->write()/->release() instances nicely Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-09-02net: stmmac: dwmac-sun8i: Variable "val" in function ↵Yizhuo
sun8i_dwmac_set_syscon() could be uninitialized In function sun8i_dwmac_set_syscon(), local variable "val" could be uninitialized if function regmap_field_read() returns -EINVAL. However, it will be used directly in the if statement, which is potentially unsafe. Signed-off-by: Yizhuo <yzhai003@ucr.edu> Signed-off-by: David S. Miller <davem@davemloft.net>