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2013-07-01drm/nouveau/bsp/nv84: initial vp2 engine implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vp/nv84: initial vp2 engine implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: xtensa engine base class implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vdec: fork vp3 implementations from vp2Ilia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: move falcon class to engine/Ben Skeggs
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/kms: don't fail if there's no dcb table entriesBen Skeggs
Fixes module not loading on Tesla K20. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau: remove limit on gartMaarten Lankhorst
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by: Maarten >Lnkhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: perform a bar flush when flushing vmMaarten Lankhorst
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc8/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc4/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc1/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc3/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvd9/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve4/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0-/gr: bump maximum gpc/tpc limitsBen Skeggs
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvf0/gr: initial register/context setupBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve7/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve6/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau: delay busy bo vma removal until fence signalsBen Skeggs
As opposed to an explicit wait. Allows userspace to not stall waiting on buffer deletion. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: make each vma take a reference on its parent vmBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: remove nouveau_mm.mutex, no more usersBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: take subdev mutex, not the mm, protects against race with ↵Ben Skeggs
vm/nvc0 nvc0_vm_flush() accesses the pgd list, which will soon be able to race with vm_unlink() during channel destruction. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/vm: handle bar tlb flushes internallyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50-/vm: take mutex rather than irqsave spinlockBen Skeggs
These operations can take quite some time, and we really don't want to have to hold a spinlock for too long. Now that the lock ordering for vm and the gr/nv84 hw bug workaround has been reversed, it's possible to use a mutex here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50/vm: remove explicit vm knowledge from enginesBen Skeggs
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50/vm: handle bar tlb flushes internallyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: port mp trap handling from calim's kepler codeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/gr: attempt to resume after sm trapsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/gr: s/tp/tpc/Ben Skeggs
NVIDIA's name... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/fifo: create our playlists up-front, at startupBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nva3/clk: minor improvements to fractional N calculationBen Skeggs
Helps us to get identical numbers to the binary driver for (at least) Kepler memory PLLs, and fixes a rounding error. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/fb: initialise vram controller as pfb sub-objectBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/clk: change init ordering, no longer needed by devinitBen Skeggs
And, will depend on FB/VOLT/DAEMON being ready when it gets initialised so that it can set/restore clocks. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/devinit: move simple pll setting routines to devinitBen Skeggs
These are pretty much useless for reclocking purposes. Lets make it clearer what they're for and move them to DEVINIT to signify they're for the very simple PLL setting requirements of running the init tables. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau: pass generic subdev to calculation routinesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/ce: stub interrupt handlerBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/ce: link ce2 to its engine, rather than from graphicsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/fifo: copy engine context stored in ramfc, not externallyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/ce: create engine object for ce2Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau: pull in latest ucode builds from external treeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-30Input: add OLPC AP-SP driverDaniel Drake
The OLPC XO-1.75 and XO-4 laptops include a PS/2 touchpad and an AT keyboard, yet they do not have a hardware PS/2 controller. Instead, a firmware runs on a dedicated core ("Security Processor", part of the SoC) that acts as a PS/2 controller through bit-banging. Communication between the main cpu (Application Processor) and the Security Processor happens via a standard command mechanism implemented by the SoC. Add a driver for this interface to enable keyboard/mouse input on this platform. Original author: Saadia Baloch Signed-off-by: Daniel Drake <dsd@laptop.org> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2013-07-01powerpc/pseries: Inform the hypervisor we are using EBB regsMichael Ellerman
On LPAR systems we need to inform the hypervisor that we are using the EBB registers. We do this by setting a bit in the Virtual Processor Area (VPA) - formerly known as the lppaca. For now we do this always, ie. we do not dynamically enable/disable. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Add power8 EBB supportMichael Ellerman
Add logic to the power8 PMU code to support EBB. Future processors would also be expected to implement similar constraints. At that time we could possibly factor these out into common code. Finally mark the power8 PMU as supporting EBB, which is the actual enable switch which allows EBBs to be configured. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Core EBB support for 64-bit book3sMichael Ellerman
Add support for EBB (Event Based Branches) on 64-bit book3s. See the included documentation for more details. EBBs are a feature which allows the hardware to branch directly to a specified user space address when a PMU event overflows. This can be used by programs for self-monitoring with no kernel involvement in the inner loop. Most of the logic is in the generic book3s code, primarily to avoid a proliferation of PMU callbacks. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Drop MMCRA from thread_structMichael Ellerman
In commit 59affcd "Context switch more PMU related SPRs" I added more PMU SPRs to thread_struct, later modified in commit b11ae95. To add insult to injury it turns out we don't need to switch MMCRA as it's only user readable, and the value is recomputed by the PMU code. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Don't enable if we have zero eventsMichael Ellerman
In power_pmu_enable() we still enable the PMU even if we have zero events. This should have no effect but doesn't make much sense. Instead just return after telling the hypervisor that we are not using the PMCs. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> CC: <stable@vger.kernel.org> [v3.10] Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Use existing out label in power_pmu_enable()Michael Ellerman
In power_pmu_enable() we can use the existing out label to reduce the number of return paths. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> CC: <stable@vger.kernel.org> [v3.10] Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Freeze PMC5/6 if we're not using themMichael Ellerman
On Power8 we can freeze PMC5 and 6 if we're not using them. Normally they run all the time. As noticed by Anshuman, we should unfreeze them when we disable the PMU as there are legacy tools which expect them to run all the time. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> CC: <stable@vger.kernel.org> [v3.10] Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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