summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-01-29clk: imx6sll: add proper spdx license identifierMarcel Ziswiler
This fixes the following error: include/dt-bindings/clock/imx6sll-clock.h:1: warning: Improper SPDX comment style for 'include/dt-bindings/clock/imx6sll-clock.h', please use '/*' instead include/dt-bindings/clock/imx6sll-clock.h:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230119085421.102804-2-marcel@ziswiler.com
2023-01-29clk: imx: imx93: invoke imx_register_uart_clocksPeng Fan
Invoke imx_register_uart_clocks to keep uart clk on when earlycon specified. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-5-peng.fan@oss.nxp.com
2023-01-29clk: imx: remove clk_count of imx_register_uart_clocksPeng Fan
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
2023-01-29clk: imx: get stdout clk count from device treePeng Fan
Currently the clk_count is specified by API users, but this parameter is wrongly used, for example, i.MX8M clk driver use 4, however the uart device tree node only use 2 clock entries. So let using of_clk_get_parent_count to get the exact clock count. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-3-peng.fan@oss.nxp.com
2023-01-29clk: imx: avoid memory leakPeng Fan
In case imx_register_uart_clocks return early, the imx_uart_clocks memory will be no freed. So execute kfree always to avoid memory leak. Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-2-peng.fan@oss.nxp.com
2023-01-27Merge tag 'renesas-clk-for-v6.3-tag2' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add support for USB host/device configuration on RZ/N1 - Add PLL2 programming support, and CAN-FD clocks on R-Car V4H - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779g0: Add CAN-FD clocks clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779g0: Add custom clock for PLL2 clk: renesas: cpg-mssr: Remove superfluous check in resume code clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence
2023-01-26clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven
Add the CANFD core clock and the CANFD0 module clock, which are used by the CAN-FD Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a78f534bd80f170f3f1267f3270fdb3b7a73b5d4.1674498643.git.geert+renesas@glider.be
2023-01-26clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto
"sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87v8l3z3y8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-26clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto
"sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87tu0nz3xr.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-25dt-bindings: clock: qcom,sm8450-camcc: constrain required-oppsKrzysztof Kozlowski
Be specific how many required-opps are allowed. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230119130028.106817-1-krzysztof.kozlowski@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-25Merge tag 'clk-microchip-6.3' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk updates from Claudiu Beznea: Only updates for AT91 SoCs this time as follows: - DDR clocks were marked as critical in the proper clock driver for each AT91 SoC such that drivers/memory/atmel-sdramc.c to be deleted in the next releases as it only does clock enablement; - Patch to avoid compiling dt-compat.o for all AT91 SoCs as only some of them may use it. * tag 'clk-microchip-6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60 clk: at91: mark ddr clocks as critical
2023-01-25Merge tag 'clk-meson-v6.3-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd
clk-amlogic Pull Amlogic clk updates from Jerome Brunet: - Use .determine_rate() instead of .round_rate() for the dualdiv, mpll, sclk-div and cpu-dyn-div amlogic clock drivers * tag 'clk-meson-v6.3-1' of https://github.com/BayLibre/clk-meson: clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk: meson: sclk-div: switch from .round_rate to .determine_rate clk: meson: dualdiv: switch from .round_rate to .determine_rate clk: meson: mpll: Switch from .round_rate to .determine_rate
2023-01-24clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven
Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core clock) to request PLL rate changes, and enable boost mode for the High Performance mode. For now this is limited to integer multiplication modes. Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H. On R-Car S4-8, the integer and fractional multiplication fields are one bit larger resp. smaller, but R-Car S4-8 does not support High Performance mode. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be
2023-01-23clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven
When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ/A Soc, as the code checked for that before. Fixes: ace342097768e35f ("clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/144a3e66d748c0c17f3524ac8fa6ece5bf5b6f1e.1673425314.git.geert+renesas@glider.be
2023-01-23clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina
The CFG_USB[H2MODE] allows to switch the USB configuration. The configuration supported are: - One host and one device or - Two hosts Set CFG_USB[H2MODE] based on the USBF controller (USB device) availability. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230105152257.310642-3-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-18dt-bindings: clock: versaclock5: Document 5P49V60 compatible stringLars-Peter Clausen
The 5P49V60 clock generator is part of the same family of devices that is described by the versaclock5 binding documentation. Add the compatible string of the 5P49V60 to the binding documentation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230114233500.3294789-3-lars@metafoo.de Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-18clk: vc5: Add support for 5P49V60Lars-Peter Clausen
The 5P49V60 is very similar to the existing supported clock chips of the versaclock5 driver and uses the same register map layout. But its maximum VCO frequency is 2.7 GHz instead of 3 GHz for the other supported devices. Add a vco_max field to the chip info field to allow to specify a per device variant maximum VCO frequency. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230114233500.3294789-2-lars@metafoo.de Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-18clk: vc5: Use `clamp()` to restrict PLL rangeLars-Peter Clausen
The VCO frequency needs to be within a certain range and the driver enforces this. Make use of the clamp macro to implement this instead of open-coding it. This makes the code a bit shorter and also semanticly stronger. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230114233500.3294789-1-lars@metafoo.de Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-18Merge tag 'renesas-clk-for-v6.3-tag1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and resets on RZ/V2M - Add display clocks on R-Car V4H - Add Camera Receiving Unit (CRU) clocks and resets on RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed clk: renesas: r9a07g044: Add clock and reset entries for CRU clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries clk: renesas: r9a09g011: Add USB clock and reset entries clk: renesas: r9a09g011: Add TIM clock and reset entries clk: renesas: r8a779g0: Add display related clocks clk: renesas: rcar-gen4: Restore PLL enum sort order clk: renesas: r8a779g0: Fix OSC predividers clk: renesas: r9a09g011: Add PWM clock and reset entries
2023-01-13clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-5-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch sclk-div over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-4-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-dualdiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-3-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-mpll over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-2-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-12dt-bindings: clock: imx8m-clock: correct i.MX8MQ node namePeng Fan
i.MX8MQ CCM is at address 0x30380000, so correct it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20221223030540.62018-1-peng.fan@oss.nxp.com Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-12clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov
If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_priv keeps dangling pointer that potentially can be used later. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support") Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1671806417-32623-1-git-send-email-khoroshilov@ispras.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-12clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar
Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for both RZ/G2L and RZ/V2L SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-11drivers/clk: Remove "select SRCU"Paul E. McKenney
Now that the SRCU Kconfig option is unconditionally selected, there is no longer any point in selecting it. Therefore, remove the "select SRCU" Kconfig statements. Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: <linux-clk@vger.kernel.org> Link: https://lore.kernel.org/r/20230105003813.1770367-9-paulmck@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-09clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60Claudiu Beznea
There is no need to have dt-compat.c compiled for SAMA7G5 and SAM9X60 as there is no in kernel device tree that could use it. Thus avoid compiling dt-compat.c for them. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208114515.35179-4-claudiu.beznea@microchip.com
2023-01-09clk: at91: mark ddr clocks as criticalClaudiu Beznea
Mark DDR clocks as critical for AT91 devices. These clocks are enabled by bootloader when initializing DDR and needs to stay enabled. Up to this patch the DDR clocks were requested from drivers/memory/atmel-sdramc.c which does only clock request and enable. There is no need to have a separate driver just for this, thus the atmel-sdramc.c will be deleted in a subsequent patch. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208114515.35179-2-claudiu.beznea@microchip.com
2023-01-08clk: sunxi-ng: d1: Add CAN bus gates and resetsFabien Poussin
The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221231231429.18357-7-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08dt-bindings: clock: Add D1 CAN bus gates and resetsSamuel Holland
The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221231231429.18357-6-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: d1: Mark cpux clock as criticalAndrás Szemző
Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU. In that case, the CPUs are driven from the 'cpux' clock, so it needs to be marked as critical, since there is no consumer when DVFS is disabled. This matches the drivers for other SoCs, and the "riscv" clock in this driver. Signed-off-by: András Szemző <szemzo.andras@gmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-5-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: d1: Allow building for R528/T113Samuel Holland
Allwinner released some 32-bit ARM (sun8i) SoCs which use the same CCU as D1. Allow them to reuse the driver. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-4-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: Move SoC driver conditions to dependenciesSamuel Holland
Do not duplicate the same expression on the `default` line, so the two lines do not need to be kept in sync. Drivers stay disabled under COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU. Three drivers had no conditions. - SUN6I_RTC_CCU and SUN8I_DE2_CCU are used on current hardware regardless of CPU architecture. - SUN8I_R_CCU is only used on pre-H6 SoCs, which means no RISCV SoCs. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-3-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependenciesSamuel Holland
SUNXI_CCU already depends on ARCH_SUNXI, so adding the dependency to individual SoC drivers is redundant. Drivers stay disabled under COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-2-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: Avoid computing the rate twiceSamuel Holland
The ccu_*_find_best() functions already compute a best_rate at the same time as the other factors. Return this value so the caller does not need to duplicate the computation. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20221231173055.42384-1-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clockSamuel Holland
The DRAM controller clock is only allowed to change frequency while the DRAM chips are in self-refresh. To support this, changes to the CLK_DRAM mux and divider have no effect until acknowledged by the memory dynamic frequency scaling (MDFS) hardware inside the DRAM controller. (There is a SDRCLK_UPD bit in DRAM_CFG_REG which should serve a similar purpose, but this bit actually does nothing.) However, the MDFS hardware in H3 appears to be broken. Triggering a frequency change using the procedure from similar SoCs (A64/H5) hangs the hardware. Additionally, the vendor BSP specifically avoids using the MDFS hardware on H3, instead performing all DRAM PHY parameter updates and resets in software. Thus, it is effectively impossible to change the CLK_DRAM mux/divider, so those features should not be modeled. Add CLK_SET_RATE_PARENT so frequency changes apply to PLL_DDR instead. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221229042230.24532-1-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issuesRandy Dunlap
Use '-' to separate the function name and its description. Use '%' on constants in kernel-doc notation. Use the kernel-doc Return: format for function return values. Fixes this warning: ccu_mmc_timing.c:21: warning: No description found for return value of 'sunxi_ccu_set_mmc_timing_mode' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Yang Li <yang.lee@linux.alibaba.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221122184844.6794-1-rdunlap@infradead.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-12-27clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy
Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-27clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das
Add USB clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221212172804.1277751-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-27clk: renesas: r9a09g011: Add TIM clock and reset entriesBiju Das
Add Compare-Match Timer (TIM) clock and reset entries to CPG driver. The TIM IP on the RZ/V2M comes with 32 channels, but the ISP has full control of channels 0 to 7, and channels 24 to 31. Therefore Linux is only allowed to use channels 8 to 23. The TIM has shared peripheral clock with other modules, so mark it as critical clock. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221205145955.391526-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-26clk: renesas: r8a779g0: Add display related clocksTomi Valkeinen
Add clocks related to display which are needed to get the DSI output working. Extracted from Renesas BSP tree. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221201095631.89448-4-tomi.valkeinen+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-26clk: renesas: rcar-gen4: Restore PLL enum sort orderGeert Uytterhoeven
When CLK_TYPE_GEN4_PLL4 was added to the rcar_gen4_clk_types enum, it was inserted at a random location. Restore sort order of the clock types referring to PLLs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/dbd61ed19f79e9ae751fbb533d6c946e810e4359.1669740824.git.geert+renesas@glider.be
2022-12-26clk: renesas: r8a779g0: Fix OSC predividersGeert Uytterhoeven
According to the table in Note 5 for the OSC clock in Table 8.1.4e ("Lists of CPG clocks generated from PLL5") of the R-Car V4H Series Hardware User's Manual Rev. 0.54, the predividers for the OSC clock are 16 resp. 32 when using a 16.66 resp. 33.33 MHz external crystal. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/dcd572acc584c237f70d2309e038f25040236a87.1669740722.git.geert+renesas@glider.be
2022-12-26clk: renesas: r9a09g011: Add PWM clock and reset entriesBiju Das
Add PWM{8..14} clock and reset entries to CPG driver. The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has full control of channels 0 to 7, and channel 15, therefore Linux is only allowed to use channels 8 to 14. The PWM channel 15 shares apb clock and reset with PWM{8..14}. The reset is deasserted by the bootloader/ISP. Add PWM{8..14} clocks to CPG driver and mark apb clock as critical clock, so that the apb clock will be always on. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221124191643.3193423-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-12-25Linux 6.2-rc1v6.2-rc1Linus Torvalds
2022-12-25treewide: Convert del_timer*() to timer_shutdown*()Steven Rostedt (Google)
Due to several bugs caused by timers being re-armed after they are shutdown and just before they are freed, a new state of timers was added called "shutdown". After a timer is set to this state, then it can no longer be re-armed. The following script was run to find all the trivial locations where del_timer() or del_timer_sync() is called in the same function that the object holding the timer is freed. It also ignores any locations where the timer->function is modified between the del_timer*() and the free(), as that is not considered a "trivial" case. This was created by using a coccinelle script and the following commands: $ cat timer.cocci @@ expression ptr, slab; identifier timer, rfield; @@ ( - del_timer(&ptr->timer); + timer_shutdown(&ptr->timer); | - del_timer_sync(&ptr->timer); + timer_shutdown_sync(&ptr->timer); ) ... when strict when != ptr->timer ( kfree_rcu(ptr, rfield); | kmem_cache_free(slab, ptr); | kfree(ptr); ) $ spatch timer.cocci . > /tmp/t.patch $ patch -p1 < /tmp/t.patch Link: https://lore.kernel.org/lkml/20221123201306.823305113@linutronix.de/ Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org> Acked-by: Pavel Machek <pavel@ucw.cz> [ LED ] Acked-by: Kalle Valo <kvalo@kernel.org> [ wireless ] Acked-by: Paolo Abeni <pabeni@redhat.com> [ networking ] Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2022-12-23Merge tag 'spi-fix-v6.2-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fix from Mark Brown: "One driver specific change here which handles the case where a SPI device for some reason tries to change the bus speed during a message on fsl_spi hardware, this should be very unusual" * tag 'spi-fix-v6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: fsl_spi: Don't change speed while chipselect is active
2022-12-23Merge tag 'regulator-fix-v6.2-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator Pull regulator fixes from Mark Brown: "Two core fixes here, one for a long standing race which some Qualcomm systems have started triggering with their UFS driver and another fixing a problem with supply lookup introduced by the fixes for devm related use after free issues that were introduced in this merge window" * tag 'regulator-fix-v6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: regulator: core: fix deadlock on regulator enable regulator: core: Fix resolve supply lookup issue
2022-12-23Merge tag 'coccinelle-6.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jlawall/linux Pull coccicheck update from Julia Lawall: "Modernize use of grep in coccicheck: Use 'grep -E' instead of 'egrep'" * tag 'coccinelle-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/jlawall/linux: scripts: coccicheck: use "grep -E" instead of "egrep"