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2016-05-09KVM: s390: enable SRS only if enabled for the guestDavid Hildenbrand
If we don't have SIGP SENSE RUNNING STATUS enabled for the guest, let's not enable interpretation so we can correctly report an invalid order. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2016-05-09KVM: s390: enable PFMFI only if guest has EDAT1David Hildenbrand
Only enable PFMF interpretation if the necessary facility (EDAT1) is available, otherwise the pfmf handler in priv.c will inject an exception Reviewed-by: Dominik Dingel <dingel@linux.vnet.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2016-05-09Merge 4.6-rc7 into staging-nextGreg Kroah-Hartman
This fixes some merge issues with some iio drivers that were found in linux-next. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09MAINTAINERS: 8250: remove website referenceBaruch Siach
This website is obsolete, as it has not been updated in more than a decade. Cc: "Theodore Ts'o" <tytso@mit.edu> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09usb: Remove unnecessary space before operator ','.Sandhya Bankar
Remove unnecessary space before operator ','. Signed-off-by: Sandhya Bankar <bankarsandhya512@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09usb: Remove unnecessary space before open square bracket.Sandhya Bankar
Remove unnecessary space before open square bracket. Signed-off-by: Sandhya Bankar <bankarsandhya512@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09USB: FHCI: avoid redundant conditionHeinrich Schuchardt
The right part of the following or expression is only evaluated if td is nonzero. !td || (td && td.status == USB_TD_INPROGRESS) So no need to check td again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09usb: host: xhci-rcar: Avoid long wait in xhci_reset()Yoshihiro Shimoda
The firmware of R-Car USB 3.0 host controller will control the reset. So, if the xhci driver doesn't do firmware downloading (e.g. kernel configuration is CONFIG_USB_XHCI_PLATFORM=y and CONFIG_USB_XHCI_RCAR is not set), the reset of USB 3.0 host controller doesn't work correctly. Then, the host controller will cause long wait in xhci_reset() because the CMD_RESET bit of op_regs->command is not cleared for 10 seconds. So, this patch modifies the Kconfig to enable both CONFIG_USB_XHCI_PLATFORM and CONFIG_USB_XHCI_RCAR. Fixes: 4ac8918f3a7 (usb: host: xhci-plat: add support for the R-Car H2 and M2 xHCI controllers) Cc: <stable@vger.kernel.org> # v3.17+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09usb/host/fotg210: remove dead code in create_sysfs_filesColin Ian King
The goto in create_sysfs_files is never executed, so remove it and clean up the code. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09usb: wusbcore: Do not initialise statics to 0.Sandhya Bankar
Do not initialise statics to 0. This patch is found by checkpatch.pl script. Signed-off-by: Sandhya Bankar <bankarsandhya512@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09usb: wusbcore: Remove space before ',' and '(' .Sandhya Bankar
Remove space before ',' and '(' . This patch is detected by checkpatch.pl Signed-off-by: Sandhya Bankar <bankarsandhya512@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09iommu/dma: Implement scatterlist segment mergingRobin Murphy
Stop wasting IOVA space by over-aligning scatterlist segments for a theoretical worst-case segment boundary mask, and instead take the real limits into account to merge consecutive segments wherever appropriate, so our callers can benefit from getting back nicely simplified lists. This also represents the last piece of functionality wanted by users of the current arch/arm implementation, thus brings us a small step closer to converting that over to the common code. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-05-09Merge branch 'for-joerg/arm-smmu/updates' of ↵Joerg Roedel
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
2016-05-09MIPS: Netlogic: Fix CP0_EBASE redefinition warningsJames Hogan
A couple of netlogic assembly files define CP0_EBASE to $15, the same as CP0_PRID in mipsregs.h, and use it for accessing both CP0_PRId and CP0_EBase registers. However commit 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART") added a different definition of CP0_EBASE to mipsregs.h, which included a register select of 1. This causes harmless build warnings like the following: arch/mips/netlogic/common/reset.S:53:0: warning: "CP0_EBASE" redefined #define CP0_EBASE $15 ^ In file included from arch/mips/netlogic/common/reset.S:41:0: ./arch/mips/include/asm/mipsregs.h:63:0: note: this is the location of the previous definition #define CP0_EBASE $15, 1 ^ Update the code to use the definitions from mipsregs.h for accessing both registers. Fixes: 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART") Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Adjust set_pte() SMP fix to handle R10000_LLSC_WARJoshua Kinard
Update the recent changes to set_pte() that were added in 46011e6ea392 to handle R10000_LLSC_WAR, and format the assembly to match other areas of the MIPS tree using the same WAR. This also incorporates a patch recently sent in my Markos Chandras, "Remove local LL/SC preprocessor variants", so that patch doesn't need to be applied if this one is accepted. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Fixes: 46011e6ea392 ("MIPS: Make set_pte() SMP safe.) Cc: David Daney <david.daney@cavium.com> Cc: Linux/MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/11103/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Move definitions for 32/64-bit agonstic inline assembler to new file.Ralf Baechle
Inspired by Markos Chandras' patch. I just didn't want do pull bitsops.h into pgtable.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> References: https://patchwork.linux-mips.org/patch/11052/
2016-05-09MIPS: Fix MSA assembly warningsJames Hogan
Building an MSA capable kernel with a toolchain that supports MSA produces warnings such as this: arch/mips/kernel/r4k_fpu.S:229: Warning: the `msa' extension requires 64-bit FPRs This is due to ".set msa" without ".set fp=64" in the non doubleword MSA load/store macros, since MSA requires the 64-bit FPU registers (FR=1). Add the missing fp=64 in these macros to silence the warnings. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13063/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix MSA assembly with big thread offsetsJames Hogan
When lockdep is enabled on a 64-bit kernel the FPR offset into the thread structure exceeds the maximum range of the MSA ld.d/st.d instructions. For example THREAD_FPR31 = 4644 (instead of 2448), while the signed immediate field is only 10 bits with an implicit multiply by 8, giving a maximum offset of 511*8 = 4088. This isn't a problem when the toolchain doesn't support MSA as the ld_*/st_* macros perform the addition separately into $1 with [d]addui which has a 16bit signed immediate field. Fix the case where the toolchain does support MSA by doing a single addition of THREAD_FPR0 into $1 with [d]addui, and doing the ld_*/st_* relative to that. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13064/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDUJames Hogan
The MSA ld_*/st_* assembler macros for when the toolchain doesn't support MSA use addu to offset the base address. However it is a virtual memory pointer so fix it to use PTR_ADDU which expands to daddu for 64-bit kernels. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.3.y- Patchwork: https://patchwork.linux-mips.org/patch/13062/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Use copy_s.fmt rather than copy_u.fmtPaul Burton
In revision 1.12 of the MSA specification, the copy_u.w instruction has been removed for MIPS32 & the copy_u.d instruction has been removed for MIPS64. Newer toolchains (eg. Codescape SDK essentials 2015.10) will complain about this like so: arch/mips/kernel/r4k_fpu.S:290: Error: opcode not supported on this processor: mips32r2 (mips32r2) `copy_u.w $1,$w26[3]' Since we always copy to the width of a GPR, simply use copy_s instead of copy_u to fix this. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.3.x+ Patchwork: https://patchwork.linux-mips.org/patch/13061/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: memset.S: Disable code unused with non-R6 MIPS configsMaciej W. Rozycki
This complements commit 8c56208aff77 ("MIPS: lib: memset: Add MIPS R6 support"). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12452/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS64: R6: R2 emulation bugfixLeonid Yegoshin
Error recovery pointers for fixups was improperly set as ".word" which is unsuitable for MIPS64. Replaced by STR(PTR) [ralf@linux-mips.org: Apply changes as requested in the review process.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") Cc: macro@linux-mips.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: <stable@vger.kernel.org> # 4.0+ Patchwork: https://patchwork.linux-mips.org/patch/9911/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: dma-default: Defend against NULL dev in massage_gfp_flagsMatt Redfearn
This patch ensures that the dev parameter is checked for NULL before it is dereferenced in massage_gfp_flags. If dev is NULL, then fall back setting the GFP flag requested and available. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11919/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: oprofile: Fix a preemption issueYanjiang Jin
Use boot_cpu_type() instead of current_cpu_type() in oprofile_arch_init() to avoid the below warning, cpu_type is normally consistent in a MIPS SMP system. There are a few exceptions such as SGI servers where it is possible to mix R10000, R12000, R14000 and R16000 within certain constraints. Let's not worry about those now. BUG: using smp_processor_id() in preemptible [00000000] code: insmod/952 caller is oprofile_arch_init+0x30/0x194 [oprofile] CPU: 5 PID: 952 Comm: insmod Not tainted 4.1.13-WR8.0.0.0_standard #1 Stack : ffffffff80c10000 0000000000000001 8000000025bf0790 ffffffff80e10000 ffffffff80e50000 ffffffff80254e2c ffffffff80b64428 ffffffff80e10790 0000000000000000 ffffffff801caeb8 0000000000000045 0000000000000005 ffffffff80c10000 ffffffff801cb798 0000000000000000 ffffffff80e30000 0000000000000000 ffffffff801ff1c0 ffffffff80e2d2f8 000000000000000b ffffffff801cbba0 ffffffff80e107b0 ffffffff80a77828 0000000000000005 00000000000003b8 ffffffff80e2d2f8 800000040ad39960 ffffffff801f9950 0000000000000124 80000004093b7990 80000004093b7ab8 ffffffff80925108 ffffffff80b69a07 ffffffff80a6f0d0 8000000407240e00 ffffffff801cc934 000000000000005d ffffffff80159080 0000000000000005 00000000000003b8 ... Call Trace: [<ffffffff80159080>] show_stack+0xe8/0x108 [<ffffffff80925108>] dump_stack+0x8c/0xd8 [<ffffffff80606570>] check_preemption_disabled+0x110/0x118 [<ffffffffc0086104>] oprofile_arch_init+0x30/0x194 [oprofile] [<ffffffffc008602c>] oprofile_init+0x2c/0xc0 [oprofile] [<ffffffff80100550>] do_one_initcall+0xa0/0x1c0 [<ffffffff80921e04>] do_init_module+0x80/0x1d8 [<ffffffff801fd0d4>] load_module+0x1b74/0x2278 [<ffffffff801fdab4>] SyS_finit_module+0xcc/0xf0 [<ffffffff80165884>] handle_sysn32+0x44/0x70 [ralf@linux-mips.org: Correct commit message.] Signed-off-by: Yanjiang Jin <yanjiang.jin@windriver.com> Cc: rric@kernel.org Cc: jinyanjiang@gmail.com Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11769/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Loongson-3: Fix build error after ld-version.sh modificationHuacai Chen
Commit d5ece1cb074b2c ("Fix ld-version.sh to handle large 3rd version part") modifies the ld version description. This causes a build error on Loongson-3, so fix it. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Loongson-3: Reserve 32MB for RS780E integrated GPUHuacai Chen
Due to datasheet, reserving 0xff800000~0xffffffff (8MB below 4GB) is not enough for RS780E integrated GPU's TOM (top of memory) registers and MSI/MSI-x memory region, so we reserve 0xfe000000~0xffffffff (32MB below 4GB). Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12889/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Reserve nosave data for hibernationHuacai Chen
After commit 92923ca3aacef63c92d ("mm: meminit: only set page reserved in the memblock region"), the MIPS hibernation is broken. Because pages in nosave data section should be "reserved", but currently they aren't set to "reserved" at initialization. This patch makes hibernation work again. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHERAndreas Ruprecht
Commit 6793f55cbc84 ("MIPS: sibyte: Amend dependencies for SIBYTE_BUS_WATCHER") changed the dependencies for SIBYTE_BUS_WATCHER to make it visible only if SIBYTE_BCM112X or SIBYTE_SB1250 are enabled. In the code in arch/mips/sibyte/common/bus_watcher, however, a #if defined() check suggests that this functionality should also be available for SIBYTE_BCM1x55 and SIBYTE_BCM1x80. Make it selectable by extending the dependencies of SIBYTE_BUS_WATCHER in arch/mips/sibyte/Kconfig. Reported-by: Jonas Rabenstein <jonas.rabenstein@studium.uni-erlangen.de> Signed-off-by: Andreas Ruprecht <andreas.ruprecht@fau.de> Cc: valentinrothberg@gmail.com Cc: stefan.hengelein@fau.de Cc: pebolle@tiscali.nl Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: I6400: Icache fills from dcacheJames Hogan
Coherence Manager 3 (CM3) as present in I6400 can fill icache lines effectively from dirty dcaches, so there is no need to flush dirty lines from dcaches through to L2 prior to icache invalidation. Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc evaluates to true, which avoids those dcache flushes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: c-r4k: Sync icache when it fills from dcacheJames Hogan
It is still necessary to handle icache coherency in flush_cache_range() and copy_to_user_page() when the icache fills from the dcache, even though the dcache does not need to be written back. However when this handling was added in commit 2eaa7ec286db ("[MIPS] Handle I-cache coherency in flush_cache_range()"), it did not do any icache flushing when it fills from dcache. Therefore fix r4k_flush_cache_range() to run local_r4k_flush_cache_range() without taking into account whether icache fills from dcache, so that the icache coherency gets handled. Checks are also added in local_r4k_flush_cache_range() so that the dcache blast doesn't take place when icache fills from dcache. A test to mmap a page PROT_READ|PROT_WRITE, modify code in it, and mprotect it to VM_READ|VM_EXEC (similar to case described in above commit) can hit this case quite easily to verify the fix. A similar check was added in commit f8829caee311 ("[MIPS] Fix aliasing bug in copy_to_user_page / copy_from_user_page"), so also fix copy_to_user_page() similarly, to call flush_cache_page() without taking into account whether icache fills from dcache, since flush_cache_page() already takes that into account to avoid performing a dcache flush. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12179/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Enable ptrace hw watchpoints on MIPS R6James Hogan
HARDWARE_WATCHPOINTS isn't being enabled for CPU_MIPSR6, even though it has an identical hardware watchpoint interface to CPU_MIPSR2, which prevents ptrace watchpoints from being loaded when executing a ptraced process even though the watchpoints are described in /proc/cpuinfo. Enable HARDWARE_WATCHPOINTS for CPU_MIPSR6 too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix watchpoint restorationJames Hogan
Commit f51246efee2b ("MIPS: Get rid of finish_arch_switch().") moved the __restore_watch() call from finish_arch_switch() (i.e. after resume() returns) to before the resume() call in switch_to(). This results in watchpoints only being restored when a task is descheduled, preventing the watchpoints from being effective most of the time, except due to chance before the watchpoints are lazily removed. Fix the call sequence from switch_to() through to mips_install_watch_registers() to pass the task_struct pointer of the next task, instead of using current. This allows the watchpoints for the next (non-current) task to be restored without reintroducing finish_arch_switch(). Fixes: f51246efee2b ("MIPS: Get rid of finish_arch_switch().") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.3.x- Patchwork: https://patchwork.linux-mips.org/patch/12726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Avoid using unwind_stack() with usermodeJames Hogan
When showing backtraces in response to traps, for example crashes and address errors (usually unaligned accesses) when they are set in debugfs to be reported, unwind_stack will be used if the PC was in the kernel text address range. However since EVA it is possible for user and kernel address ranges to overlap, and even without EVA userland can still trigger an address error by jumping to a KSeg0 address. Adjust the check to also ensure that it was running in kernel mode. I don't believe any harm can come of this problem, since unwind_stack() is sufficiently defensive, however it is only meant for unwinding kernel code, so to be correct it should use the raw backtracing instead. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/11701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit d2941a975ac745c607dfb590e92bb30bc352dad9)
2016-05-09MIPS: Don't unwind to user mode with EVAJames Hogan
When unwinding through IRQs and exceptions, the unwinding only continues if the PC is a kernel text address, however since EVA it is possible for user and kernel address ranges to overlap, potentially allowing unwinding to continue to user mode if the user PC happens to be in the kernel text address range. Adjust the check to also ensure that the register state from before the exception is actually running in kernel mode, i.e. !user_mode(regs). I don't believe any harm can come of this problem, since the PC is only output, the stack pointer is checked to ensure it resides within the task's stack page before it is dereferenced in search of the return address, and the return address register is similarly only output (if the PC is in a leaf function or the beginning of a non-leaf function). However unwind_stack() is only meant for unwinding kernel code, so to be correct the unwind should stop there. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/11700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Fill in current_cpu_data.coreFlorian Fainelli
Read the core ID in bmips_smp_finish() for BMIPS5000 CPUs to get appropriate processor parenting in set_cpu_sibling_map(). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12380/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Remove maxcpus from BCM97435SVMB DTSFlorian Fainelli
Now that SMP properly works on 7435, do not restrict the number of core, unleash them all. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12379/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435Florian Fainelli
7435 has 4 7038 L1 base register address for each of its Core + TP (for a total of 4 threads of execution), add the two missing cells for Core 1. We are providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they are, and we can later decide to remap these in software to provide proper interrupt affinity/parenting. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12378/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Make whitespacely correct.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization codeFlorian Fainelli
Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to bring them online. Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some additional changes in the L1 interrupt area to work properly with interrupt affinity. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/12377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200Florian Fainelli
BMIPS5000 have a PrID value of 0x5A00 and BMIPS5200 have a PrID value of 0x5B00, which, masked with 0x5A00, returns 0x5A00. Update all conditionals on the PrID to cover both variants since we are going to need this to enable BMIPS5200 SMP. The existing check, masking with 0xFF00 would not cover BMIPS5200 at all. Fixes: 68e6a78373a6d ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)") Fixes: 6465460c92a85 ("MIPS: BMIPS: change compile time checks to runtime checks") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: jaedon.shin@gmail.com Cc: jfraser@broadcom.com Cc: pgynther@google.com Cc: dragan.stancevic@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12279/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Don't BUG_ON when no IPI domain is foundPaul Burton
Commit fbde2d7d8290 ("MIPS: Add generic SMP IPI support") introduced code that BUG_ON's in the case of a kernel that supports IPI domains but does not have one at runtime. This case is possible on Malta where for IPIs we may use either the GIC (which has an IPI IRQ domain implementation) or core-local software interrupts between VPEs (which do not currently have an IPI IRQ domain implementation). We can not know which will be used until runtime when we know whether a GIC is actually present, and if we run on a system with multiple VPEs and no GIC then the BUG_ON is hit. Commit 19fb5818ed60 ("IPS: Fix broken malta qemu") worked around this for the single-core single-VPE case typically seen using QEMU, but does not catch the multi-VPE case. This patch removes the insufficient CPU presence check that was added and works around the bug differently, effectively reverting that commit. A simple way to reproduce this bug is by using QEMU, which partially implements the MT ASE but does not implement the GIC as of version 2.5. Using "-cpu 34Kf -smp 2" will present a system with 2 VPEs in one core & no GIC, hitting the BUG_ON. Given that we're post-merge-window on the way to v4.6, avoid this by just returning from mips_smp_ipi_init when no IPI IRQ domain is found. Ideally at some point all IPI implementations would be converted to the same IPI IRQ domain interface & we'd be able to restore the check. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Fixes: fbde2d7d8290 ("MIPS: Add generic SMP IPI support") Fixes: 19fb5818ed60 ("IPS: Fix broken malta qemu") Reverts: 19fb5818ed60 ("IPS: Fix broken malta qemu") Cc: Qais Yousef <qsyousef@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix siginfo.h to use strict posix typesJames Hogan
Commit 85efde6f4e0d ("make exported headers use strict posix types") changed the asm-generic siginfo.h to use the __kernel_* types, and commit 3a471cbc081b ("remove __KERNEL_STRICT_NAMES") make the internal types accessible only to the kernel, but the MIPS implementation hasn't been updated to match. Switch to proper types now so that the exported asm/siginfo.h won't produce quite so many compiler errors when included alone by a user program. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Christopher Ferris <cferris@google.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 2.6.30- Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12477/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix crash registers on non-crashing CPUsCorey Minyard
As part of handling a crash on an SMP system, an IPI is send to all other CPUs to save their current registers and stop. It was using task_pt_regs(current) to get the registers, but that will only be accurate if the CPU was interrupted running in userland. Instead allow the architecture to pass in the registers (all pass NULL now, but allow for the future) and then use get_irq_regs() which should be accurate as we are in an interrupt. Fall back to task_pt_regs(current) if nothing else is available. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13050/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09mips: Fix CPC_BASE_ADDR mask to match datasheetNikolay Martynov
According to 'MIPS32® interAptivTM Multiprocessing System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15]. This change is tested ith mt7621 which wasn't working without it. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11766/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09pinctrl: nomadik: hide nmk_gpio_get_mode when unusedArnd Bergmann
nmk_gpio_get_mode is only used in one place, and that is conditionally compiled if DEBUG_FS is enabled. A recent cleanup has marked the definition 'static', which now leads to a warning: drivers/pinctrl/nomadik/pinctrl-nomadik.c:614:12: error: 'nmk_gpio_get_mode' defined but not used [-Werror=unused-function] static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) ^~~~~~~~~~~~~~~~~ Moving the function itself inside the #ifdef shuts it up again. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 5e81e0a0913c ("pinctrl: nomadik: use BIT() with offsets consequently") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-09btrfs: fix int32 overflow in shrink_delalloc().Adam Borowski
UBSAN: Undefined behaviour in fs/btrfs/extent-tree.c:4623:21 signed integer overflow: 10808 * 262144 cannot be represented in type 'int [8]' If 8192<=items<16384, we request a writeback of an insane number of pages which is benign (everything will be written). But if items>=16384, the space reservation won't be enough. Signed-off-by: Adam Borowski <kilobyte@angband.pl> Reviewed-by: David Sterba <dsterba@suse.com> Signed-off-by: David Sterba <dsterba@suse.com>
2016-05-09pinctrl: ns2: rename pinctrl_utils_dt_free_mapArnd Bergmann
A conflict of two patches caused a build error when a function got renamed but a new user appeared in the other patch: drivers/pinctrl/bcm/pinctrl-ns2-mux.c:540:17: error: 'pinctrl_utils_dt_free_map' undeclared here (not in a function) .dt_free_map = pinctrl_utils_dt_free_map, ^~~~~~~~~~~~~~~~~~~~~~~~~ This renames the new user of pinctrl_utils_dt_free_map accordingly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: d32f7fd3bbc3 ("pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map") Fixes: b5aa1006e4a9 ("pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-09arm/configs: Add Aspeed defconfigJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09arm/configs/multi_v5: Add Aspeed ast2400Joel Stanley
This adds the Aspeed ast2400 BMC SoC to the build. The SoC has six UARTs so we need to enable the appropriate options for SERIAL_8250 Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09can: ifi: Add more detailed error reportingMarek Vasut
The updated specification for the IFI CANFD core contains description of more detailed error reporting capability of the core. Implement support for this detailed error reporting. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
generated by cgit (git 2.34.1) at 2025-09-21 23:40:42 +0000