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2023-08-15dt-bindings: pinctrl: oxnas,pinctrl: remove obsolete bindingsNeil Armstrong
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 pinctrl bindings. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-2-04a0c5cdda52@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-15pinctrl: pinctrl-oxnas: remove obsolete pinctrl driverNeil Armstrong
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-15dt-bindings: pinctrl: brcm,bcm11351-pinctrl: Convert to YAMLStanislav Jakubek
Convert Broadcom BCM281xx pin controller bindings to DT schema. Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/ZMZ3aEnrrZRDNdO+@standask-GA-A55M-S2HP Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: nsp-gpio: Silence probe deferral messagesFlorian Fainelli
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230808180733.2081353-3-florian.fainelli@broadcom.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: iproc-gpio: Silence probe deferral messagesFlorian Fainelli
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230808180733.2081353-2-florian.fainelli@broadcom.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: single: Add compatible for ti,am654-padconfTony Lindgren
Use the "ti,am654-padconf" compatible to enable the use of wake-up enable and event bits on K3 SOCs that support the daisychain feature Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230808102207.130177-3-d-gole@ti.com [Alphabetized the compatible list] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10dt-bindings: pinctrl: pinctrl-single: add ti,am654-padconf compatibleDhruva Gole
Add the "ti,am654-padconf" compatible to support the new wakeup enable and status bits positions on K3 family SOCs that support the IO daisychain feature. Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230808102207.130177-2-d-gole@ti.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: stm32: set default gpio line names using pin namesValentin Caron
Add stm32_pctrl_get_desc_pin_from_gpio function to find a stm32 pin descriptor which is matching with a gpio. Most of the time pin number is equal to pin index in array. So the first part of the function is useful to speed up. And during gpio bank register, we set default gpio names with pin names. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20230620104349.834687-1-valentin.caron@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: stmfx: Do not check for 0 return after calling platform_get_irq()Ruan Jinjie
Since commit ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk"), there is no possible for platform_get_irq() to return 0. Use the return value from platform_get_irq(). Signed-off-by: Ruan Jinjie <ruanjinjie@huawei.com> Link: https://lore.kernel.org/r/20230803094304.733371-1-ruanjinjie@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: at91-pio4: drop useless check in atmel_conf_pin_config_dbg_show()Sergey Shtylyov
In atmel_conf_pin_config_dbg_show(), checking atmel_pioctrl->pins[pin_id] against being NULL doesn't make any sense as it gets derefenced first and the driver's probe() method immediately returns -ENOMEM when devm_kzalloc() returns NULL for any atmel_pioctrl->pins[] element anyway, thus failing to register the device... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/4ab2f59f-45c1-76a2-94da-3331e8ec4e35@omp.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10ARM: dts: ux500: switch to enable-gpiosKrzysztof Kozlowski
The recommended name for enable GPIOs property in regulator-gpio is "enable-gpios". This is also required by bindings: ste-hrefv60plus-stuib.dtb: regulator-gpio: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230726070353.103989-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: mcp23s08: check return value of devm_kasprintf()Claudiu Beznea
devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 0f04a81784fe ("pinctrl: mcp23s08: Split to three parts: core, I²C, SPI") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230621100409.1608395-1-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07arm64: dts: Replace the IRQ number with the IRQID macro definitionHuqiang Qin
Replacing IRQ numbers with IRQID macro definitions makes node properties easier to understand and also makes GPIO interrupts easier to use. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230724060108.1403662-4-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: Replace the IRQ number in the driver with the IRQID macro definitionHuqiang Qin
Replacing IRQ numbers with IRQID macro definitions makes driver code easier to understand. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230724060108.1403662-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07dt-bindings: interrupt-controller: Add header file for Amlogic Meson-G12A SoCsHuqiang Qin
Add a new dt-binding header that details the interrupt number of the GPIO. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230724060108.1403662-2-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07dt-bindings: pinctrl: Update pinctrl-single to use yamlTony Lindgren
Update binding for yaml and remove the old related txt bindings. Note that we are also adding the undocumented pinctrl-single,slew-rate property. And we only use the first example from the old binding. As we are mostly using a generic compatible across various SoCs, let's not start adding matches for random pin group node naming. Let's standardize on pin group node name ending in -pins with an optional instance number suffix. As a pin group may have additional pins added to it later on, let's always use -pins rather than -pin for the gropu name. Most of the dts files have been updated already for the pin group node names with a few changes still pending. Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230721082654.27036-1-tony@atomide.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: qcom: Remove the unused _groups variable build warningSricharan Ramabadhran
When building with clang toolchain and arm64-randconfig-r015-20230712 kernel test robot reports the below warning. drivers/pinctrl/qcom/pinctrl-ipq5018.c:244:27: warning: unused variable '_groups' [-Wunused-const-variable] static const char * const _groups[] = { ^ 1 warning generated. static const char * const _groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", }; Fixing it by removing the variable. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307120814.vWPY6URk-lkp@intel.com/ Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1689934361-32642-1-git-send-email-quic_srichara@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: qcom: Introduce SM6115 LPI pinctrl driverKonrad Dybcio
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07dt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add SM6115 LPASS TLMMKonrad Dybcio
Add bindings for pin controller in SM6115 Low Power Audio SubSystem LPASS). Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-1-d4883831a858@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high impedanceSai Krishna Potthuri
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. Using these pinctrl properties observed hang issues with older PMUFW(Xilinx ZynqMP Platform Management Firmware), hence reverted the patch. Commit 9989bc33c4894e075167 ("Revert "pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance""). Support for configuring these properties added in PMUFW Configuration Set version 2.0. When there is a request for these configurations from pinctrl driver for ZynqMP platform, xilinx firmware driver checks for this version before configuring these properties to avoid the hang issue and proceeds further only when firmware version is >=2 otherwise it returns error. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230731095026.3766675-5-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07dt-bindings: pinctrl-zynqmp: Add output-enable configurationSai Krishna Potthuri
Add 'output-enable' configuration parameter to the properties list. Using these pinctrl properties observed hang issues with older Xilinx ZynqMP Platform Management Firmware, hence reverted the patch previously. Commit ff8356060e3a5e126abb ("Revert "dt-bindings: pinctrl-zynqmp: Add output-enable configuration""). Support for configuring these properties added in Xilinx ZynqMP Platform Management firmware(PMUFW) Configuration Set version 2.0. Linux firmware driver checks if the configuration is supported by the PMUFW when it gets request for TRISTATE configuration from pinctrl driver. If it supports, then calls will be made otherwise it returns error. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230731095026.3766675-4-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07firmware: xilinx: Add version check for TRISTATE configurationSai Krishna Potthuri
Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx ZynqMP Platform Management Firmware) Configuration Param Set version 2.0. If the requested configuration is TRISTATE and platform is ZYNQMP then check the version before requesting Xilinx firmware to set the configuration. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230731095026.3766675-3-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07firmware: xilinx: Add support to get platform informationDhaval Shah
Add function to get family code and sub family code from the idcode. This family code and sub family code helps to identify the platform. Family code of any platform is on bits 21 to 27 and Sub family code is on bits 19 and 20. Signed-off-by: Dhaval Shah <dhaval.r.shah@amd.com> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230731095026.3766675-2-sai.krishna.potthuri@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-03Merge tag 'renesas-pinctrl-for-v6.6-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.6 - Use the new devm_clk_get_enabled() helper. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-28pinctrl: pinmux: handle radix_tree_insert() errors in ↵Sergey Shtylyov
pinmux_generic_add_function() pinctrl_generic_add_function() doesn't check result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/20230719202253.13469-4-s.shtylyov@omp.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-28pinctrl: core: handle radix_tree_insert() errors in pinctrl_register_one_pin()Sergey Shtylyov
pinctrl_register_one_pin() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/20230719202253.13469-3-s.shtylyov@omp.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-28pinctrl: core: handle radix_tree_insert() errors in pinctrl_generic_add_group()Sergey Shtylyov
pinctrl_generic_add_group() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/20230719202253.13469-2-s.shtylyov@omp.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-25pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helperChristophe JAILLET
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). While at it, use dev_err_probe() which filters -EPROBE_DEFER. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr [geert: Make clk local to rzg2l_pinctrl_probe()] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25pinctrl: renesas: rzv2m: Use devm_clk_get_enabled() helperGeert Uytterhoeven
Simplify clock handling by using the devm_clk_get_enabled() helper, instead of open-coding the same operations. Move the clock pointer from the driver-private data to a local variable, as it is not needed outside the .probe() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cca0b1795fd0335401bdf2be393ab84445e04095.1688396836.git.geert+renesas@glider.be
2023-07-23pinctrl: amd: Don't show `Invalid config param` errorsMario Limonciello
On some systems amd_pinconf_set() is called with parameters 0x8 (PIN_CONFIG_DRIVE_PUSH_PULL) or 0x14 (PIN_CONFIG_PERSIST_STATE) which are not supported by pinctrl-amd. Don't show an err message when called with an invalid parameter, downgrade this to debug instead. Cc: stable@vger.kernel.org # 6.1 Fixes: 635a750d958e1 ("pinctrl: amd: Use amd_pinconf_set() for all config options") Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230717201652.17168-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-23pinctrl: Add driver support for Amlogic C3 SoCsHuqiang Qin
Add a new pinctrl driver for Amlogic C3 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-23dt-bindings: pinctrl: Add compatibles for Amlogic C3 SoCsHuqiang Qin
Add a new compatible name for Amlogic C3 pin controller, and add a new dt-binding header file which document the detail pin names. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: Explicitly include correct DT includesRob Herring
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20dt-bindings: pinctrl: qcom: lpass-lpi: Remove qcom,adsp-bypass-modeKonrad Dybcio
This property was introduced as a bad hack. Now that it's useless, get rid of it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-2-dc18b5bd14f7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: qcom: lpass-lpi: Make the clocks optional, alwaysKonrad Dybcio
Some platforms provide a single clock source to all LPASS peripherals, others provide two, and there are probably others that provide it through magic invisible-to-Linux wires. Rely on bindings to mandate the adequate number of clocks necessary. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-1-dc18b5bd14f7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: tegra: Add support to display pin functionPrathamesh Shete
The current function for a given pin is not displayed via the debugfs. Add support to display the current function that is set for each pin. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: sunxi: Add some defensiveness for regulators arrayMark Brown
The sunxi pinctrl has a fixed size array it uses to store regulators used in the driver. There is currently nothing that ensures that the number of elements in the array is large enough to map the regulators defined by the individual SoCs. While this is currently the case having an explicit check in there will make life easier for anyone debugging memory issues that manifest in the driver so let's add one. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230712-pinctrl-sunxi-boudns-v1-1-85f37de79b9f@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: cy8c95x0: Add reset supportPatrick Rudolph
This patch adds support for an optional "reset" GPIO pin in the cy8c95x0 pinctrl driver. On probe, the reset pin is pulled low to bring chip out of reset. The reset pin has an internal pull-down and can be left floating if not required. The datasheet doesn't mention any timing related to the reset pin. Based on empirical tests, it was found that the chip requires a delay of 250 milliseconds before accepting I2C transfers after driving the reset pin low. Therefore, a delay of 250ms is added before proceeding with I2C transfers. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Link: https://lore.kernel.org/r/20230714081902.2621771-2-Naresh.Solanki@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20dt-bindings: pinctrl: cypress,cy8c95x0: Add reset pinPatrick Rudolph
This patch adds support for an optional reset pin. The reset pin is used to bring the chip into a known state and has an internal pull-down, allowing it to be left floating if not needed. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230714081902.2621771-1-Naresh.Solanki@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16dt-bindings: pinctrl: amlogic,meson-pinctrl-common: allow gpio hogsNeil Armstrong
Allow gpio hog subnodes to the gpio subnode. Fixes: 94df03a45276 ("dt-bindings: pinctrl: Convert Amlogic Meson pinctrl binding") Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230707-topic-amlogic-upstream-pinctrl-fix-bindings-v2-2-2160060446d7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16dt-bindings: pinctrl: amlogic,meson-pinctrl: allow gpio-line-namesNeil Armstrong
Allow gpio-line-names property for the gpio subnodes. Fixes: 94df03a45276 ("dt-bindings: pinctrl: Convert Amlogic Meson pinctrl binding") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230707-topic-amlogic-upstream-pinctrl-fix-bindings-v2-1-2160060446d7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16pinctrl: ti: Convert to devm_platform_get_and_ioremap_resource()Yangtao Li
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230704124742.9596-4-frank.li@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16pinctrl: pic32: Convert to devm_platform_ioremap_resource()Yangtao Li
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230704124742.9596-3-frank.li@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16pinctrl: mvebu: Use devm_platform_get_and_ioremap_resource()Yangtao Li
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230704124742.9596-2-frank.li@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16pinctrl: berlin: as370: Use devm_platform_get_and_ioremap_resource()Yangtao Li
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230704124742.9596-1-frank.li@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16pinctrl: qcom-pmic-gpio: Add support for pmx75Rohit Agarwal
pmx75 pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1688707209-30151-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16pinctrl: qcom-pmic-gpio: Add support for pm7550baRohit Agarwal
pm7550ba pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1688707209-30151-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx75 supportRohit Agarwal
Add support for the pmx75 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1688707209-30151-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-16dt-bindings: pinctrl: qcom-pmic-gpio: Add pm7550ba supportRohit Agarwal
Add support for the pm7550ba GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1688707209-30151-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-10pinctrl: renesas: rzg2l: Handle non-unique subnode namesBiju Das
Currently, sd1 and sd0 have unique subnode names 'sd1_mux' and 'sd0_mux'. If we change these to non-unique subnode names such as 'mux' this can lead to the below conflict as the RZ/G2L pin control driver considers only the names of the subnodes. pinctrl-rzg2l 11030000.pinctrl: pin P47_0 already requested by 11c00000.mmc; cannot claim for 11c10000.mmc pinctrl-rzg2l 11030000.pinctrl: pin-376 (11c10000.mmc) status -22 pinctrl-rzg2l 11030000.pinctrl: could not request pin 376 (P47_0) from group mux on device pinctrl-rzg2l renesas_sdhi_internal_dmac 11c10000.mmc: Error applying setting, reverse things back Fix this by constructing unique names from the node names of both the pin control configuration node and its child node, where appropriate. Based on the work done by Geert for the RZ/V2M pinctrl driver. Fixes: c4c4637eb57f ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230704111858.215278-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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