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2010-10-09r8169: use device model DMA APIStanislaw Gruszka
Use DMA API as PCI equivalents will be deprecated. This change also allow to allocate with GFP_KERNEL where possible. Tested-by: Neal Becker <ndbecker2@gmail.com> Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Acked-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-10-09r8169: allocate with GFP_KERNEL flag when able to sleepStanislaw Gruszka
We have fedora bug report where driver fail to initialize after suspend/resume because of memory allocation errors: https://bugzilla.redhat.com/show_bug.cgi?id=629158 To fix use GFP_KERNEL allocation where possible. Tested-by: Neal Becker <ndbecker2@gmail.com> Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Acked-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-10-09ARM: pxa/balloon3: Disperse MFP configMarek Vasut
Move pin config to appropriate places and use it only if needed. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-By: Jonathan McDowell <noodles@earth.li> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: mmp: update cpuid of pxa168 and pxa910Haojian Zhuang
Correct the cpuid of pxa168 and pxa910. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa: reduce the scope of get_memclk_frequency_10khz()Haojian Zhuang
Up to now, only pxa2xx pcmcia driver is using the API. No other device driver is using this API in PXA3xx or any other PXA silicons. Restrict the scope only on pxa2xx and remove the implementation of pxa3xx. So we can avoid oo much checking on cpuid after more pxa chips supported. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Cc: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa: reduce the scope of get_clk_frequency_khz()Haojian Zhuang
get_clk_frequency_khz() is used in private cpufreq driver. In order to meet the change of different pxa silicons, checking cpuid is introduced in get_clk_frequency_khz(). While more pxa silicons are supported, the workload of checking cpuid is higher. So restrict the scope of get_clk_frequency_khz() on pxa2xx. Different pxa silcions use different private cpufreq driver to avoid too much checking on cpuid. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Cc: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168/teton bga: add board support for i2c and rtc-ds1337Mark F. Brown
Defined I2C/ALARM pin definitions DS1337 RTC alarm support is tied to RTC_INT_GPIO Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168/teton bga: added keypad supportMark F. Brown
Support for Matrix keypad ESC, ENTER, LEFT, and RIGHT Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168: added support for Teton BGA platformMark F. Brown
Added board defintion, header, and debug UART support. Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: mmp: support sparse irqHaojian Zhuang
Add sparse IRQ support in ARCH_MMP. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa: append tavorevb3 supportHaojian Zhuang
Bringup tavorevb3 development platform. UART and PMIC are enabled. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168fb: add .remove functionHaojian Zhuang
The pxa168fb driver is missing .remove function so the framebuffer isn't correctly shut down when the module is removed. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168/aspenite: add board support for keypadMark F. Brown
Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168: added keypad wake clear event support for platformMark F. Brown
Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa27x_keypad: added wakeup event handler for keypad interruptsMark F. Brown
mach-mmp needs to clear wake event in order to clear the keypad interrupt Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168: added wake clear register support for APMUMark F. Brown
Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa168: added keypad supportMark F. Brown
Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-09ARM: pxa: moved pxa27x_keypad.h to platform pxa directoryMark F. Brown
mach-mmp utilizes pxa27x_keypad code so we need to move header to platform pxa directory. Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-10-08Merge branch 'msi-dmi' into releaseLen Brown
2010-10-08Merge branch 'pdc-regression' into releaseLen Brown
2010-10-08intel_idle: enable Atom C6Len Brown
ATM-C6 was commented out, pending public documentation. https://bugzilla.kernel.org/show_bug.cgi?id=19762 Tested-by: Dennis Jansen <Dennis.Jansen@...> Signed-off-by: Len Brown <len.brown@intel.com>
2010-10-08msm: Platform data for msm8x60 IOMMUsStepan Moskovchenko
Add the platform data for the IOMMUs found on the Qualcomm msm8x60 SoC. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: Platform initialization for the IOMMU driverStepan Moskovchenko
Register a driver for the MSM IOMMU devices and a driver for the translation context devices. Set up the global IOMMU registers and initialize the context banks. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: Add MSM IOMMU supportStepan Moskovchenko
Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: add MSM8x60 FFA supportGregory Bean
The MSM8X60 FFA contains different components than the MSM8X60 SURF, and therefore requires a different ARCH type and machine ID. Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: MSM8X60 simulator board supportSteve Muckle
Board configuration for MSM8X60 simulation. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: add msm8x60_surf machineSteve Muckle
Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: physical offset for MSM8X60Jeff Ohlstein
The MSM8x60 has a different physical memory offset than other targets. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: 8x60: setup correct handlers for private interruptsAbhijeet Dharmapurikar
Private Peripheral interrupts could be edge triggered or level triggered depending on the platform. Initialize handlers for these in board file. Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: add build support for msm8x60 targetJeff Ohlstein
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: allow uart to be conditionally disabledDaniel Walker
Some MSM targets don't select the debug UART in this way. For those we need to disable this selection mechanism. Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: dma: add stub functions for dma features not yet present on 8x60Daniel Walker
Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: clock: add dummy clock driverJeff Ohlstein
Need to add this until real clock support for 8x60 goes in, or else some drivers won't compile. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: 8x60: gic initialization fixup for RUMISteve Muckle
On RUMI platform STIs are not enabled by default, contrary to the GIC spec. The bits for STIs in the enable/enable clear registers are also RW instead of RO. STIs need to be enabled at initialization time. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: irq: rename existing entry-macro to entry-macro-vicSteve Muckle
The existing MSM irq entry macro is specific to a VIC implementation. Renaming this makes room for irq support based on other interrupt controllers. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: MSM8X60 RUMI3 board supportSteve Muckle
Board configuration for MSM8X60 emulation on RUMI3. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: timer: support 8x60 timersJeff Ohlstein
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: irqs-8x60: interrupt mapAbhijeet Dharmapurikar
Define the interrupt map in irq-8x60.h Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: initial irq definitions for MSM8X60Steve Muckle
IRQ assignments are different for MSM8X60 than other existing MSMs. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: io: MSM8X60 io supportSteve Muckle
MSM8X60 has different IO mappings than previous MSMs. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08msm: create config option for proc-commSteve Muckle
Some builds may not support the proc-comm interface with the baseband processor. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-08x86, iommu: Update header comments with appropriate namingKonrad Rzeszutek Wilk
The header comments diverged a bit from the implementation. Lets re-sync them. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> LKML-Reference: <1286564028-2352-3-git-send-email-konrad.wilk@oracle.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-10-08ia64, iommu: Add a dummy iommu_table.h file in IA64.Konrad Rzeszutek Wilk
We don't need a complex IOMMU dependency list on IA64 so we just define the IOMMU_* macro which is used the DMAR driver, as a dummy. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> LKML-Reference: <1286564028-2352-2-git-send-email-konrad.wilk@oracle.com> Reported-by: Tony Luck <tony.luck@intel.com> Tested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-10-08spi/topcliff: Add topcliff platform controller hub (PCH) spi bus driverMasayuki Ohtake
Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. This patch adds a driver for the SPI bus integrated into the Topcliff device. Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-08net: clear heap allocation for ETHTOOL_GRXCLSRLALLKees Cook
Calling ETHTOOL_GRXCLSRLALL with a large rule_cnt will allocate kernel heap without clearing it. For the one driver (niu) that implements it, it will leave the unused portion of heap unchanged and copy the full contents back to userspace. Signed-off-by: Kees Cook <kees.cook@canonical.com> Acked-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-10-08Merge branch 'master' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-2.6
2010-10-08isdn: strcpy() => strlcpy()Dan Carpenter
setup.phone and setup.eazmsn are 32 character buffers. rcvmsg.msg_data.byte_array is a 48 character buffer. sc_adapter[card]->channel[rcvmsg.phy_link_no - 1].dn is 50 chars. The rcvmsg struct comes from the memcpy_fromio() in receivemessage(). I guess that means it's data off the wire. I'm not very familiar with this code but I don't see any reason to assume these strings are NULL terminated. Also it's weird that "dn" in a 50 character buffer but we only seem to use 32 characters. In drivers/isdn/sc/scioc.h, "dn" is only a 49 character buffer. So potentially there is still an issue there. The important thing for now is to prevent the memory corruption. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-10-08powerpc/ppc64e: Fix link problem when building ppc64e_defconfigKumar Gala
arch/powerpc/platforms/built-in.o:(.toc1+0x18): undefined reference to `__early_start' This is due to the 85xx/smp.c not handling the 64-bit side properly. We need to set the entry point for secondary cores on ppc64e to generic_secondary_smp_init instead of __early_start that we due on ppc32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-08exofs: Fix double page_unlock BUG in write_begin/endBoaz Harrosh
This BUG is there since the first submit of the code, but only triggered in last Kernel. It's timing related do to the asynchronous object-creation behaviour of exofs. (Which should be investigated farther) The bug is obvious hence the fixed. Signed-off-by: Boaz Harrosh <Boaz Harrosh bharrosh@panasas.com>
2010-10-08mfd: twl4030: Fix dummy irq chip usageThomas Gleixner
The twl irqchip uses the dummy irq chip ack functions, which is NULL now. Switch it over to use irq_ack. Reported-and-tested-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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