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2019-10-11firmware: google: increment VPD key_len properlyBrian Norris
Commit 4b708b7b1a2c ("firmware: google: check if size is valid when decoding VPD data") adds length checks, but the new vpd_decode_entry() function botched the logic -- it adds the key length twice, instead of adding the key and value lengths separately. On my local system, this means vpd.c's vpd_section_create_attribs() hits an error case after the first attribute it parses, since it's no longer looking at the correct offset. With this patch, I'm back to seeing all the correct attributes in /sys/firmware/vpd/... Fixes: 4b708b7b1a2c ("firmware: google: check if size is valid when decoding VPD data") Cc: <stable@vger.kernel.org> Cc: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Guenter Roeck <groeck@chromium.org> Link: https://lore.kernel.org/r/20190930214522.240680-1-briannorris@chromium.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-11MAINTAINERS: kgdb: Add myself as a reviewer for kgdb/kdbDouglas Anderson
I'm interested in kdb / kgdb and have sent various fixes over the years. I'd like to get CCed on patches so I can be aware of them and also help review. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Daniel Thompson <daniel.thompson@linaro.org> Link: https://lore.kernel.org/r/20190920104404.1.I237e68e8825e2d6ac26f8e847f521fe2fcc3705a@changeid Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-11spufs: fix a crash in spufs_create_root()Emmanuel Nicolet
The spu_fs_context was not set in fc->fs_private, this caused a crash when accessing ctx->mode in spufs_create_root(). Fixes: d2e0981c3b9a ("vfs: Convert spufs to use the new mount API") Signed-off-by: Emmanuel Nicolet <emmanuel.nicolet@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20191008141342.GA266797@gmail.com
2019-10-10io_uring: fix sequence logic for timeout requestsJens Axboe
We have two ways a request can be deferred: 1) It's a regular request that depends on another one 2) It's a timeout that tracks completions We have a shared helper to determine whether to defer, and that attempts to make the right decision based on the request. But we only have some of this information in the caller. Un-share the two timeout/defer helpers so the caller can use the right one. Fixes: 5262f567987d ("io_uring: IORING_OP_TIMEOUT support") Reported-by: yangerkun <yangerkun@huawei.com> Reviewed-by: Jackie Liu <liuyun01@kylinos.cn> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-10-10Merge branch 'smc-fixes'Jakub Kicinski
Karsten Graul says: ==================== Fixes for -net, addressing two races in SMC receive path and add a missing cleanup when the link group creating fails with ISM devices and a VLAN id. ==================== Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-10-10net/smc: receive pending data after RCV_SHUTDOWNKarsten Graul
smc_rx_recvmsg() first checks if data is available, and then if RCV_SHUTDOWN is set. There is a race when smc_cdc_msg_recv_action() runs in between these 2 checks, receives data and sets RCV_SHUTDOWN. In that case smc_rx_recvmsg() would return from receive without to process the available data. Fix that with a final check for data available if RCV_SHUTDOWN is set. Move the check for data into a function and call it twice. And use the existing helper smc_rx_data_available(). Fixes: 952310ccf2d8 ("smc: receive data from RMBE") Reviewed-by: Ursula Braun <ubraun@linux.ibm.com> Signed-off-by: Karsten Graul <kgraul@linux.ibm.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-10-10net/smc: receive returns without dataKarsten Graul
smc_cdc_rxed_any_close_or_senddone() is used as an end condition for the receive loop. This conflicts with smc_cdc_msg_recv_action() which could run in parallel and set the bits checked by smc_cdc_rxed_any_close_or_senddone() before the receive is processed. In that case we could return from receive with no data, although data is available. The same applies to smc_rx_wait(). Fix this by checking for RCV_SHUTDOWN only, which is set in smc_cdc_msg_recv_action() after the receive was actually processed. Fixes: 952310ccf2d8 ("smc: receive data from RMBE") Reviewed-by: Ursula Braun <ubraun@linux.ibm.com> Signed-off-by: Karsten Graul <kgraul@linux.ibm.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-10-10net/smc: fix SMCD link group creation with VLAN idUrsula Braun
If creation of an SMCD link group with VLAN id fails, the initial smc_ism_get_vlan() step has to be reverted as well. Fixes: c6ba7c9ba43d ("net/smc: add base infrastructure for SMC-D and ISM") Signed-off-by: Ursula Braun <ubraun@linux.ibm.com> Signed-off-by: Karsten Graul <kgraul@linux.ibm.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-10-10drm/amdgpu/swSMU/navi: add feature toggles for more thingsAlex Deucher
Add toggles for more power features. Helpful in debugging. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/powerplay: Use swap() where appropriateVille Syrjälä
@swap@ identifier TEMP; expression A,B; @@ - TEMP = A; - A = B; - B = TEMP; + swap(A, B); @@ type T; identifier swap.TEMP; @@ ( - T TEMP; | - T TEMP = {...}; ) ... when != TEMP Cc: Rex Zhu <rex.zhu@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Use swap() where appropriateVille Syrjälä
Mostly a cocci-job, but it flat out refused to remove the declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so had to do that part manually. @swap@ identifier TEMP; expression A,B; @@ - TEMP = A; - A = B; - B = TEMP; + swap(A, B); @@ type T; identifier swap.TEMP; @@ ( - T TEMP; | - T TEMP = {...}; ) ... when != TEMP Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu: Do not implement power-on for SDMA after do mode2 reset on Renoirchen gong
Find that ring sdma0 test failed if turn on SDMA powergating after do mode2 reset. Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is already powered up so there is no need to ask the SMU to power it up again. So I skip this function for a moment. Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/powerplay: add more feature bitsXiaojie Yuan
Additional features that can be enabled in the SMU. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe syncXiaojie Yuan
sdma will hang once sequence number to be polled reaches 0x1000_0000 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/powerplay: fix typo in mvdd table setupAlex Deucher
Polaris and vegam use count for the value rather than level. This looks like a copy paste typo from when the code was adapted from previous asics. I'm not sure that the SMU actually uses this value, so I don't know that it actually is a bug per se. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609 Reported-by: Robert Strube <rstrube@gmail.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu: fix memory leakNirmoy Das
cleanup error handling code and make sure temporary info array with the handles are freed by amdgpu_bo_list_put() on idr_replace()'s failure. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu: avoid ras error injection for retired pageTao Zhou
check whether a page is bad page before umc error injection, bad page should not be accessed again Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu: Use the ALIGN() macroLuben Tuikov
Use the ALIGN() macro to set "num_dw" to a multiple of 8, i.e. lower 3 bits cleared. Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/ras: document the reboot ras optionAlex Deucher
We recently added it, but never documented it. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/ras: fix typos in documentationAlex Deucher
Fix a couple of spelling typos. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: add renoir specific watermark range and clk helperDmytro Laktyushkin
Doing this allows us to split it for diffrent asics. This design will be helpful for future Asciis. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: hook up notify watermark ranges and get clock tableEric Yang
[Why] Previously SMU was giving us 0s for the clock table. Now they have valid clock table. We should use theirs. Also, need to send SMU watermark ranges for selecting optimal watermarks. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Skip DIG Check if Link is Virtual for Display CountSung Lee
[WHY] Without a check for virtual links, every link's DIG was getting checked for enabled or disabled. If link was virtual, since it did not have a DIG, this would cause issues. [HOW] Skip DIG Enable check if link is virtual and add virtual link to to display count. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: correct stream LTE_340MCSC_SCRAMBLE valueWayne Lin
[Why] HDMI 2.0 requires scrambling under specific conditions. We refer to stream property LTE_340MCSC_SCRAMBLE to determine whether en/dis scrambling. While creating stream for sink, we setup LTE_340MCSC_SCRAMBLE by referring to edid_caps. However, dm_helpers_parse_edid_caps() doesn't construct HDMI Forum block data for edid_caps. Moreover, fill_stream_properties_from_drm_display_mode() aslo unconsciously clear the LTE_340MCSC_SCRAMBLE flag. [How] Drm already provides drm_display_info to refer HDMI Forum vsdb info. Set stream LTE_340MCSC_SCRAMBLE by drm_display_info and remove memset in fill_stream_properties_from_drm_display_mode() Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Fix dongle_caps containing stale information.David Galiffi
[WHY] During detection: function: get_active_converter_info populates link->dpcd_caps.dongle_caps only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS. Otherwise, it is not cleared, and stale information remains. During mode validation: function: dp_active_dongle_validate_timing reads link->dpcd_caps.dongle_caps->dongle_type to determine the maximum pixel clock to support. This information is now stale and no longer valid. [HOW] dp_active_dongle_validate_timing should be using link->dpcd_caps->dongle_type instead. Signed-off-by: David Galiffi <david.galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Add capability check for static ramp calcJaehyun Chung
[Why] Static ramp to max refresh rate does not have capability check on calculated v_total. Programming a lower v_total_min and max than the total causes continuous spurious HPDs. [How] Add a capability check after v_total calculation similar to calculate v_total helper functions. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: 3.2.54Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: make aux defer delay and aux sw start delay seperateXiaodong Yan
[why] 1. defer delay and sw start delay has been mixed up, defer delay was programmed to AUX_SW_CONTROL:AUX_SW_START_DELAY. 2. There's no delay for defer [how] 1. Set aux sw start to 0 2. Add delay for defer scenario Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: use vbios message to call smu for dpm levelCharlene Liu
[Description] use vbios message to call smu for dpm level also only program dmdata in vsyncflip as HW requirement. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Fix maybe-uninitialized warningLeo Li
[Why] Compiling with GCC 9.1.0 gives the following warning (I have warnings-as-errors enabled): drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c: In function 'dc_validate_seamless_boot_timing': drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c:1180:8: error: 'se' may be used uninitialized in this function [-Werror=maybe-uninitialized] 1180 | if (!se->funcs->dp_get_pixel_format( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1181 | se, | ~~~ 1182 | &hw_crtc_timing.pixel_encoding, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1183 | &hw_crtc_timing.display_color_depth)) [How] Initialize se to NULL. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: add more checks to validate seamless boot timingMartin Leung
[why] we found using an active DP to HDMI panel that we weren't validating dp_pixel_format and hardware timing v_front_porch, causing screen to blank and/or corrupt while attempting a seamless boot. [how] added checks during dc_validate_seamless_boot_timing for these values Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: add new active dongle to existent w/aVitaly Prosyak
[Why & How] Dongle 0x00E04C power down all internal circuits including AUX communication preventing reading DPCD table. Encoder will skip DP RX power down on disable output to keep receiver powered all the time. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Update number of dcn21 audio endpointsMichael Strauss
[WHY] Number of audio endpoints wasn't updated from dcn20's 6 when created [HOW] Changed num_audio to 4 to match the correct sbios value Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: add guard for SMU ver, for 48mhz clkJoseph Gravenor
[why] dp_48m_refclk_driver_pwdn is persistent through S3 and S5. This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix so we will hang on reboot [how] add a guard for smu versions before SMU FW 55.21.0 Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: fix code to control 48mhz refclkEric Yang
[Why] The SMU message to enable this feature looks at argument. Previous code didn't send right argument. This change will allow the feature to be be enabled. [How] Fixed one issue where SMU message to enable the feature was sent without setting the parameter. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: exit PSR during detectionEric Yang
[Why] If 48mhz refclk is turned off during PSR, we will have issue doing link training during detection. [How] Get out of PSR before detection Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Program DWB watermarks from correct stateJulian Parkin
[Why] When diags adds a DWB via a stream update, we calculate MMHUBBUB paramaters, but dc->current_state has not yet been updated when the DWB programming happens. This leads to overflow on high bandwidth tests since the incorrect MMHUBBUB arbitration parameters are programmed. [How] Pass the updated context down to the (enable|update)_writeback functions so that they can use the correct watermarks when programming MMHUBBUB. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: 3.2.53Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Use dcn1 Optimal Taps GetWesley Chalmers
[WHY] dpp2_get_optimal_number_of_taps is incorrect, and dcn2 should be using dpp1_get_optimal_number_of_taps instead Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: fix bug with check for HPD Low in verify link capSivapiriyan Kumarasamy
[Why] There is a bug when determining if link training should be retried when HPD is low in dp_verify_link_cap_with_retries. [How] Correctly, fail dp_verify_link_cap_with_retries without retry when HPD is low. Signed-off-by: Sivapiriyan Kumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: wait for set pipe mcp command completionJosip Pavic
[Why] When the driver sends a pipe set command to the DMCU FW, it does not wait for the command to complete. This can lead to unpredictable behavior if, for example, the driver were to request a pipe disable to the FW via MCP, then power down some hardware before the firmware has completed processing the command. [How] Wait for the DMCU FW to finish processing set pipe commands Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Add output bitrate to DML calculationsNikola Cornij
[why] Output bitrate was mistakenly left out, causing corruption on some DSC low resolution (such as 800x600) modes. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Properly round nominal frequency for SPDAric Cyr
[Why] Some displays rely on the SPD verticle frequency maximum value. Must round the calculated refresh rate to the nearest integer. [How] Round the nominal calculated refresh rate to the nearest whole integer. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Restore should_update_pstate_support after bad revertJoshua Aberback
[Why] This function was mistakenly reverted as part of a legitimate revert. The old version that was reverted to has bad logic, and is causing situations where p-state change support is being toggled when it shouldn't be, resulting in hangs. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: check phy dpalt lane count configLewis Huang
[Why] Type-c PHY config is not align with dpcd lane count. When those values didn't match, it cause driver do link training with 4 lane but phy only can output 2 lane. The link trainig always fail. [How] 1. Modify get_max_link_cap function. According DPALT_DP4 to update max lane count. 2. Add dp_mst_verify_link_cap to handle MST case because we didn't call dp_mst_verify_link_cap for MST case. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: build up VSIF infopacketWayne Lin
[Why] Didn't send VSIF infopacket when it's 4k mode defined in HDMI 1.4b. For HDMI 1.4b, While displaying 4k modes, it should send VSP. [How] Call mod_build_hf_vsif_infopacket() function to build info frame and send it. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: 3.2.52Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: Add missing shifts and masks for dpp registers on dcn2Joshua Aberback
[Why] The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is called from dpp2_cnv_setup, but the shifts and masks for the fields of that register are not initialized for dcn2. This causes all reads of that register to return 0. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: add explicit comparator as default optimization checkJun Lei
[why] memcmp is vulnerable to regression due to dc_clocks structures not being organized properly (not "current" clock related structures being at the beginning of the structure) and causes unnecessary setting of the optimize bit [how] add a dcn sepcific comparator, implement for dcn2 Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/display: add support for VSIP info packetWayne Lin
[Why] The vendor specific infoframe is needed for HDMI while displaying specific modes. DC supports sending it, but we aren't currently building it [How] Add mod_build_hf_vsif_infopacket() to build the vendor specific info packet. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-15 16:51:28 +0000