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This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add ams AS3722 entry for gpio/pincontrol and regulators
to venice2 DT.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Compare the initial population of default pinmux configuration of Venice2
with the chrome branch and add/fix the missing configurations.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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From Jason Cooper:
mvebu DT changes for v3.14 (incr. #3)
- kirkwood
- use symbolic names for gpios and key inputs
- mvebu
- add the pxa nand controller to the ReadyNAS and A370-RD boards
* tag 'mvebu-dt-3.14-3' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Enable NAND controller in A370 Reference Design board
ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file
ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file
ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file
ARM: DT: Kirkwood: Use symbolic names from gpio.h
ARM: DT: Kirkwood: Use symbolic names from input.h
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
From Linus Walleij:
Some Nomadik Device Tree updates for the v3.14 cycle:
- Drop 0x prefixes
- Get rid of explicit GPIO management
* tag 'nomadik-dt-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: get rid of explicit ethernet GPIO management
ARM: nomadik: Remove '0x's from nomadik stn8815 DTS file
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Now that the DTS file r8a7790-lager.dts can be used with board-lager.c
and board-lager-reference.c, proceed with removing
r8a7790-lager-reference.dts.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The external crystal frequency is 20MHz on the Koelsch board. Specify it
in the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The external crystal frequency is 20MHz on the Lager board. Specify it
in the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Copy the device nodes from Koelsch reference into the Koeslch device
tree file. This will allow us to use a single DTS file regarless of
kernel configuration. In case of legacy C board code the device nodes
may or may not be used, but in the multiplatform case all the DT device
nodes are used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Copy the device nodes from Lager reference into the Lager device tree
file. This will allow us to use a single DTS file regarless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
are used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Declare all core clocks and DIV6 clocks, as well as all MSTP clocks
currently used by r8a7791 boards.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Declare all core clocks and DIV6 clocks, as well as all MSTP clocks
currently used by r8a7790 boards.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The board had 4 buttons connected to GPIOs, add a corresponding
gpio-keys device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The Armadillo 800 EVA panel module has a backlight enable signal
connected to GPIO 61. Report this in the backlight DT node.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Commit 22ceeee16eb8f0d04de3ef43a5174fb30ec18af9 ("pwm-backlight: Add
power supply support") added a mandatory power supply for the PWM
backlight. Add a fixed 5V regulator and reference it for the backlight
power supply.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The koelsch board uses has an SH ethernet controller which uses a Micrel
phy. Select MICREL_PHY for koelsch if SH_ETH is enabled to make use of the
Micrel-specific phy driver rather than relying on the generic phy driver.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Linux 3.13-rc3
Conflicts:
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
drivers/pinctrl/sh-pfc/pfc-sh7372.c
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into dt3-base
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This is a commit from the for-next branch of Linus Walleij's pin control tre
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
It is the oldest commit in that branch that provides the dependencies
needed for SoC changes to the usage of sh-pfc.
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When CONFIG_COMMON_CLOCK is enabled, call rcar_gen2_clocks_init() in the
timer init function to initialize the common clock framework before
initializing the clock sources. This will take care of clock
initialization when the r8a779[01] boards will be switched to
multiplatform kernels.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add macros usable by device tree sources to reference r8a7791 clocks by
index.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add macros usable by device tree sources to reference r8a7790 clocks by
index.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
tegra124-venice2.dts isn't touched yet since we haven't added any off-
SoC RTC device to its device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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According to board schematics, for HSMMC1 a GPIO line is used to detect
card presence, while currently it is being configured for internal card
detect line, which is multiplexed with card detect line of HSMMC0 and
thus breaking it.
This patch adds proper sdhci platform data setting card detect type to
external GPIO and fixing operation of HSMMC0.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Prepare the clock at probe time, as there is no other appropriate place
in the driver where we're allowed to sleep.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The SPI controllers on Tegra124 are compatible with those found on the
Tegra114 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This pin needs to be configured in pull-down, non-tristate mode in order
for the backlight to work correctly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Other boards use PULL_NONE for their debug UART pins, and without this
change, the board doesn't accept any serial input.
Don't set the I2S port pins to tristate mode, or no audio signal will
be sent out.
Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add the default pinmux configuration for the Tegra124 based
Venice2 platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Set the parent of the regulators LDO2 to LDO9 according to the
schematic. Set the base voltage to 3.3V, there is only 3.3V on the
module itself.
Set the Core and CPU voltage to the specified voltages of 1.2V and
1.0V respectivly.
LDO6 should deliver 2.85V. The attached peripherals were not in
use so far.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra114 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This new header file defines pincontrol constants for Tegra to
use from Tegra's DTS file for pincontrol properties option.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use key code macros for all key code refernced for keys.
For tegra20-seaboard.dts and tegra20-harmony.dts:
The key comment for key (16th row and 1st column) is KEY_KPSLASH but
code is 0x004e which is the key code for KEY_KPPLUS. As there other
key exist with KY_KPPLUS, I am assuming key code is wrong and comment
is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Subsequent patches will need to reference a PWM channel for backlight
support, so enable the PWM device and assign a label to it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The PWM controller on Tegra124 is the same as the one on earlier SoC
generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, added reset properties]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers,
and a combo headphones/microphone jack. Add a top-level sound card node
to represent this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra124 contains a similar set of audio devices to previous Tegra chips.
Specifically, there is an AHUB device which contains DMA FIFOs and audio
routing, and which hosts various audio-related components such as I2S
controllers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Enable all the I2C controllers that are wired up on Venice2. I don't
know the correct I2C bus clock rates, so set them all to a conservative
100KHz for now.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra124 has 6 I2C controllers. The first 5 have identical configuration
to Tegra114, but the sixth obviously has different interrupt/... IDs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.
Also enable the relevant controllers in the Venice2 board DT.
power-gpios property suggested by Thierry Reding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
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