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2023-04-20usb: gadget: tegra-xudc: Remove unneeded return variableJon Hunter
The 'ret' variable in the function tegra_xudc_gadget_vbus_draw() is not needed and so remove this variable. Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230405181854.42355-2-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-04-20usb: gadget: tegra-xudc: Fix crash in vbus_drawJon Hunter
Commit ac82b56bda5f ("usb: gadget: tegra-xudc: Add vbus_draw support") populated the vbus_draw callback for the Tegra XUDC driver. The function tegra_xudc_gadget_vbus_draw(), that was added by this commit, assumes that the pointer 'curr_usbphy' has been initialised, which is not always the case because this is only initialised when the USB role is updated. Fix this crash, by checking that the 'curr_usbphy' is valid before dereferencing. Fixes: ac82b56bda5f ("usb: gadget: tegra-xudc: Add vbus_draw support") Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230405181854.42355-1-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-04-20net: bridge: switchdev: don't notify FDB entries with "master dynamic"Vladimir Oltean
There is a structural problem in switchdev, where the flag bits in struct switchdev_notifier_fdb_info (added_by_user, is_local etc) only represent a simplified / denatured view of what's in struct net_bridge_fdb_entry :: flags (BR_FDB_ADDED_BY_USER, BR_FDB_LOCAL etc). Each time we want to pass more information about struct net_bridge_fdb_entry :: flags to struct switchdev_notifier_fdb_info (here, BR_FDB_STATIC), we find that FDB entries were already notified to switchdev with no regard to this flag, and thus, switchdev drivers had no indication whether the notified entries were static or not. For example, this command: ip link add br0 type bridge && ip link set swp0 master br0 bridge fdb add dev swp0 00:01:02:03:04:05 master dynamic has never worked as intended with switchdev. It causes a struct net_bridge_fdb_entry to be passed to br_switchdev_fdb_notify() which has a single flag set: BR_FDB_ADDED_BY_USER. This is further passed to the switchdev notifier chain, where interested drivers have no choice but to assume this is a static (does not age) and sticky (does not migrate) FDB entry. So currently, all drivers offload it to hardware as such, as can be seen below ("offload" is set). bridge fdb get 00:01:02:03:04:05 dev swp0 master 00:01:02:03:04:05 dev swp0 offload master br0 The software FDB entry expires $ageing_time centiseconds after the kernel last sees a packet with this MAC SA, and the bridge notifies its deletion as well, so it eventually disappears from hardware too. This is a problem, because it is actually desirable to start offloading "master dynamic" FDB entries correctly - they should expire $ageing_time centiseconds after the *hardware* port last sees a packet with this MAC SA - and this is how the current incorrect behavior was discovered. With an offloaded data plane, it can be expected that software only sees exception path packets, so an otherwise active dynamic FDB entry would be aged out by software sooner than it should. With the change in place, these FDB entries are no longer offloaded: bridge fdb get 00:01:02:03:04:05 dev swp0 master 00:01:02:03:04:05 dev swp0 master br0 and this also constitutes a better way (assuming a backport to stable kernels) for user space to determine whether the kernel has the capability of doing something sane with these or not. As opposed to "master dynamic" FDB entries, on the current behavior of which no one currently depends on (which can be deduced from the lack of kselftests), Ido Schimmel explains that entries with the "extern_learn" flag (BR_FDB_ADDED_BY_EXT_LEARN) should still be notified to switchdev, since the spectrum driver listens to them (and this is kind of okay, because although they are treated identically to "static", they are expected to not age, and to roam). Fixes: 6b26b51b1d13 ("net: bridge: Add support for notifying devices about FDB add/del") Link: https://lore.kernel.org/netdev/20230327115206.jk5q5l753aoelwus@skbuf/ Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Tested-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/20230418155902.898627-1-vladimir.oltean@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2023-04-20Merge tag 'usb-serial-6.4-rc1' of ↵Greg Kroah-Hartman
https://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial into usb-next Johan writes: USB-serial updates for 6.4-rc1 Here are the USB-serial updates for 6.4-rc1; a new modem device id and an unused-function cleanup. All have been in linux-next with no reported issues. * tag 'usb-serial-6.4-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial: USB: serial: option: add UNISOC vendor and TOZED LT70C product USB: serial: quatech2: remove unused qt2_setdevice function
2023-04-20ALSA: hda/realtek: fix mute/micmute LEDs for a HP ProBookAndy Chi
There is a HP ProBook 455 G10 which using ALC236 codec and need the ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF quirk to make mute LED and micmute LED work. Signed-off-by: Andy Chi <andy.chi@canonical.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20230420035942.66817-1-andy.chi@canonical.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-04-20Merge tag 'asoc-fix-v6.3-rc7' of ↵Takashi Iwai
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus ASoC: Fixes for v6.3 A few remaining small fixes for v6.3, all small driver specific ones.
2023-04-19Merge branch 'Access variable length array relaxed for integer type'Alexei Starovoitov
Feng zhou says: ==================== From: Feng Zhou <zhoufeng.zf@bytedance.com> Add support for integer type of accessing variable length array. Add a selftest to check it. ==================== Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2023-04-19selftests/bpf: Add test to access integer type of variable arrayFeng Zhou
Add prog test for accessing integer type of variable array in tracing program. In addition, hook load_balance function to access sd->span[0], only to confirm whether the load is successful. Because there is no direct way to trigger load_balance call. Co-developed-by: Chengming Zhou <zhouchengming@bytedance.com> Signed-off-by: Chengming Zhou <zhouchengming@bytedance.com> Signed-off-by: Feng Zhou <zhoufeng.zf@bytedance.com> Link: https://lore.kernel.org/r/20230420032735.27760-3-zhoufeng.zf@bytedance.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2023-04-19bpf: support access variable length array of integer typeFeng Zhou
After this commit: bpf: Support variable length array in tracing programs (9c5f8a1008a1) Trace programs can access variable length array, but for structure type. This patch adds support for integer type. Example: Hook load_balance struct sched_domain { ... unsigned long span[]; } The access: sd->span[0]. Co-developed-by: Chengming Zhou <zhouchengming@bytedance.com> Signed-off-by: Chengming Zhou <zhouchengming@bytedance.com> Signed-off-by: Feng Zhou <zhoufeng.zf@bytedance.com> Link: https://lore.kernel.org/r/20230420032735.27760-2-zhoufeng.zf@bytedance.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2023-04-19ext4: Add a uapi header for ext4 userspace APIsJosh Triplett
Create a uapi header include/uapi/linux/ext4.h, move the ioctls and associated data structures to the uapi header, and include it from fs/ext4/ext4.h. Signed-off-by: Josh Triplett <josh@joshtriplett.org> Link: https://lore.kernel.org/r/680175260970d977d16b5cc7e7606483ec99eb63.1680402881.git.josh@joshtriplett.org Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2023-04-19ext4: remove useless conditional branch codewuchi
It's ok because the code will be optimized by the compiler, just try to simple the code. Signed-off-by: wuchi <wuchi.zero@gmail.com> Reviewed-by: Jan Kara <jack@suse.cz> Link: https://lore.kernel.org/r/20230401075303.45206-1-wuchi.zero@gmail.com Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2023-04-19ext4: remove unneeded check of nr_to_submitTom Rix
cppcheck reports fs/ext4/page-io.c:516:51: style: Condition 'nr_to_submit' is always true [knownConditionTrueFalse] if (fscrypt_inode_uses_fs_layer_crypto(inode) && nr_to_submit) { ^ This earlier check to bail, makes this check unncessary /* Nothing to submit? Just unlock the page... */ if (!nr_to_submit) return 0; Signed-off-by: Tom Rix <trix@redhat.com> Fixes: dff4ac75eeee ("ext4: move keep_towrite handling to ext4_bio_write_page()") Reviewed-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20230316204831.2472537-1-trix@redhat.com Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2023-04-20powerpc/Makefile: Don't prefix archhelp commands with "@"Michael Ellerman
It's not necessary to prefix every command in archhelp with "@" (to suppress echoing the command), because that is done by the top level Makefile when it evaluates archhelp. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230329072334.2023357-1-mpe@ellerman.id.au
2023-04-20powerpc/pseries: Always inline functions called from cpuidleMichael Ellerman
Code in the idle path is not allowed to be instrumented because RCU is disabled, see commit 0e985e9d2286 ("cpuidle: Add comments about noinstr/__cpuidle usage"). Force inlining of the inline functions called from cpuidle, to ensure they are not emitted out-of-line and then available for tracing. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406144535.3786008-4-mpe@ellerman.id.au
2023-04-20cpuidle: pseries: Mark ->enter() functions as __cpuidleMichael Ellerman
Code in the idle path is not allowed to be instrumented because RCU is disabled, see commit 0e985e9d2286 ("cpuidle: Add comments about noinstr/__cpuidle usage"). Mark the cpuidle ->enter() callbacks as __cpuidle and use the raw_local_irq_*() routines to ensure that is the case. Reported-by: Sachin Sant <sachinp@linux.ibm.com> Link: https://lore.kernel.org/all/4C073F6A-C812-4C4A-BB7A-ECD10B75FB88@linux.ibm.com/ Suggested-by: Peter Zijlstra <peterz@infradead.org> Tested-by: Sachin Sant <sachinp@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406144535.3786008-3-mpe@ellerman.id.au
2023-04-20powerpc/64: Don't call trace_hardirqs_on() in prep_irq_for_idle()Michael Ellerman
Since commit a01353cf1896 ("cpuidle: Fix ct_idle_*() usage"), the cpuidle entry code calls trace_hardirqs_on() (actually trace_hardirqs_on_prepare()) in ct_cpuidle_enter() before calling into the cpuidle driver. Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406144535.3786008-2-mpe@ellerman.id.au
2023-04-20powerpc/64: Mark prep_irq_for_idle() __cpuidleMichael Ellerman
Code in the idle path is not allowed to be instrumented because RCU is disabled, see commit 0e985e9d2286 ("cpuidle: Add comments about noinstr/__cpuidle usage"). Mark prep_irq_for_idle() __cpuidle, which is equivalent to noinstr, to enforce that. Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406144535.3786008-1-mpe@ellerman.id.au
2023-04-20powerpc/irq: Mark check_return_regs_valid() notraceMichael Ellerman
check_return_regs_valid() is called from the middle of the irq exit handling, which is all notrace, so mark it notrace also. Reported-by: Sachin Sant <sachinp@linux.ibm.com> Link: https://lore.kernel.org/all/4C073F6A-C812-4C4A-BB7A-ECD10B75FB88@linux.ibm.com/ Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406122118.3760344-1-mpe@ellerman.id.au
2023-04-20powerpc/corenet: Add PPC_QEMU_E500 to corenet configsMichael Ellerman
Add PPC_QEMU_E500 to corenet_base.config, which is then used to generate corenet64_smp_defconfig and corenet32_smp_defconfig. That then allows both those configs to build kernels that boot in qemu using the ppce500 machine type and respectively -cpu e5500 or -cpu e500mc. The code that is added by PPC_QEMU_E500 just defines another machine with a probe function that recognises qemu, so there should be no change when booting on actual hardware supported by CORENET_GENERIC. The increase in vmlinux size is less than 1KB. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230411102838.512859-1-mpe@ellerman.id.au
2023-04-20powerpc: drop MPC8272-ADS and PowerQUICC II FADS shared code.Paul Gortmaker
With the two platforms depending on this shared code, and no others, we can remove the orphaned code and Kconfigs Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230224204959.17425-4-paul.gortmaker@windriver.com
2023-04-20powerpc: drop PowerQUICC II Family ADS platform supportPaul Gortmaker
Based on documentation revision dates, this MPC82xx pq2fads system predates the MPC8272-ADS variant by about a year and only has 1/2 the amount of RAM (32MB) -- largely making it useless with a modern v6.x kernel from today. Similar to the MPC8272-ADS the pq2fads also supported other 82xx CPU variants, had 8MB flash, and like the 8272 ADS platform, was on a fairly large PCB in order to have space for breakout connectors for all features. These 82xx platforms are two decades old, and originally made for a small group of industry related people in order to assist in new OEM board designs. Given that, it makes sense to remove support today. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230224204959.17425-3-paul.gortmaker@windriver.com
2023-04-20powerpc: drop MPC8272_ADS platform supportPaul Gortmaker
The MPC8272-ADS also supported other 82xx CPU variants, had 64MB RAM, 8MB flash, and like the 85xx ADS platforms, was on a fairly large PCB in order to have space for breakout connectors for all the features. These 82xx platforms are two decades old, and originally made for a small group of industry related people in order to assist in new OEM board designs. Given that, it makes sense to remove support today. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230224204959.17425-2-paul.gortmaker@windriver.com
2023-04-20powerpc: drop HPCD/MPC8610 evaluation platform supportPaul Gortmaker
This evaluation platform was essentially a single core 8641 with integrated graphics/display support - in an effort to reduce chip count on kiosk and similar applications. Compared to other evaluation platforms considered for removal in other recent commits, this platform was relatively rare. Unlike all the other 10+ platforms, I couldn't find any documentation on it - just a link to downloading the 2007 era BSP in "LTIB" format as was done back then. With all that in mind, it seems prudent to remove it here in 2023. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> [mpe: Drop stale reference to MPC8610_HPCD in 86xx/Kconfig] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230225201318.3682-4-paul.gortmaker@windriver.com
2023-04-20powerpc: drop HPC-NET/MPC8641D evaluation platform supportPaul Gortmaker
There is no denying that this was an interesting platform in its day. Access to a SMP powerpc platform became a bit more obtainable for folks in the BSP industry in the 2007 era, thanks to this platform. Add to that the move to the black Antec case vs. the generic white 2005 era case of the MPC8548CDS or the retro 1950s 1/2 height horizontal case of the HPC II, and it was pretty interesting to people like myself then. However, like all the other evaluation platforms, the overall system was complex out of necessity, as it tried to showcase all possible features and use-cases. That included an AMP option, where you could run two bootloaders and two kernels over two serial consoles. Peripheral sharing got a bit more tricky when you got to the hard disk and similar. In any case we still have the same circumstance. A relatively rare and expensive evaluation platform that is now 15+ years old and not out there in large numbers in the general public. Removal in 2023 just makes sense. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230225201318.3682-3-paul.gortmaker@windriver.com
2023-04-20powerpc: drop HPC II (MPC7448) evaluation platform support.Paul Gortmaker
This was an interesting platform - it was the 1st instance of a respin of earlier 130nm 74xx CPUs on 90nm and systems using MPC7448 were positioned as a rack server platform solution. Given that, the evaluation platform (at least the one I had) was shipped in a horizontal 1/2 height Antec desktop case with retro styling and colours, despite the fact the docs explicitly stated that the HPC II is not a desktop machine (noting it had no gfx or legacy PC I/O support). Historic trivia aside, this was the 1st introduction of the e600 procfam as an evolution from the earlier G4. However even with the claim to being "1st e600" it seems the 2005+ era was turning its attention to multicore support and from my memory this poor guy was quickly overshadowed by the dual core MPC8641D. All that aside, we are once again looking at 15+ year old evaluation platforms that were not widely distributed, so 2023 removal makes sense. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230225201318.3682-2-paul.gortmaker@windriver.com
2023-04-20powerpc: drop MPC832x_MDS platform supportPaul Gortmaker
This final variant in the e300 family of Modular Development System (MDS) in this series was actually aimed at feature reduction - things like floating point and ethernet were removed in order to make for a lower power and lower cost system. Like all the MDS systems, it was meant as a vehicle to get the CPU out early to hardware OEMs so software and board development could take place in parallel. These were made in limited numbers and availability preference was given to partners who were planning to make their own boards. Given that the whole reason for existence was to assist in enabling new board designs [not happening for 10+ years], and that they weren't generally available, and that the hardware wasn't really hobbyist friendly even for retro computing, it makes sense to retire the support for this particular platform. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Li Yang <leoyang.li@nxp.com> [mpe: Drop stale reference to MPC832x_MDS in arch/powerpc/boot/Makefile] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230220115913.25811-5-paul.gortmaker@windriver.com
2023-04-20powerpc: drop MPC837x_MDS platform supportPaul Gortmaker
This next evolutionary step in the e300 family of Modular Development System (MDS) still has, at its core component, a full length card with a PCI edge. No case. Serial and network connectors were on card, so it could optionally be fitted with plastic stand-offs and run stand-alone off a power brick. This is very similar to the MPC834x_MDS and MPC836x_MDS removed in the prior commits, but with this board variant as yet another evolutionary step. SATA and PCI-e were now available. But overall the form factor and design goals were unchanged. Like all the MDS systems, it was meant as a vehicle to get the CPU out early to hardware OEMs so software and board development could take place in parallel. These were made in limited numbers and availability preference was given to partners who were planning to make their own boards. Given that the whole reason for existence was to assist in enabling new board designs [not happening for 10+ years], and that they weren't generally available, and that the hardware wasn't really hobbyist friendly even for retro computing, it makes sense to retire the support for this particular platform. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230220115913.25811-4-paul.gortmaker@windriver.com
2023-04-20powerpc: drop MPC836x_MDS platform supportPaul Gortmaker
This 2006 era Modular Development System (MDS) has, at its core component, a full length card with a PCI edge. No case. Serial and network connectors were on card, so it could optionally be fitted with plastic stand-offs and run stand-alone off a power brick. This is very similar to the MPC834x_MDS removed in the prior commit, but with this board variant as an evolutionary step. DDR2 was now an option, and the card edge was revised down to PCI-32 as PCI-64 never got traction. But overall the form factor and design goals were unchanged. Like all the MDS systems, it was meant as a vehicle to get the CPU out early to hardware OEMs so software and board development could take place in parallel. To that end, the BGA CPU was held in place with a mechanical spring loaded pressure assembly (vs. solder) so that early rev silicon could be replaced in the field. Not for COTS deployment! These were made in limited numbers and availability preference was given to partners who were planning to make their own boards. Given that the whole reason for existence was to assist in enabling new board designs [not happening for 10+ years], and that they weren't generally available, and that the hardware wasn't really hobbyist friendly even for retro computing, it makes sense to retire the support for this particular platform. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Li Yang <leoyang.li@nxp.com> [mpe: Drop stale reference to MPC836x_MDS in arch/powerpc/boot/Makefile] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230220115913.25811-3-paul.gortmaker@windriver.com
2023-04-20powerpc: drop MPC834x_MDS platform supportPaul Gortmaker
This 2006 era Modular Development System (MDS) has, at its core component, a full length card with a PCI-64 edge. No case. Serial and network connectors were on card, so it could optionally be fitted with plastic stand-offs and run stand-alone off a power brick. Like all the MDS systems, it was meant as a vehicle to get the CPU out early to hardware OEMs so software and board development could take place in parallel. To that end, the BGA CPU was held in place with a mechanical spring loaded pressure assembly (vs. solder) so that early rev silicon could be replaced in the field. Not for COTS deployment! These were made in limited numbers and availability preference was given to partners who were planning to make their own boards, like our WR SBC8349 [since retired in v4.18 (2017, commit 3bc6cf5a86e5)] Given that the whole reason for existence was to assist in enabling new board designs [not happening for 10+ years], and that they weren't generally available, and that the hardware wasn't really hobbyist friendly even for retro computing, it makes sense to retire the support for this platform. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230220115913.25811-2-paul.gortmaker@windriver.com
2023-04-20powerpc/pseries: Add FW_FEATURE_PLPKS feature flagAndrew Donnellan
Add a firmware feature flag, FW_FEATURE_PLPKS, to indicate availability of Platform KeyStore related hcalls. Check this flag in plpks_is_available() and pseries_plpks_init() before trying to make an hcall. Suggested-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230224041012.772648-1-ajd@linux.ibm.com
2023-04-20selftests/powerpc/dscr: Restore timeout to DSCR selftestsBenjamin Gray
Reducing the time taken by dscr_sysfs_test.c allows restoring the default timeout, which was removed in commit 850507f30c38 ("selftests/powerpc: Turn off timeout setting for benchmarks, dscr, signal, tm") because that test took too long. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-8-bgray@linux.ibm.com
2023-04-20selftests/powerpc/dscr: Speed up DSCR sysfs testsBenjamin Gray
This test case is extremely slow, taking around a minute compared to most of the other DSCR tests taking a second at most. Perf shows most time is spent by the kernel switching to each CPU it reads in /sys/devices/system/cpu. This switching is an unavoidable consequnce of reading all the .../cpuN/dscr values. Remove the outer iteration loop from this test case, reducing the reads from 1600 to 16. This still updates the DSCR 16 times and verifies on every CPU each time, so I do not expect the lower coverage to be meaningful. The speedup is significant: back down to ~1 second like the other tests. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-7-bgray@linux.ibm.com
2023-04-20selftests/powerpc/dscr: Improve DSCR explicit random test caseBenjamin Gray
The tests currently have a single writer thread updating the system DSCR with a 1/1000 chance looped only 100 times. So only around one in 10 runs actually do anything. * Add multiple threads to the dscr_explicit_random_test case. * Use a barrier to make all the threads start work as simultaneously as possible. * Use a rwlock and make all threads have a reasonable chance to write to the DSCR on each iteration. PTHREAD_RWLOCK_PREFER_WRITER_NONRECURSIVE_NP is used to prevent writers from starving while all the other threads keep reading. Logging the reads/writes shows a decent mix across the whole test. * Allow all threads a chance to write. * Make the chance of writing more likely. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-6-bgray@linux.ibm.com
2023-04-20selftests/powerpc/dscr: Add lockstep test cases to DSCR explicit testsBenjamin Gray
Add new cases to the relevant tests that use explicitly synchronized threads to test the behaviour across context switches with less randomness. By locking the participants to the same CPU we guarantee a context switch occurs each time they make progress, which is a likely failure point if the kernel is not tracking the thread local DSCR correctly. The random case is left in to keep exercising potential edge cases. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-5-bgray@linux.ibm.com
2023-04-20selftests/powerpc: Allow bind_to_cpu() to automatically pick CPUBenjamin Gray
All current users of bind_to_cpu() don't care _which_ CPU they get, just that they are bound to a single free one. So alter the interface to 1. Accept a BIND_CPU_ANY value that tells it to automatically pick a CPU 2. Return the picked CPU And convert all these users to bind_to_cpu(BIND_CPU_ANY). Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-4-bgray@linux.ibm.com
2023-04-20selftests/powerpc: Move bind_to_cpu() to utils.hBenjamin Gray
This function will be useful in the DSCR test patches later in this series, so promote it to be shared by all powerpc selftests. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-3-bgray@linux.ibm.com
2023-04-20selftests/powerpc/dscr: Correct typosBenjamin Gray
Correct a couple of typos while working on other improvements to the DSCR tests. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230406043320.125138-2-bgray@linux.ibm.com
2023-04-20powerpc: Remove duplicate SPRN_HSRR definitionsJoel Stanley
There are two copies of these defines. Keep the older ones as they have associated bit definitions. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230405045316.95003-1-joel@jms.id.au
2023-04-20powerpc/64: modules support building with PCREL addresingNicholas Piggin
Build modules using PCREL addressing when CONFIG_PPC_KERNEL_PCREL=y. - The module loader must handle several new relocation types: * R_PPC64_REL24_NOTOC is a function call handled like R_PPC_REL24, but does not restore r2 upon return. The external function call stub is changed to use pcrel addressing to load the function pointer rather than based on the module TOC. * R_PPC64_GOT_PCREL34 is a reference to external data. A GOT table must be built by hand, because the linker adds this during the final link (which is not done for kernel modules). The GOT table is built similarly to the way the external function call stub table is. This section is called .mygot because .got has a special meaning for the linker and can become upset. * R_PPC64_PCREL34 is used for local data addressing, but there is a special case where the percpu section is moved at load-time to the percpu area which is out of range of this relocation. This requires the PCREL34 relocations are converted to use GOT_PCREL34 addressing. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Some coding style & formatting fixups] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-7-npiggin@gmail.com
2023-04-20powerpc/64: vmlinux support building with PCREL addresingNicholas Piggin
PC-Relative or PCREL addressing is an extension to the ELF ABI which uses Power ISA v3.1 PC-relative instructions to calculate addresses, rather than the traditional TOC scheme. Add an option to build vmlinux using pcrel addressing. Modules continue to use TOC addressing. - TOC address helpers and r2 are poisoned with -1 when running vmlinux. r2 could be used for something useful once things are ironed out. - Assembly must call C functions with @notoc annotation, or the linker complains aobut a missing nop after the call. This is done with the CFUNC macro introduced earlier. - Boot: with the exception of prom_init, the execution branches to the kernel virtual address early in boot, before any addresses are generated, which ensures 34-bit pcrel addressing does not miss the high PAGE_OFFSET bits. TOC relative addressing has a similar requirement. prom_init does not go to the virtual address and its addresses should not carry over to the post-prom kernel. - Ftrace trampolines are converted from TOC addressing to pcrel addressing, including module ftrace trampolines that currently use the kernel TOC to find ftrace target functions. - BPF function prologue and function calling generation are converted from TOC to pcrel. - copypage_64.S has an interesting problem, prefixed instructions have alignment restrictions so the linker can add padding, which makes the assembler treat the difference between two local labels as non-constant even if alignment is arranged so padding is not required. This may need toolchain help to solve nicely, for now move the prefix instruction out of the alternate patch section to work around it. This reduces kernel text size by about 6%. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-6-npiggin@gmail.com
2023-04-20powerpc: add CFUNC assembly label annotationNicholas Piggin
This macro is to be used in assembly where C functions are called. pcrel addressing mode requires branches to functions with a localentry value of 1 to have either a trailing nop or @notoc. This macro permits the latter without changing callers. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Add dummy definitions to fix selftests build] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-5-npiggin@gmail.com
2023-04-20powerpc/64: Add support to build with prefixed instructionsNicholas Piggin
Add an option to build kernel and module with prefixed instructions if the CPU and toolchain support it. This is not related to kernel support for userspace execution of prefixed instructions. Building with prefixed instructions breaks some extended inline asm memory addressing, for example it will provide immediates that exceed the range of simple load/store displacement. Whether this is a toolchain or a kernel asm problem remains to be seen. For now, these are replaced with simpler and less efficient direct register addressing when compiling with prefixed. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-4-npiggin@gmail.com
2023-04-20powerpc/64s: Run at the kernel virtual address earlier in bootNicholas Piggin
This mostly consolidates the Book3E and Book3S behaviour in boot WRT executing from the physical or virtual address. Book3E sets up kernel virtual linear map in start_initialization_book3e and runs from the virtual linear alias after that. This change makes Book3S begin to execute from the virtual alias at the same point. Book3S can not use its MMU for that at this point, but when the MMU is disabled, the virtual linear address correctly aliases to physical memory because the top bits of the address are ignored with MMU disabled. Secondaries execute from the virtual address similarly early. This reduces the differences between subarchs, but the main motivation was to enable the PC-relative addressing ABI for Book3S, where pointer calculations must execute from the virtual address or the top bits of the pointer will be lost. This is similar to the requirement the TOC relative addressing already has that the TOC pointer use its virtual address. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-3-npiggin@gmail.com
2023-04-20powerpc/64: Move initial base and TOC pointer calculationNicholas Piggin
A later change moves the non-prom case to run at the virtual address earlier, which calls for virtual TOC and kernel base. Split these two calculations for prom and non-prom to make that change simpler. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Retain relative_toc call for start_initialization_book3e] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408021752.862660-2-npiggin@gmail.com
2023-04-20powerpc: dts: turris1x.dts: Remove "fsl,P2020RDB-PC" compatible stringPali Rohár
"fsl,P2020RDB-PC" compatible string was present in Turris 1.x DTS file just because Linux kernel required it for proper detection of P2020 processor during boot. This was quite a hack as CZ.NIC Turris 1.x is not compatible with Freescale P2020-RDB-PC board. Now when kernel has generic unified support for boards with P2020 processors, there is no need to have this "hack" in turris1x.dts file. So remove incorrect "fsl,P2020RDB-PC" compatible string from turris1x.dts. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408140122.25293-14-pali@kernel.org
2023-04-20powerpc/85xx: p2020: Enable boards by new config option CONFIG_PPC_P2020Pali Rohár
Generic unified P2020 machine description which supports all P2020-based boards is now in separate file p2020.c. So create a separate config option CONFIG_PPC_P2020 for it. Previously machine descriptions for P2020 boards were enabled by CONFIG_MPC85xx_DS or CONFIG_MPC85xx_RDB option. So set CONFIG_PPC_P2020 to be enabled by default when one of those option is enabled. This allows to compile support for P2020 boards without need to have enabled support for older mpc85xx boards. And to compile kernel for old mpc85xx boards without having enabled support for new P2020 boards. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408140122.25293-13-pali@kernel.org
2023-04-20powerpc/85xx: p2020: Define just one machine descriptionPali Rohár
Combine machine descriptions and code of all P2020 boards into just one generic unified P2020 machine description. This allows kernel to boot on any P2020-based board with P2020 DTS file without need to patch kernel and define a new machine description in 85xx powerpc platform directory. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408140122.25293-12-pali@kernel.org
2023-04-20powerpc/85xx: p2020: Unify .setup_arch and .init_IRQ callbacksPali Rohár
Make just one .setup_arch and one .init_IRQ callback implementation for all P2020 board code. This deduplicate repeated and same code. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408140122.25293-11-pali@kernel.org
2023-04-20powerpc/85xx: mpc85xx_ds: Move i8259 code into own filePali Rohár
In order to share mpc85xx i8259 code between DS and P2020. Prefix i8259 debug and error messages by i8259 word. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> [mpe: Fix some coding style warnings in the moved code] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230408140122.25293-10-pali@kernel.org
2023-04-19x86: remove 'zerorest' argument from __copy_user_nocache()Linus Torvalds
Every caller passes in zero, meaning they don't want any partial copy to zero the remainder of the destination buffer. Which is just as well, because the implementation of that function didn't actually even look at that argument, and wasn't even aware it existed, although some misleading comments did mention it still. The 'zerorest' thing is a historical artifact of how "copy_from_user()" worked, in that it would zero the rest of the kernel buffer that it copied into. That zeroing still exists, but it's long since been moved to generic code, and the raw architecture-specific code doesn't do it. See _copy_from_user() in lib/usercopy.c for this all. However, while __copy_user_nocache() shares some history and superficial other similarities with copy_from_user(), it is in many ways also very different. In particular, while the code makes it *look* similar to the generic user copy functions that can copy both to and from user space, and take faults on both reads and writes as a result, __copy_user_nocache() does no such thing at all. __copy_user_nocache() always copies to kernel space, and will never take a page fault on the destination. What *can* happen, though, is that the non-temporal stores take a machine check because one of the use cases is for writing to stable memory, and any memory errors would then take synchronous faults. So __copy_user_nocache() does look a lot like copy_from_user(), but has faulting behavior that is more akin to our old copy_in_user() (which no longer exists, but copied from user space to user space and could fault on both source and destination). And it very much does not have the "zero the end of the destination buffer", since a problem with the destination buffer is very possibly the very source of the partial copy. So this whole thing was just a confusing historical artifact from having shared some code with a completely different function with completely different use cases. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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