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https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 FVP/Vexpress/Juno updates for v6.15
The main and bulk of the addition this time is the support for the Arm
reference Morello System Development Platform (SDP).
The Morello architecture is an experimental extension to Armv8.2-A,
enhancing the AArch64 execution state with capabilities for fine-grained
memory protection and scalable software compartmentalization. However
these changes doesn't add any of the support for security enhancements.
This is mainly adding device tree support for Morello SDP.
The platform iteslf is shipped with ACPI firmware. However, since the
ACPI bindings for GPU, DPU, I2C, I2S,..etc are not well defined or not
provided in the shipped ACPI firmware, there is a need for the device
tree as alternative for the developers focusing on those features.
The CPU is called rainier, the architecture is Morello and the platform
is Morello SDP board. There is FVP equivalent of the same though they
are not completely in feature parity with the real hardware.
These changes provide the initial support for Morello SDP and FVP
platforms.
Apart from this, we have an update to add support for secondary cores
on Corstone1000 FVP platform.
* tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: corstone1000: Add definitions for secondary CPU cores
MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer
arm64: dts: morello: Add support for fvp dts
arm64: dts: morello: Add support for soc dts
arm64: dts: morello: Add support for common functionalities
dt-bindings: arm-pmu: Add support for ARM Rainier PMU
dt-bindings: arm: Add Rainier compatibility
dt-bindings: arm: Add Morello fvp compatibility
dt-bindings: arm: Add Morello compatibility
arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS
Link: https://lore.kernel.org/r/20250304105856.432848-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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soc/dt
Apple SoC DT updates for 6.15, second batch:
- Added a missing p-state for iPad mini 4
- Added SPI controller nodes for M1 and M2 devices
- Added SPI NOR flash nodes and NVRAM partitions
- Added touchbar digitizer nodes for M1 and M2 devices
* tag 'asahi-soc-dt-6.15-v2' of https://github.com/AsahiLinux/linux:
arm64: dts: apple: Add touchbar digitizer nodes
arm64: dts: apple: Add SPI NOR nvram partition to all devices
arm64: dts: apple: t600x: Add spi controller nodes
arm64: dts: apple: t8112: Add spi controller nodes
arm64: dts: apple: t8103: Add spi controller nodes
arm64: dts: apple: t8103: Fix spi4 power domain sort order
arm64: dts: apple: t7000: Add missing CPU p-state 7 for J96 and J97
Link: https://lore.kernel.org/r/20250302115808.59172-1-sven@svenpeter.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.15
- Add support for the second and third Ethernet interfaces on the Gray
Hawk Single development board,
- Add Image Signal Processor helper block (FCPVX and VSPX) support for
the R-Car V3U and V4M SoCs,
- Add Watchdog and System Controller support for the RZ/G3E SoC and
the RZ/G3E SMARC Carrier-II EVK development board,
- Add initial support for the Yuridenki-Shokai Kakip and MYIR Remi Pi
boards,
- Add support for the spare UART and PMOD serial ports on the RZ/G3S
SMARC Carrier II board,
- Add a CPU Operating Performance Points table for the RZ/G3S SoC,
- Add boot phase tags on R-Car Gen2/3/4 and RZ/G2 boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
ARM: dts: renesas: r9a06g032: Fix UART dma channel order
arm64: dts: renesas: rzg2: Add boot phase tags
arm64: dts: renesas: rcar: Add boot phase tags
ARM: dts: renesas: rcar-gen2: Add boot phase tags
arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line orders
arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for capture
arm64: dts: renesas: Add initial support for MYIR Remi Pi
arm64: dts: renesas: r9a08g045: Add OPP table
arm64: dts: renesas: r9a09g057: Enable SYS node
arm64: dts: renesas: r9a09g047: Add SYS node
arm64: dts: renesas: r9a08g045: Enable SYS node
arm64: dts: renesas: r8a779f0: Disable rswitch ports by default
arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches
arm64: dts: renesas: r8a779g0: Restore sort order
arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitch
arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitch
arm64: dts: renesas: s4sk: Access rswitch ports via phandles
arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles
...
Link: https://lore.kernel.org/r/cover.1740156747.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.15
- Document support for the Yuridenki-Shokai Kakip (based on RZ/V2H)
and MYIR Remi Pi (based on RZ/G2L) boards,
- Document support for the RZ/G3E System Controller.
* tag 'renesas-dt-bindings-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: Document MYIR Remi Pi board
dt-bindings: soc: renesas: Add RZ/G3E variant SYS binding
dt-bindings: soc: renesas: Document Yuridenki-Shokai Kakip board
dt-bindings: vendor-prefixes: Add Yuridenki-Shokai Co. Ltd.
dt-bindings: soc: renesas: Document more Renesas RZ/V2H SoC variants
Link: https://lore.kernel.org/r/cover.1740156745.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
Some minor IXP4xx updates for v6.15:
- Assing the right NPE for EthA
- Fix up erroneous PCI mappings on WG302
- Add LEDs and keys on GPIO to WG302
* tag 'ixp4xx-dts-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
ARM: dts: ixp4xx: Fix up PCI on WG302
ARM: dts: Properly assign NPE to ethA
Link: https://lore.kernel.org/r/CACRpkdbi_A_RCufEZSk0cEoQ_H-s0VLGUzJ9zPQECSvsUP7-dQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Apple SoC DT updates for 6.15:
- Added device trees for Apple T2 SoCs
- Added cpufreq and PMGR compatibles and nodes for Apple A7-A11 and T2
SoCs
* tag 'asahi-soc-dt-6.15' of https://github.com/AsahiLinux/linux: (23 commits)
arm64: dts: apple: t8015: Add cpufreq nodes
arm64: dts: apple: t8012: Add cpufreq nodes
arm64: dts: apple: t8011: Add cpufreq nodes
arm64: dts: apple: t8010: Add cpufreq nodes
arm64: dts: apple: s8001: Add cpufreq nodes
arm64: dts: apple: Add cpufreq nodes for S8000/S8003
arm64: dts: apple: t7001: Add cpufreq nodes
arm64: dts: apple: t7000: Add cpufreq nodes
arm64: dts: apple: s5l8960x: Add cpufreq nodes
arm64: dts: apple: t8015: Add PMGR nodes
arm64: dts: apple: t8012: Add PMGR nodes
arm64: dts: apple: t8011: Add PMGR nodes
arm64: dts: apple: t8010: Add PMGR nodes
arm64: dts: apple: s8001: Add PMGR nodes
arm64: dts: apple: s800-0-3: Add PMGR nodes
arm64: dts: apple: t7001: Add PMGR node
arm64: dts: apple: t7000: Add PMGR node
arm64: dts: apple: s5l8960x: Add PMGR node
dt-bindings: arm: apple: apple,pmgr-pwrstate: Add A7-A11, T2 compatibles
dt-bindings: arm: apple: apple,pmgr: Add A7-A11, T2 compatibles
...
Link: https://lore.kernel.org/r/20250209135558.8243-1-sven@svenpeter.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add cpu{1-3} device nodes to the corstone1000 device tree to enable the
support for secondary CPU cores.
This update facilitates symmetric multiprocessing (SMP) support on the
corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores
to be properly initialised and utilised.
Only FVP platform will have SMP support and hence the secondary cpu
definitions are not added to corstone1000.dtsi.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com>
(sudeep.holla: Added psci enable-method for cpu0)
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add Vincenzo Frascino <vincenzo.frascino@arm.com> as Arm Morello Software
Development Platform Maintainer.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-11-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
Introduce Morello fvp dts.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
Introduce Morello SoC dts.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-9-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
some functionalities that have conveniently been included in
morello.dtsi to avoid duplication.
Introduce morello.dtsi.
Note: Morello fvp will be introduced with a future patch series.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-8-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add support for the ARM Rainier CPU core PMU.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-6-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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The Arm Morello System Development Platform uses Rainier CPUs.
Add compatibility to Rainier.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-5-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add compatibility to Arm Morello Fixed Virtual Platform.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-4-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Add compatibility to Arm Morello System Development Platform.
Note: Morello is at the same time the name of an Architecture [1], an SoC
[2] and a Board [2].
To distinguish in between Architecture/SoC and Board we refer to the first
as arm,morello and to the second as arm,morello-sdp.
[1] https://developer.arm.com/Architectures/Morello
[2] https://www.morello-project.org/
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-3-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Update the description and contextually the help text of
CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-Id: <20250221180349.1413089-2-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Adds device tree entries for the touchbar digitizer
Co-developed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Link: https://lore.kernel.org/r/20250225-z2-dts-v1-1-df101a7c17c8@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
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make dtbs_check:
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: serial@50000000: dma-names:0: 'tx' was expected
from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: serial@50000000: dma-names:1: 'rx' was expected
from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
...
The DT bindings specify a fixed order of the channels in the dmas and
dma-names properties, while the Linux driver does not care.
Get rid of the warnings by changing the order in the DTS to match the
bindings.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/bcb604ad6e567de4e0410756ba840c82a32ff7d3.1739525488.git.geert+renesas@glider.be
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bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas RZ/G2 SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas R-Car SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas R-Car Gen2 SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The symbolic names for the line-orders are now available in
<dt-bindings/media/video-interfaces.h>. Switch to them instead of using
their numerical values.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250205103311.668768-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Current ulcb/kf of -mix+split.dtsi is using TDM Split Mode, but only for
playback. Use TDM Split Mode on capture too.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/875xlrshp5.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add basic support for the MYIR Remi Pi (based on r9a07g044l2):
- UART,
- I2C,
- eMMC,
- USB host,
- HDMI output,
- Ethernet.
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250131-myir-remi-pi-v3-2-2dda53e79291@collabora.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add OPP table for the Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250128145616.2691841-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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SoC identification needs the System Controller. Enable it.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250123170508.13578-10-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add a node for the System Controller to the RZ/G3E (R9A09G047) SoC DTSI,
as it is also required for SoC identification.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250123170508.13578-9-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Enable the System Controller. It is needed for SoC identification.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250123170508.13578-8-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The Renesas Ethernet Switch has three independent ports. Each port can
act as a separate interface, and can be enabled or disabled
independently. Currently all ports are enabled by default, hence board
DTS files that enable the switch must disable all unused ports
explicitly.
Disable all ports by default, and explicitly enable ports that are used,
next to their configuration.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/c4688de8e3289ad82c2cd85f0893eac660ac8890.1737649969.git.geert+renesas@glider.be
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Add a DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through
the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II
board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Enable SCIF3. It is routed to the SER1_UART interface on the RZ SMARC
Carrier II board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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different switches
There are different switches available on both the RZ/G3S SMARC Module and
RZ SMARC Carrier II boards. These switches are used to route different SoC
signals to different parts available on board.
These switches are described in device trees through macros. These macros
are set accordingly such that the resulted compiled dtb to describe the
on-board switches states.
The SCIF1 depends on the state of the SW_CONFIG3 and SW_OPT_MUX4 switches.
SCIF1 can be enabled through a device tree overlay. To manage all switches
in a unified state and allow users to configure the output device tree, add
a file that contains all switch definitions and states.
Commit prepares the code to enable SCIF1 on the RZ/G3S overlay.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Numerical by unit address, but grouped by type.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/ccd215c1146b84c085908e01966f7036be51afa8.1737370801.git.geert+renesas@glider.be
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Each rswitch port TSNn has a dedicated MAC address assigned to it, so
does AVB MAC. The MAC addresses for each rswitch port and AVB, four in
total, are stored in the FPGA populated on the board and can be read out
via I2C from bus i2c@e66e0000 address 0x70 offsets 0x58 for AVB and
0x60, 0x68, 0x70 for TSNn.
There is no single MAC address assigned to the rswitch itself, there are
three of them, one for each rswitch port. Instead of ethernet0 alias
for rswitch itself, describe aliases ethernet0, ethernet1 for each
enabled rswitch port. This allows U-Boot to insert MAC addresses from
its environment variables ethaddr/eth1addr/eth2addr into each rswitch
port nodes, so Linux can read and use one unique MAC address for each
rswitch port.
Note that it is unlikely this would break existing rswitch driver
operation in the Linux kernel, because as of right now, the rswitch
driver already calls of_get_ethdev_address() for each port to read
out the MAC address of each rswitch port DT node. If that is missing,
it falls back to MAC address settings read from the hardware itself.
If that also fails, it uses a random MAC address.
Fixes: 412f2224b3b6 ("arm64: dts: renesas: s4sk: Fix ethernet0 alias")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-5-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The rswitch has three independent ports which each can act as a separate
interface with its own MAC address. Describe DT aliases ethernet0,
ethernet1, ethernet2 for each rswitch port in DT. This allows U-Boot to
insert MAC addresses from its environment variables
ethaddr/eth1addr/eth2addr into each rswitch port nodes, so Linux can
read and use one unique MAC address for each rswitch port.
Note that it is unlikely this would break existing rswitch driver
operation in the Linux kernel, because as of right now, the rswitch
driver already calls of_get_ethdev_address() for each port to read
out the MAC address of each rswitch port DT node. If that is missing,
it falls back to MAC address settings read from the hardware itself.
If that also fails, it uses a random MAC address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-4-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The r8a779f0.dtsi now contains labels for each rswitch port in the form
'rswitch_portN'. Use those to access rswitch ports and slightly reduce
the depth of this board DT. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The r8a779f0.dtsi now contains labels for each rswitch port in the form
'rswitch_portN'. Use those to access rswitch ports and slightly reduce
the depth of this board DT. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Introduce labels for each rswitch port in the form 'rswitch_portN'.
Those can be used to access rswitch port nodes directly, which is going
to be useful in reducing DT indentation slightly as well as in the DT
/aliases node to reference the rswitch ports as ethernetN interfaces.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250118111344.361617-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add basic support for the Yuridenki-Shokai Kakip board based on
R9A09G057H48, including:
- Memory
- OSTM0 - OSTM7
- Pin Control
- Input clocks
- SCIF
- SDHI0
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250116144752.1738574-5-iwamatsu@nigauri.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Bindings expect GPIO hog names to end with 'hog' suffix, so correct it
to fix dtbs_check warning:
r8a77970-eagle-function-expansion.dtb: gpio@27: 'vin0_adv7612_en' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115211755.194219-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add device node for the VSPX instance on R-Car V4M.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115181050.3728275-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add device node for the FCPVX instance on R-Car V4M.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115181050.3728275-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Enable WDT1 watchdog on RZ/G3E SMARC SoM platform.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Alphabetical by label name.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/4f3e057b9a73d7ee7ff073f51bb9a4c30bdd0c84.1736506813.git.geert+renesas@glider.be
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Add device nodes for the VSPX instances on R-Car V3U.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250109125433.2402045-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add device nodes for the FCPVX instances on R-Car V3U.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250109125433.2402045-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Describe the two Marvell 88Q2110/QFN40 PHYs available on the R-Car V4M
Gray Hawk single-board. The two PHYs are wired up on the board by
default.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250107160127.528933-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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When describing the PHYs connected to AVB1 and AVB2, mdio nodes will be
needed to describe the connections, and each mdio node will need to
contain these two properties instead. This will make the #address-cells
and #size-cells described in the base SoC include file redundant and
they will produce warnings, remove them.
In an effort to keep all three AVB nodes style consistent add an mdio
node to AVB0 already described and rename the phy node to better
describe the PHY that is connected to AVB0 before adding more PHYs.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250107160127.528933-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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When CONFIG_ENERGY_MODEL=y:
cpu cpu0: EM: invalid perf. state: -22
When removing the (incorrect) voltages from the Operating Points
Parameters tables, it was assumed they were optional, and unused, when
none of the CPU nodes is tied to a regulator using the "cpu-supply"
property. This assumption turned out to be incorrect, causing the
reported error message.
Fix this by re-adding the (correct) voltages. Note that because all
voltages are identical, all operating points are considered to have the
same efficiency, and the energy model always picks the one with the
highest clock rate.
Reported-by: Renesas Test Team via Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Fixes: fb76b0fae3ca8803 ("arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP table")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/80890bc244670bc3e8d6fc89fb2c3cb23e7025f5.1728377971.git.geert+renesas@glider.be
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