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2018-04-04Merge branch '6c994c504fa2'Bjorn Helgaas
- exclude af3c73473d10 ("PCI: Improve host drivers compile test coverage") from lorenzo/pci/host/misc to avoid build failure * commit '6c994c504fa2': PCI: v3-semi: Remove unnecessary semicolon PCI: rcar: Remove unnecessary semicolon PCI: faraday: Make struct faraday_pci_variant static PCI: kirin: Make struct kirin_pcie_driver static PCI: kirin: Fix missing dependency on PCI_MSI_IRQ_DOMAIN PCI: iproc: Remove dependency on ARM specific struct pci_sys_data PCI: kirin: Remove unnecessary asm/compiler.h include PCI: tegra: Add PCI_MSI_IRQ_DOMAIN kconfig dependency PCI: vmd: Fix malformed Kconfig default
2018-04-04Merge branch 'lorenzo/pci/endpoint'Bjorn Helgaas
* lorenzo/pci/endpoint: misc: pci_endpoint_test: Handle 64-bit BARs properly PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar PCI: endpoint: Handle 64-bit BARs properly PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not set PCI: endpoint: Setting 64-bit/prefetch bit is invalid when IO is set PCI: endpoint: Setting BAR_5 to 64-bits wide is invalid PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar() PCI: endpoint: BAR width should not depend on sizeof dma_addr_t PCI: endpoint: Remove goto labels in pci_epf_create() PCI: endpoint: Fix kernel panic after put_device() PCI: endpoint: Simplify name allocation for EPF device
2018-04-04Merge branch 'lorenzo/pci/dwc-msi'Bjorn Helgaas
* lorenzo/pci/dwc-msi: PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256 PCI: dwc: Remove old MSI IRQs API PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
2018-04-04Merge branch 'lorenzo/pci/dwc'Bjorn Helgaas
* lorenzo/pci/dwc: PCI: histb: Add an optional regulator for PCIe port power control PCI: histb: Fix error path of histb_pcie_host_enable() PCI: qcom: Use regulator bulk api for apq8064 supplies PCI: qcom: Add missing supplies required for msm8996 PCI: designware-ep: Fix typo in error message
2018-04-04Merge branch 'lorenzo/pci/altera'Bjorn Helgaas
* lorenzo/pci/altera: PCI: altera: Fix bool initialization in tlp_read_packet()
2018-04-04Merge branch 'pci/vpd'Bjorn Helgaas
- consolidate VPD code in vpd.c (Bjorn Helgaas) * pci/vpd: PCI/VPD: Move VPD structures to vpd.c PCI/VPD: Move VPD quirks to vpd.c PCI/VPD: Move VPD sysfs code to vpd.c PCI/VPD: Move VPD access code to vpd.c
2018-04-04Merge branch 'pci/virtualization'Bjorn Helgaas
- probe for device reset support during enumeration instead of runtime (Bjorn Helgaas) - add ACS quirk for Ampere (née APM) root ports (Feng Kan) - add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas Vincent-Cross) - protect device restore with device lock (Sinan Kaya) - handle failure of FLR gracefully (Sinan Kaya) - handle CRS (config retry status) after device resets (Sinan Kaya) - skip various config reads for SR-IOV VFs as an optimization (KarimAllah Ahmed) * pci/virtualization: PCI/IOV: Add missing prototypes for powerpc pcibios interfaces PCI/IOV: Use VF0 cached config registers for other VFs PCI/IOV: Skip BAR sizing for VFs PCI/IOV: Skip INTx config reads for VFs PCI: Wait for device to become ready after secondary bus reset PCI: Add a return type for pci_reset_bridge_secondary_bus() PCI: Wait for device to become ready after a power management reset PCI: Rename pci_flr_wait() to pci_dev_wait() and make it generic PCI: Handle FLR failure and allow other reset types PCI: Protect restore with device lock to be consistent PCI: Add function 1 DMA alias quirk for Marvell 88SE9220 PCI: Add ACS quirk for Ampere root ports PCI: Remove redundant probes for device reset support PCI: Probe for device reset support during enumeration Conflicts: include/linux/pci.h
2018-04-04Merge branch 'pci/sparc'Bjorn Helgaas
- support arbitrary PCI host bridge offsets on sparc (Yinghai Lu) - remove System and Video ROM reservations on sparc (Bjorn Helgaas) * pci/sparc: sparc/PCI: Stop reserving System ROM and Video ROM in PCI space sparc/PCI: Support arbitrary host bridge address offset
2018-04-04Merge branch 'pci/resource-mmap'Bjorn Helgaas
- use generic pci_mmap_resource_range() instead of powerpc and xtensa arch-specific versions (David Woodhouse) * pci/resource-mmap: xtensa/PCI: Use generic pci_mmap_resource_range() powerpc/pci: Use generic pci_mmap_resource_range()
2018-04-04Merge branch 'pci/portdrv'Bjorn Helgaas
- move pcieport_if.h to drivers/pci/pcie/ to encapsulate it (Frederick Lawler) - merge pcieport_if.h into portdrv.h (Bjorn Helgaas) - move workaround for BIOS PME issue from portdrv to PCI core (Bjorn Helgaas) - completely disable portdrv with "pcie_ports=compat" (Bjorn Helgaas) - remove portdrv link order dependency (Bjorn Helgaas) - remove support for unused VC portdrv service (Bjorn Helgaas) - simplify portdrv feature permission checking (Bjorn Helgaas) - remove "pcie_hp=nomsi" parameter (use "pci=nomsi" instead) (Bjorn Helgaas) - remove unnecessary "pcie_ports=auto" parameter (Bjorn Helgaas) - use cached AER capability offset (Frederick Lawler) - don't enable DPC if BIOS hasn't granted AER control (Mika Westerberg) - rename pcie-dpc.c to dpc.c (Bjorn Helgaas) * pci/portdrv: PCI/DPC: Rename from pcie-dpc.c to dpc.c PCI/DPC: Do not enable DPC if AER control is not allowed by the BIOS PCI/AER: Use cached AER Capability offset PCI/portdrv: Rename and reverse sense of pcie_ports_auto PCI/portdrv: Encapsulate pcie_ports_auto inside the port driver PCI/portdrv: Remove unnecessary "pcie_ports=auto" parameter PCI/portdrv: Remove "pcie_hp=nomsi" kernel parameter PCI/portdrv: Remove unnecessary include of <linux/pci-aspm.h> PCI/portdrv: Simplify PCIe feature permission checking PCI/portdrv: Remove unused PCIE_PORT_SERVICE_VC PCI/portdrv: Remove pcie_port_bus_type link order dependency PCI/portdrv: Disable port driver in compat mode PCI/PM: Clear PCIe PME Status bit for Root Complex Event Collectors PCI/PM: Clear PCIe PME Status bit in core, not PCIe port driver PCI/PM: Move pcie_clear_root_pme_status() to core PCI/portdrv: Merge pcieport_if.h into portdrv.h PCI/portdrv: Move pcieport_if.h to drivers/pci/pcie/ Conflicts: drivers/pci/pcie/Makefile drivers/pci/pcie/portdrv.h
2018-04-04Merge branch 'pci/msi'Bjorn Helgaas
- don't set up INTx if MSI or MSI-X is enabled to align cris, frv, ia64, and mn10300 with x86 (Bjorn Helgaas) * pci/msi: PCI/MSI: Don't set up INTx if MSI or MSI-X is enabled
2018-04-04Merge branch 'pci/misc'Bjorn Helgaas
- use PCI_EXP_DEVCTL2_COMP_TIMEOUT in rapidio/tsi721 (Bjorn Helgaas) - remove possible NULL pointer dereference in of_pci_bus_find_domain_nr() (Shawn Lin) - report quirk timings with dev_info (Bjorn Helgaas) - report quirks that take longer than 10ms (Bjorn Helgaas) - add and use Altera Vendor ID (Johannes Thumshirn) - tidy Makefiles and comments (Bjorn Helgaas) * pci/misc: PCI: Always define the of_node helpers PCI: Tidy comments PCI: Tidy Makefiles mcb: Add Altera PCI ID to mcb-pci PCI: Add Altera vendor ID PCI: Report quirks that take more than 10ms PCI: Report quirk timings with pci_info() instead of pr_debug() PCI: Fix NULL pointer dereference in of_pci_bus_find_domain_nr() rapidio/tsi721: use PCI_EXP_DEVCTL2_COMP_TIMEOUT macro
2018-04-04Merge branch 'pci/lpc'Bjorn Helgaas
- add support for PCI I/O port space that's neither directly accessible via CPU in/out instructions nor directly mapped into CPU physical memory space (Zhichang Yuan) - add support for HiSilicon Hip06/Hip07 LPC I/O space (Zhichang Yuan, John Garry) * pci/lpc: MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver HISI LPC: Add ACPI support ACPI / scan: Do not enumerate Indirect IO host children ACPI / scan: Rename acpi_is_serial_bus_slave() for more general use HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings of: Add missing I/O range exception for indirect-IO devices PCI: Apply the new generic I/O management on PCI IO hosts PCI: Add fwnode handler as input param of pci_register_io_range() PCI: Remove __weak tag from pci_register_io_range() lib: Add generic PIO mapping method
2018-04-04Merge branch 'pci/hotplug'Bjorn Helgaas
- fix possible cpqphp NULL pointer dereference (Shawn Lin) - rescan more of the hierarchy on ACPI hotplug to fix Thunderbolt/xHCI hotplug (Mika Westerberg) * pci/hotplug: ACPI / hotplug / PCI: Check presence of slot itself in get_slot_status() PCI: cpqphp: Fix possible NULL pointer dereference
2018-04-04Merge branch 'pci/enumeration'Bjorn Helgaas
- add decoding for 16 GT/s link speed (Jay Fang) - add interfaces to get max link speed and width (Tal Gilboa) - add pcie_bandwidth_capable() to compute max supported link bandwidth (Tal Gilboa) - add pcie_bandwidth_available() to compute bandwidth available to device (Tal Gilboa) - add pcie_print_link_status() to log link speed and whether it's limited (Tal Gilboa) - use PCI core interfaces to report when device performance may be limited by its slot instead of doing it in each driver (Tal Gilboa) * pci/enumeration: fm10k: Report PCIe link properties with pcie_print_link_status() net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth net/mlx5: Report PCIe link properties with pcie_print_link_status() net/mlx4_core: Report PCIe link properties with pcie_print_link_status() PCI: Add pcie_print_link_status() to log link speed and whether it's limited PCI: Add pcie_bandwidth_available() to compute bandwidth available to device PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth PCI: Add pcie_get_width_cap() to find max supported link width PCI: Add pcie_get_speed_cap() to find max supported link speed PCI: Add decoding for 16 GT/s link speed
2018-04-04Merge branch 'pci/deprecate-get-bus-and-slot'Bjorn Helgaas
- remove last user of pci_get_bus_and_slot() and the function itself (Sinan Kaya) * pci/deprecate-get-bus-and-slot: PCI: Remove pci_get_bus_and_slot() function drm/i915: Deprecate pci_get_bus_and_slot()
2018-04-04Merge branch 'pci/aspm'Bjorn Helgaas
- skip ASPM common clock warning if BIOS already configured it (Sinan Kaya) - fix ASPM Coverity warning about threshold_ns (Gustavo A. R. Silva) * pci/aspm: PCI/ASPM: Don't warn if already in common clock mode PCI/ASPM: Declare threshold_ns as u32, not u64
2018-04-04Merge branch 'pci/aer'Bjorn Helgaas
- move pci_uevent_ers() out of pci.h (Michael Ellerman) * pci/aer: PCI/AER: Move pci_uevent_ers() out of pci.h
2018-04-04MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driverJohn Garry
Add John Garry as maintainer for drivers/bus/hisi_lpc.c, the HiSilicon LPC driver. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-04HISI LPC: Add ACPI supportJohn Garry
Based on the previous patches, this patch supports the LPC host on Hip06/Hip07 for ACPI FW. It is the responsibility of the LPC host driver to enumerate the child devices, as the ACPI scan code will not enumerate children of "indirect IO" hosts. The ACPI table for the LPC host controller and the child devices is in the following format: Device (LPC0) { Name (_HID, "HISI0191") // HiSi LPC Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) }) } Device (LPC0.IPMI) { Name (_HID, "IPI0001") Name (LORS, ResourceTemplate() { QWordIO ( ResourceConsumer, MinNotFixed, // _MIF MaxNotFixed, // _MAF PosDecode, EntireRange, 0x0, // _GRA 0xe4, // _MIN 0x3fff, // _MAX 0x0, // _TRA 0x04, // _LEN , , BTIO ) }) Since the IO resources of the child devices need to be translated from LPC bus addresses to logical PIO addresses, and we shouldn't modify the resources of the devices generated in the FW scan, a per-child MFD is created as a substitute. The MFD IO resources will be the translated bus addresses of the ACPI child. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2018-04-04ACPI / scan: Do not enumerate Indirect IO host childrenJohn Garry
Through the logical PIO framework, systems which otherwise have no IO space access to legacy ISA/LPC devices may access these devices through so-called "indirect IO" method. In this, IO space accesses for non-PCI hosts are redirected to a host LLDD to manually generate the IO space (bus) accesses. Hosts are able to register a region in logical PIO space to map to its bus address range. Indirect IO child devices have an associated host-specific bus address. Special translation is required to map between a logical PIO address for a device and its host bus address. Since in the ACPI tables the child device IO resources would be the host-specific values, it is required the ACPI scan code should not enumerate these devices, and that this should be the responsibility of the host driver so that it can "fixup" the resources so that they map to the appropriate logical PIO addresses. To avoid enumerating these child devices, add a check from acpi_device_enumeration_by_parent() as to whether the parent for a device is a member of a known list of "indirect IO" hosts. For now, the HiSilicon LPC host controller ID is added. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-04-04ACPI / scan: Rename acpi_is_serial_bus_slave() for more general useJohn Garry
Currently the ACPI scan has special handling for serial bus slaves, in that it makes it the responsibility of the slave device's parent to enumerate the device. To support other types of slave devices which require the same special handling but where the bus is not strictly a serial bus, such as devices on the HiSilicon LPC controller bus, rename acpi_is_serial_bus_slave() to acpi_device_enumeration_by_parent(), so that the name can fit the wider purpose. Also rename the associated device flag acpi_device_flags.serial_bus_slave to .enumeration_by_parent. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-04-04HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindingsZhichang Yuan
The low-pin-count (LPC) interface of Hip06/Hip07 accesses I/O port space of peripherals. Implement the LPC host controller driver which performs the I/O operations on the underlying hardware. We don't want to touch existing drivers such as ipmi-bt, so this driver applies the indirect-IO introduced in the previous patch after registering an indirect-IO node to the indirect-IO devices list which will be searched by the I/O accessors to retrieve the host-local I/O port. The driver config is set as a bool instead of a tristate. The reason here is that, by the very nature of the driver providing a logical PIO range, it does not make sense to have this driver as a loadable module. Another more specific reason is that the Huawei D03 board which includes Hip06 SoC requires the LPC bus for UART console, so should be built in. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Zou Rongrong <zourongrong@huawei.com> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org> # dts part
2018-04-04of: Add missing I/O range exception for indirect-IO devicesZhichang Yuan
There are some special ISA/LPC devices that work on a specific I/O range where it is not correct to specify a 'ranges' property in the DTS parent node as CPU addresses translated from DTS node are only for memory space on some architectures, such as ARM64. Without the parent 'ranges' property, of_translate_address() returns an error. Here we add special handling for this case. During the OF address translation, some checking will be performed to identify whether the device node is registered as indirect-IO. If it is, the I/O translation will be done in a different way from that one of PCI MMIO. In this way, the I/O 'reg' property of the special ISA/LPC devices will be parsed correctly. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> # earlier draft Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
2018-04-04PCI: Apply the new generic I/O management on PCI IO hostsZhichang Yuan
After introducing the new generic I/O space management (Logical PIO), the original PCI MMIO relevant helpers need to be updated based on the new interfaces defined in logical PIO. Adapt the corresponding code to match the changes introduced by logical PIO. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> # earlier draft Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2018-04-04PCI: Add fwnode handler as input param of pci_register_io_range()Gabriele Paoloni
In preparation for having the PCI MMIO helpers use the new generic I/O space management (logical PIO) we need to add the fwnode handler as an extra input parameter. Changes the signature of pci_register_io_range() and its callers as needed. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
2018-04-04PCI: Remove __weak tag from pci_register_io_range()Gabriele Paoloni
pci_register_io_range() has only one definition, so there is no need for the __weak attribute. Remove it. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2018-04-03fm10k: Report PCIe link properties with pcie_print_link_status()Bjorn Helgaas
Previously the driver used pcie_get_minimum_link() to warn when the NIC is in a slot that can't supply as much bandwidth as the NIC could use. pcie_get_minimum_link() can be misleading because it finds the slowest link and the narrowest link (which may be different links) without considering the total bandwidth of each link. For a path with a 16 GT/s x1 link and a 2.5 GT/s x16 link, it returns 2.5 GT/s x1, which corresponds to 250 MB/s of bandwidth, not the true available bandwidth of about 1969 MB/s for a 16 GT/s x1 link. Use pcie_print_link_status() to report PCIe link speed and possible limitations instead of implementing this in the driver itself. This finds the slowest link in the path to the device by computing the total bandwidth of each link and compares that with the capabilities of the device. Note that the driver previously used dev_warn() to suggest using a different slot, but pcie_print_link_status() uses dev_info() because if the platform has no faster slot available, the user can't do anything about the warning and may not want to be bothered with it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jacob Keller <jacob.e.keller@intel.com>
2018-04-03net/mlx5e: Use pcie_bandwidth_available() to compute bandwidthTal Gilboa
Use the new pci_bandwidth_available() function to calculate maximum available bandwidth through the PCI chain instead of computing it ourselves with mlx5e_get_pci_bw(). This is used to detect when the device is capable of more bandwidth than is available in the current slot. The driver may adjust compression settings accordingly. Note that pci_bandwidth_available() accounts for PCIe encoding overhead, so it is more accurate than mlx5e_get_pci_bw() was. Signed-off-by: Tal Gilboa <talgi@mellanox.com> [bhelgaas: remove mlx5e_get_pci_bw() wrapper altogether] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
2018-04-03net/mlx5: Report PCIe link properties with pcie_print_link_status()Tal Gilboa
Use pcie_print_link_status() to report PCIe link speed and possible limitations. Signed-off-by: Tal Gilboa <talgi@mellanox.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
2018-04-03net/mlx4_core: Report PCIe link properties with pcie_print_link_status()Tal Gilboa
Use pcie_print_link_status() to report PCIe link speed and possible limitations instead of implementing this in the driver itself. Signed-off-by: Tal Gilboa <talgi@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-03PCI: Add pcie_print_link_status() to log link speed and whether it's limitedTal Gilboa
Add pcie_print_link_status(). This logs the current settings of the link (speed, width, and total available bandwidth). If the device is capable of more bandwidth but is limited by a slower upstream link, we include information about the link that limits the device's performance. The user may be able to move the device to a different slot for better performance. This provides a unified method for all PCI devices to report status and issues, instead of each device reporting in a different way, using different code. Signed-off-by: Tal Gilboa <talgi@mellanox.com> [bhelgaas: changelog, reword log messages, print device capabilities when not limited, print bandwidth in Gb/s] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-03PCI: Add pcie_bandwidth_available() to compute bandwidth available to deviceTal Gilboa
Add pcie_bandwidth_available() to compute the bandwidth available to a device. This may be limited by the device itself or by a slower upstream link leading to the device. The available bandwidth at each link along the path is computed as: link_width * link_speed * (1 - encoding_overhead) 2.5 and 5.0 GT/s links use 8b/10b encoding, which reduces the raw bandwidth available by 20%; 8.0 GT/s and faster links use 128b/130b encoding, which reduces it by about 1.5%. The result is in Mb/s, i.e., megabits/second, of raw bandwidth. Also return the device with the slowest link and the speed and width of that link. Signed-off-by: Tal Gilboa <talgi@mellanox.com> [bhelgaas: changelog, leave pcie_get_minimum_link() alone for now, return bw directly, use pci_upstream_bridge(), check "next_bw <= bw" to find uppermost limiting device, return speed/width of the limiting device] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-04-03misc: pci_endpoint_test: Handle 64-bit BARs properlyNiklas Cassel
A 64-bit BAR consists of a BAR pair, where the second BAR has the upper bits, so we cannot simply call pci_ioremap_bar() on every single BAR index. The second BAR in a BAR pair will not have the IORESOURCE_MEM resource flag set. Only call ioremap on BARs that have the IORESOURCE_MEM resource flag set. pci 0000:01:00.0: BAR 4: assigned [mem 0xc0300000-0xc031ffff 64bit] pci 0000:01:00.0: BAR 2: assigned [mem 0xc0320000-0xc03203ff 64bit] pci 0000:01:00.0: BAR 0: assigned [mem 0xc0320400-0xc03204ff 64bit] pci-endpoint-test 0000:01:00.0: can't ioremap BAR 1: [??? 0x00000000 flags 0x0] pci-endpoint-test 0000:01:00.0: failed to read BAR1 pci-endpoint-test 0000:01:00.0: can't ioremap BAR 3: [??? 0x00000000 flags 0x0] pci-endpoint-test 0000:01:00.0: failed to read BAR3 pci-endpoint-test 0000:01:00.0: can't ioremap BAR 5: [??? 0x00000000 flags 0x0] pci-endpoint-test 0000:01:00.0: failed to read BAR5 Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properlyNiklas Cassel
Since a 64-bit BAR consists of a BAR pair, we need to write to both BARs in the BAR pair to clear the BAR properly. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearingNiklas Cassel
Since a 64-bit BAR consists of a BAR pair, and since there is no BAR after BAR_5, BAR_5 cannot be 64-bits wide. This sanity check is done in pci_epc_clear_bar(), so that we don't need to do this sanity check in all epc->ops->clear_bar() implementations. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct ↵Niklas Cassel
*epf_bar Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar. This is needed so that epc->ops->clear_bar() can clear the BAR pair, if the BAR is 64-bits wide. This also makes it possible for pci_epc_clear_bar() to sanity check the flags. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2018-04-03PCI: endpoint: Handle 64-bit BARs properlyNiklas Cassel
If a 64-bit BAR was set-up, we need to skip a BAR, since a 64-bit BAR consists of a BAR pair. We need to check what BAR width the epc->ops->set_bar() specific implementation actually did set-up, since some drivers, like the Cadence EP controller, sometimes sets up a 64-bit BAR, even though a 32-bit BAR was requested. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-upNiklas Cassel
cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means that a 64-bit BAR can be set-up, even when the flag PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set. If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64, so that the calling function can know what BAR width that was actually set-up. I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to fix, since there might be a reason why this flag is ignored. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Alan Douglas <adouglas@cadence.com>
2018-04-03PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properlyNiklas Cassel
Since a 64-bit BAR consists of a BAR pair, we need to write to both BARs in the BAR pair to setup the BAR properly. Link: https://lkml.kernel.org/r/20180328115018.31921-7-niklas.cassel@axis.com Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> [lorenzo.pieralisi@arm.com: updated code according to review] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2018-04-03PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not setNiklas Cassel
Setting a BAR size > 4 GB is invalid if PCI_BASE_ADDRESS_MEM_TYPE_64 flag is not set. This sanity check is done in pci_epc_set_bar(), so that we don't need to do this sanity check in all epc->ops->set_bar() implementations. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: endpoint: Setting 64-bit/prefetch bit is invalid when IO is setNiklas Cassel
If flag PCI_BASE_ADDRESS_SPACE_IO is set, also having any PCI_BASE_ADDRESS_MEM_* bit set is invalid. This sanity check is done in pci_epc_set_bar(), so that we don't need to do this sanity check in all epc->ops->set_bar() implementations. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: endpoint: Setting BAR_5 to 64-bits wide is invalidNiklas Cassel
Since a 64-bit BAR consists of a BAR pair, and since there is no BAR after BAR_5, BAR_5 cannot be 64-bits wide. This sanity check is done in pci_epc_set_bar(), so that we don't need to do this sanity check in all epc->ops->set_bar() implementations. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar()Niklas Cassel
Add barno and flags to struct epf_bar. That way we can simplify epc->ops->set_bar()/pci_epc_set_bar() by passing a struct *epf_bar instead of a whole lot of arguments. This is needed so that epc->ops->set_bar() implementations can modify BAR flags. Will be utilized in a succeeding patch. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03PCI: endpoint: BAR width should not depend on sizeof dma_addr_tNiklas Cassel
If a BAR supports 64-bit width or not depends on the hardware, and should thus not depend on sizeof(dma_addr_t). If a certain hardware doesn't support 64-bit BARs, its epc->ops->set_bar() implementation should return -EINVAL when PCI_BASE_ADDRESS_MEM_TYPE_64 is set. We can't change pci_epc_set_bar() to only set PCI_BASE_ADDRESS_MEM_TYPE_64 based on size, since if the user, for some reason, wants to configure a BAR with a 64-bit width, even though the BAR size is less than 4 GB, he should be able to do that. However, since pci-epf-test is simply a test and not an API, we can set PCI_BASE_ADDRESS_MEM_TYPE_64 in pci-epf-test itself only based on size. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-03-31PCI/DPC: Rename from pcie-dpc.c to dpc.cBjorn Helgaas
Rename pcie-dpc.c to dpc.c. The path "drivers/pci/pcie/pcie-dpc.c" has more occurrences of "pci" than necessary. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-03-31PCI/IOV: Add missing prototypes for powerpc pcibios interfacesMathieu Malaterre
Add missing prototypes for: resource_size_t pcibios_default_alignment(void); int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); int pcibios_sriov_disable(struct pci_dev *pdev); This fixes the following warnings treated as errors when using W=1: arch/powerpc/kernel/pci-common.c:236:17: error: no previous prototype for ‘pcibios_default_alignment’ [-Werror=missing-prototypes] arch/powerpc/kernel/pci-common.c:253:5: error: no previous prototype for ‘pcibios_sriov_enable’ [-Werror=missing-prototypes] arch/powerpc/kernel/pci-common.c:261:5: error: no previous prototype for ‘pcibios_sriov_disable’ [-Werror=missing-prototypes] Also, commit 978d2d683123 ("PCI: Add pcibios_iov_resource_alignment() interface") added a new function but the prototype was located in the main header instead of the CONFIG_PCI_IOV specific section. Move this function next to the newly added ones. Signed-off-by: Mathieu Malaterre <malat@debian.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2018-03-31PCI/IOV: Use VF0 cached config registers for other VFsKarimAllah Ahmed
Cache some config data from VF0 and use it for all other VFs instead of reading it from the config space of each VF. We assume these items are the same across all associated VFs: Revision ID Class Code Subsystem Vendor ID Subsystem ID This is an optimization when enabling SR-IOV on a device with many VFs. Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> [bhelgaas: changelog, simplify comments, remove unused "device", test CONFIG_PCI_IOV instead of CONFIG_PCI_ATS, rename functions] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2018-03-30PCI: Always define the of_node helpersBjørn Mork
Simply move these inline functions outside the ifdef instead of duplicating them as stubs in the !OF case. The struct device of_node field does not depend on OF. This also fixes the missing stubbed pci_bus_to_OF_node(). Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2018-03-30PCI/DPC: Do not enable DPC if AER control is not allowed by the BIOSMika Westerberg
Commit eed85ff4c0da ("PCI/DPC: Enable DPC only if AER is available") made DPC control dependent whether AER is enabled in the OS. However, it does not take into account situations where BIOS has not given OS control of AER: acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] acpi PNP0A08:00: _OSC: platform does not support [AER] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME PCIeCapability] I think here it is better not to enable DPC even if the capability is available because then it would be against what "Determination of DPC Control" note in PCIe 4.0 sec 6.1.10 recommends. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-10 21:22:53 +0000