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2019-07-12Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas
- Move qcom driver to bulk clock API (Bjorn Andersson) - Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson) - Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel) * remotes/lorenzo/pci/qcom: PCI: qcom: Ensure that PERST is asserted for at least 100 ms PCI: qcom: Add QCS404 PCIe controller support dt-bindings: PCI: qcom: Add QCS404 to the binding PCI: qcom: Use clk bulk API for 2.4.0 controllers
2019-07-12Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas
- Unify mobiveil register accessors (Hou Zhiqiang) - Remove MSI_FLAG_MULTI_PCI_MSI since mobiveil hardware doesn't support Multiple MSI (Hou Zhiqiang) - Program outbound windows with base address from DT instead of assuming zero (Hou Zhiqiang) - Skip "safe" list traversal when it's unnecessary (Hou Zhiqiang) - Initialize WIN_NUM_0 explicitly for CFG outbound transactions (Hou Zhiqiang) - Use WIN_NUM_0 for MEM inbound transactions (Hou Zhiqiang) - Fix up mobiveil Class Code to PCI_CLASS_BRIDGE_PCI (Hou Zhiqiang) - Wait for link-up before enumerating devices, not while initializing host (Hou Zhiqiang) - Move IRQ chained handler setup out of DT code (Hou Zhiqiang) - Set primary/secondary/subordinate bus numbers (Hou Zhiqiang) - Fix "valid device" check to allow root bus device 0 to be multi-function (Hou Zhiqiang) - Make DT "gpio_slave" and "apb_csr" properties optional (Hou Zhiqiang) - Refactor MEM/IO outbound window initialization (Hou Zhiqiang) - Fix validity check for inbound/outbound window programming (Hou Zhiqiang) - Initialize and preserve window control bits (Hou Zhiqiang) - Fix 64-bit outbound window setup (both CPU and PCI addresses) (Hou Zhiqiang) - Move IO port setup to host init (Hou Zhiqiang) - Fix infinite loop in INTx ISR (Hou Zhiqiang) - Fix INTx interrupt clearing to avoid missed interrupts (Hou Zhiqiang) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr() PCI: mobiveil: Fix infinite-loop in the INTx handling function PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setup PCI: mobiveil: Clear the control fields before updating it PCI: mobiveil: Add configured inbound windows counter PCI: mobiveil: Fix the valid check for inbound and outbound windows PCI: mobiveil: Clean-up program_{ib/ob}_windows() PCI: mobiveil: Remove an unnecessary return value check PCI: mobiveil: Fix error return values PCI: mobiveil: Refactor the MEM/IO outbound window initialization PCI: mobiveil: Make some register updates more readable PCI: mobiveil: Reformat the code for readability dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device() PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers PCI: mobiveil: Move IRQ chained handler setup out of DT parse PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() PCI: mobiveil: Fix the Class Code field PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window PCI: mobiveil: Update the resource list traversal function PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI PCI: mobiveil: Unify register accessors
2019-07-12Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas
- Fix Hyper-V use-after-free in eject path (Dexuan Cui) * remotes/lorenzo/pci/hv: PCI: hv: Fix a use-after-free bug in hv_eject_device_work()
2019-07-12Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas
- Add dwc API support to de-initialize host (Vidya Sagar) - Clean up dwc DBI,ATU read and write APIs (Vidya Sagar) - Export dwc APIs to support .remove() so drivers can be modular (Vidya Sagar) - Simplify imx6 Kconfig dependencies (Leonard Crestez) - Fix dra7xx build error when !CONFIG_GPIOLIB (YueHaibing) * remotes/lorenzo/pci/dwc: PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB PCI: imx6: Simplify Kconfig depends on PCI: dwc: Export APIs to support .remove() implementation PCI: dwc: Cleanup DBI,ATU read and write APIs PCI: dwc: Add API support to de-initialize host
2019-07-12Merge branch 'remotes/lorenzo/pci/armada'Bjorn Helgaas
- Add Armada8k PHYs support (Miquel Raynal) * remotes/lorenzo/pci/armada: PCI: armada8k: Add PHYs support
2019-07-12Merge branch 'remotes/lorenzo/pci/altera'Bjorn Helgaas
- Allow building Altera host bridge driver as a module (Ley Foon Tan) - Fix Altera Stratix 10 Type 1 to Type 0 config access conversion (Ley Foon Tan) * remotes/lorenzo/pci/altera: PCI: altera: Fix configuration type based on secondary number PCI: altera-msi: Allow building as module PCI: altera: Allow building as module
2019-07-12Merge branch 'pci/virtualization'Bjorn Helgaas
- Fix problem with caching VF config space size (Alex Williamson) * pci/virtualization: PCI/IOV: Assume SR-IOV VFs support extended config space. Revert "PCI/IOV: Use VF0 cached config space size for other VFs"
2019-07-12Merge branch 'pci/resource'Bjorn Helgaas
- Evaluate ACPI "PCI Boot Configuration"_DSM (Benjamin Herrenschmidt) - Don't auto-realloc if we're preserving firmware config (Benjamin Herrenschmidt) - Allow arm64 to reallocate resources if necessary (Benjamin Herrenschmidt) - Preserve firmware config on arm64 when desired (Benjamin Herrenschmidt) - Simplify resource distribution to hotplug bridges (Nicholas Johnson) * pci/resource: PCI: Skip resource distribution when no hotplug bridges PCI: Simplify pci_bus_distribute_available_resources() arm64: PCI: Preserve firmware configuration when desired arm64: PCI: Allow resource reallocation if necessary PCI: Don't auto-realloc if we're preserving firmware config PCI/ACPI: Evaluate PCI Boot Configuration _DSM
2019-07-12Merge branch 'pci/peer-to-peer'Bjorn Helgaas
- Prevent drivers that use dma_virt_ops from using peer-to-peer DMA (Logan Gunthorpe) * pci/peer-to-peer: PCI/P2PDMA: Fix missing check for dma_virt_ops
2019-07-12Merge branch 'pci/misc'Bjorn Helgaas
- Generalize multi-function power dependency device links (Abhishek Sahu) - Add NVIDIA GPU multi-function power dependencies (Abhishek Sahu) - Optimize /proc/bus/pci/devices by using seq_puts() instead of seq_printf() (Markus Elfring) - Enable NVIDIA HDA controllers if BIOS didn't (Lukas Wunner) * pci/misc: PCI: Enable NVIDIA HDA controllers PCI: Use seq_puts() instead of seq_printf() in show_device() PCI: Add NVIDIA GPU multi-function power dependencies PCI: Generalize multi-function power dependency device links
2019-07-12Merge branch 'pci/enumeration'Bjorn Helgaas
- If user prevents VF probing, return error instead of pretending a driver has claimed the VF (Alex Williamson) - Always allow probing with driver_override (Alex Williamson) - Decode PCIe 32 GT/s link speed (Gustavo Pimentel) - Ignore lockdep for sysfs remove to avoid lockdep false positive (Marek Vasut) * pci/enumeration: PCI: sysfs: Ignore lockdep for remove attribute PCI: Decode PCIe 32 GT/s link speed PCI: Always allow probing with driver_override PCI: Return error if cannot probe VF
2019-07-12Merge branch 'pci/docs'Bjorn Helgaas
- Convert docs to reST (Changbin Du) - Convert PM docs to reST (Mauro Carvalho Chehab) * pci/docs: docs: power: convert docs to ReST and rename to *.rst Documentation: PCI: convert endpoint/pci-test-howto.txt to reST Documentation: PCI: convert endpoint/pci-test-function.txt to reST Documentation: PCI: convert endpoint/pci-endpoint-cfs.txt to reST Documentation: PCI: convert endpoint/pci-endpoint.txt to reST Documentation: PCI: convert pcieaer-howto.txt to reST Documentation: PCI: convert pci-error-recovery.txt to reST Documentation: PCI: convert acpi-info.txt to reST Documentation: PCI: convert MSI-HOWTO.txt to reST Documentation: PCI: convert pci-iov-howto.txt to reST Documentation: PCI: convert PCIEBUS-HOWTO.txt to reST Documentation: PCI: convert pci.txt to reST Documentation: add Linux PCI to Sphinx TOC tree
2019-07-11PCI: Enable NVIDIA HDA controllersLukas Wunner
Many NVIDIA GPUs can be configured as either a single-function video device or a multi-function device with video at function 0 and an HDA audio controller at function 1. The HDA controller can be enabled or disabled by a bit in the function 0 config space. Some BIOSes leave the HDA disabled, which means the HDMI connector from the NVIDIA GPU may not work. Sometimes the BIOS enables the HDA if an HDMI cable is connected at boot time, but that doesn't handle hotplug cases. Enable the HDA controller on device enumeration and resume and re-read the header type, which tells us whether the GPU is a multi-function device. This quirk is limited to NVIDIA PCI devices with the VGA Controller device class. This is expected to correspond to product configurations where the NVIDIA GPU has connectors attached. Other products where the device class is 3D Controller are expected to correspond to configurations where the NVIDIA GPU is dedicated (dGPU) and has no connectors. See original post (URL below) for more details. This commit takes inspiration from an earlier patch by Daniel Drake. Link: https://lore.kernel.org/r/20190708051744.24039-1-drake@endlessm.com v2 Link: https://lore.kernel.org/r/20190613063514.15317-1-drake@endlessm.com v1 Link: https://devtalk.nvidia.com/default/topic/1024022 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75985 Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Daniel Drake <drake@endlessm.com> [bhelgaas: commit log, log message, return early if already enabled] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Aaron Plattner <aplattner@nvidia.com> Cc: Peter Wu <peter@lekensteyn.nl> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Cc: Karol Herbst <kherbst@redhat.com> Cc: Maik Freudenberg <hhfeuer@gmx.de>
2019-07-09PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIBYueHaibing
If CONFIG_GPIOLIB is not selected the compilation results in the following build errors: drivers/pci/controller/dwc/pci-dra7xx.c: In function dra7xx_pcie_probe: drivers/pci/controller/dwc/pci-dra7xx.c:777:10: error: implicit declaration of function devm_gpiod_get_optional; did you mean devm_regulator_get_optional? [-Werror=implicit-function-declaration] reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); drivers/pci/controller/dwc/pci-dra7xx.c:778:45: error: ‘GPIOD_OUT_HIGH’ undeclared (first use in this function); did you mean ‘GPIOF_INIT_HIGH’? reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); ^~~~~~~~~~~~~~ GPIOF_INIT_HIGH Fix them by including the appropriate header file. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-07-08PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr()Hou Zhiqiang
The current INTx handling function clears all interrupts after handling the first pending; this can potentially cause missing INTx detection. Fix the code to clear only the handled INTx IRQ. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
2019-07-08PCI: mobiveil: Fix infinite-loop in the INTx handling functionHou Zhiqiang
In the loop handling INTx interrupts in mobiveil_pcie_isr(), there is no code to update the loop control variable, which is causing an infinite loop. Fix the code by reading the interrupt status registers inside the loop. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
2019-07-08PCI: mobiveil: Move PCIe PIO enablement out of inbound window routineHou Zhiqiang
Move the PCIe PIO master enablement to function mobiveil_host_init(). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound windowHou Zhiqiang
Current code erroneously sets-up the lower 32-bit PCI base address in the inbound window, which results in inbound transactions not working in 64-bit platforms. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound windowHou Zhiqiang
Current code erroneously sets-up only the lower 32-bit CPU base address in the outbound window, which results in outbound transactions not working in 64-bit platforms. Fix it. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setupHou Zhiqiang
The lower 10 bits of window size field are hardcoded to zero in HW so they can't really be changed but the lower 10-bit of PAB_AXI_AMAP_CTRL register are used for control fields, so while programming inbound and outbout windows decoding we should mask out the lower 10-bit of window size to prevent overriding the control bits. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Clear the control fields before updating itHou Zhiqiang
While programming the inbound and outbound windows in program_{ib/ob}_windows() we shoud clear the control fields in the registers before programming it with a new value to prevent stale bits from older configuration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Add configured inbound windows counterHou Zhiqiang
Current code only keeps track of the number of outbound windows configured but it does not for inbound windows. Add a counter to keep track of initialized inbound windows. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Fix the valid check for inbound and outbound windowsHou Zhiqiang
In program_ib/ob_windows() check the window index from the function parameter instead of the total number of initialized windows to determine if the specified window is valid. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Clean-up program_{ib/ob}_windows()Hou Zhiqiang
In function program_ob_windows(), remove the redundant read operations to registers PAB_AXI_AMAP_AXI_WIN and PAB_AXI_AMAP_PEX_WIN_H, and remove the useless definition of 'value'. Rename the parameter 'config_io_bit' to 'type' and then remove the definition of 'type'. In function program_ib_windows(), remove the definitions of 'pio_ctrl_val' and 'amap_ctrl_dw' and reduce to only one variable 'value' to keep the temporary value read from registers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Remove an unnecessary return value checkHou Zhiqiang
The memory for the host controller private structure (struct mobiveil_pcie) is allocated together with the pci_host_bridge structure in function devm_pci_alloc_host_bridge(), so it is unnecessary to check the return value when get the private structure pointer. Remove the useless check. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Fix error return valuesHou Zhiqiang
Some error return values in the host controller driver are either unconventional or plain wrong. Update them all with the expected return values. Signed-off-by: Hou Zhiqiang <Zhinqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Refactor the MEM/IO outbound window initializationHou Zhiqiang
Move the resource type check into an if/else block and only set-up the outbound window for MEM and IO resource. No functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
2019-07-08PCI: mobiveil: Make some register updates more readableHou Zhiqiang
To make some register updates more readable use a temporary value to hold the register value and carry out the update. Change the register update sequence to: - Read out the original value from the target register - Update the value - Program the updated value back to the register Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
2019-07-08PCI: mobiveil: Reformat the code for readabilityHou Zhiqiang
Reformat the code to make it more readable. No functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
2019-07-08dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optionalHou Zhiqiang
Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave" is not used in current code, and "apb_csr" is not used by some platforms. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device()Hou Zhiqiang
Current check for devfn number in mobiveil_pci_valid_device() is wrong in that it flags as invalid functions present in PCI device 0 in the root bus while it is perfectly valid to access all functions in PCI device 0 in the root bus. Update the check in mobiveil_pci_valid_device() to fix the issue. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
2019-07-08PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbersHou Zhiqiang
The reset value of Primary, Secondary and Subordinate bus numbers is zero which is a broken setup. Program a sensible default value for Primary/Secondary/Subordinate bus numbers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Move IRQ chained handler setup out of DT parseHou Zhiqiang
The irq_set_chained_handler_and_data() call is not dependent on device tree firmware so it should be moved out of the DT parsing function for clarity. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [lorenzo.pieralisi@arm.com: rewritten commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()Hou Zhiqiang
The host initializing sequence does not depend on the PCIe link being up, so move the link up check right before the code scanning the root bus for enumeration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Fix the Class Code fieldHou Zhiqiang
Fix up the Class Code field in PCI configuration space and set it to PCI_CLASS_BRIDGE_PCI. Move the Class Code fixup to function mobiveil_host_init() where it belongs. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Use the 1st inbound window for MEM inbound transactionsHou Zhiqiang
The inbound and outbound windows have completely separate control registers sets in the host controller MMIO space. Windows control register are accessed through an MMIO base address and an offset that depends on the window index. Since inbound and outbound windows control registers are completely separate there is no real need to use different window indexes in the inbound/outbound windows initialization routines to prevent clashing. To fix this inconsistency, change the MEM inbound window index to 0, mirroring the outbound window set-up. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [lorenzo.pieralisi@arm.com: update commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound windowHou Zhiqiang
As the .map_bus() use the WIN_NUM_0 for CFG transactions, it is appropriate to pass WIN_NUM_0 explicitly when initializing the CFG outbound window rather than implicitly relying on the ob_wins_configure counter. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Update the resource list traversal functionHou Zhiqiang
Code that executes the resource list traversal does not need to delete any node therefore using the *_safe() API version is useless. Replace function resource_list_for_each_entry_safe() with the resource_list_for_each_entry() counterpart. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Fix PCI base address in MEM/IO outbound windowsHou Zhiqiang
The outbound memory windows PCI base addresses should be taken from the 'ranges' property of DT node to setup MEM/IO outbound windows decoding correctly instead of being hardcoded to zero. Update the code to retrieve the PCI base address for each range and use it to program the outbound windows address decoders Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-08PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSIHou Zhiqiang
The Mobiveil internal MSI controller requires separate target addresses, one per MSI vector; this is clearly incompatible with the Multiple MSI feature, which requires the same target address for all vectors requested by an endpoint (ie the Message Address field in the MSI Capability structure), so the multi MSI feature is clearly not supported by the host controller driver. Remove the flag MSI_FLAG_MULTI_PCI_MSI and with it multi MSI support, fixing the misconfiguration. Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
2019-07-08PCI: mobiveil: Unify register accessorsHou Zhiqiang
It is confusing to have two sets of functions to read/write registers, some with csr_readl()/csr_writel(), while others with read_paged_register()/write_paged_register(). In the register space the lower 3KB of 4KB PCIe configure space can be accessed directly and higher 1KB through a simple paging mechanism. Unify the register accessors in csr_readl() and csr_writel() by comparing the register offset with page access boundary 3KB in the accessor internal so that the paging mechanism is hidden behind the csr_read()/write() common function calls. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-07-05PCI: imx6: Simplify Kconfig depends onLeonard Crestez
The imx6 driver can be used on imx6sx without enabling support for imx6q or imx7d but the "depends on" condition doesn't allow that. Instead of making the condition even longer just make it depend on "ARCH_MXC || COMPILE_TEST" instead. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Lucas Stach <l.stach@pengutronix.de>
2019-07-05PCI: hv: Fix a use-after-free bug in hv_eject_device_work()Dexuan Cui
Fix a use-after-free in hv_eject_device_work(). Fixes: 05f151a73ec2 ("PCI: hv: Fix a memory leak in hv_eject_device_work()") Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Cc: stable@vger.kernel.org
2019-07-03PCI/IOV: Assume SR-IOV VFs support extended config space.Alex Williamson
The SR-IOV specification requires both PFs and VFs to implement a PCIe capability. Generally this is sufficient to assume extended config space is present, but we generally also perform additional tests to make sure the extended config space is reachable and not simply an alias of standard config space. For a VF to exist extended config space must be accessible on the PF, therefore we can also assume it to be accessible on the VF. This enables a micro performance optimization previously implemented in commit 975bb8b4dc93 ("PCI/IOV: Use VF0 cached config space size for other VFs") to speed up probing of VFs. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Cc: KarimAllah Ahmed <karahmed@amazon.de> Cc: Hao Zheng <yinhe@linux.alibaba.com>
2019-07-03Revert "PCI/IOV: Use VF0 cached config space size for other VFs"Alex Williamson
Revert 975bb8b4dc93 ("PCI/IOV: Use VF0 cached config space size for other VFs"), which attempted to cache the config space size from the first VF to re-use for subsequent VFs. The cached value was determined prior to discovering the PCIe capability on the VF, which resulted in the first VF reporting the correct config space size (4K), as it has a special case through pci_cfg_space_size(), while all the other VFs only reported 256 bytes. As this was only a performance optimization, we're better off without it. Fixes: 975bb8b4dc93 ("PCI/IOV: Use VF0 cached config space size for other VFs") Link: https://lore.kernel.org/r/156046663197.29869.3633634445109057665.stgit@gimli.home Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: KarimAllah Ahmed <karahmed@amazon.de> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Cc: Hao Zheng <yinhe@linux.alibaba.com>
2019-07-02PCI: Use seq_puts() instead of seq_printf() in show_device()Markus Elfring
The driver name in /proc/bus/pci/devices can be printed without a printf format specification, so use seq_puts() instead of seq_printf(). This issue was detected by using the Coccinelle software. Link: https://lore.kernel.org/r/a6b110cb-0d0e-5dc3-9ca1-9041609cf74c@web.de Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-07-02PCI/P2PDMA: Fix missing check for dma_virt_opsLogan Gunthorpe
Drivers that use dma_virt_ops were meant to be rejected when testing compatibility for P2PDMA. This check got inadvertently dropped in one of the later versions of the original patchset, so add it back. Fixes: 52916982af48 ("PCI/P2PDMA: Support peer-to-peer memory") Link: https://lore.kernel.org/r/20190702173544.21950-1-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-07-02PCI: Skip resource distribution when no hotplug bridgesNicholas Johnson
If "hotplug_bridges == 0", "!dev->is_hotplug_bridge" is always true, so the loop that divides the remaining resources among hotplug-capable bridges does nothing. Check for "hotplug_bridges == 0" earlier, so we don't even have to compute the amount of remaining resources. No functional change intended. Link: https://lore.kernel.org/r/PS2P216MB0642C7A485649D2D787A1C6F80000@PS2P216MB0642.KORP216.PROD.OUTLOOK.COM Link: https://lore.kernel.org/r/20190622210310.180905-3-helgaas@kernel.org Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-07-02PCI: Simplify pci_bus_distribute_available_resources()Nicholas Johnson
Reorder pci_bus_distribute_available_resources() to group related code together. No functional change intended. Link: https://lore.kernel.org/r/PS2P216MB0642C7A485649D2D787A1C6F80000@PS2P216MB0642.KORP216.PROD.OUTLOOK.COM Link: https://lore.kernel.org/r/20190622210310.180905-2-helgaas@kernel.org Signed-off-by: Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2019-06-27PCI: dwc: Export APIs to support .remove() implementationVidya Sagar
Export all configuration space access APIs and also other APIs to support host controller drivers of dwc core based implementations while adding support for .remove() hook to build their respective drivers as modules. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
generated by cgit (git 2.34.1) at 2025-09-08 17:47:01 +0000