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2017-11-08xen/privcmd: remove unused variable pageidxColin Ian King
Variable pageidx is assigned a value but it is never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/xen/privcmd.c:199:2: warning: Value stored to 'pageidx' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Juergen Gross <jgross@suse.com> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
2017-11-08s390: vfio-ccw: Do not attempt to free no-op, test and tic cda.Jason J. Herne
Because we do not make use of the cda (channel data address) for test, no-op ccws no address translation takes place. This means cda could contain a guest address which we do not want to attempt to free. Let's check the command type and skip cda free when it is not needed. For a TIC ccw, ccw->cda points to either a ccw in an existing chain or it points to a whole new allocated chain. In either case the data will be freed when the owning chain is freed. Signed-off-by: Jason J. Herne <jjherne@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Message-Id: <1510068152-21988-1-git-send-email-jjherne@linux.vnet.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-11-09KEYS: fix NULL pointer dereference during ASN.1 parsing [ver #2]Eric Biggers
syzkaller reported a NULL pointer dereference in asn1_ber_decoder(). It can be reproduced by the following command, assuming CONFIG_PKCS7_TEST_KEY=y: keyctl add pkcs7_test desc '' @s The bug is that if the data buffer is empty, an integer underflow occurs in the following check: if (unlikely(dp >= datalen - 1)) goto data_overrun_error; This results in the NULL data pointer being dereferenced. Fix it by checking for 'datalen - dp < 2' instead. Also fix the similar check for 'dp >= datalen - n' later in the same function. That one possibly could result in a buffer overread. The NULL pointer dereference was reproducible using the "pkcs7_test" key type but not the "asymmetric" key type because the "asymmetric" key type checks for a 0-length payload before calling into the ASN.1 decoder but the "pkcs7_test" key type does not. The bug report was: BUG: unable to handle kernel NULL pointer dereference at (null) IP: asn1_ber_decoder+0x17f/0xe60 lib/asn1_decoder.c:233 PGD 7b708067 P4D 7b708067 PUD 7b6ee067 PMD 0 Oops: 0000 [#1] SMP Modules linked in: CPU: 0 PID: 522 Comm: syz-executor1 Not tainted 4.14.0-rc8 #7 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.10.3-20171021_125229-anatol 04/01/2014 task: ffff9b6b3798c040 task.stack: ffff9b6b37970000 RIP: 0010:asn1_ber_decoder+0x17f/0xe60 lib/asn1_decoder.c:233 RSP: 0018:ffff9b6b37973c78 EFLAGS: 00010216 RAX: 0000000000000000 RBX: 0000000000000000 RCX: 000000000000021c RDX: ffffffff814a04ed RSI: ffffb1524066e000 RDI: ffffffff910759e0 RBP: ffff9b6b37973d60 R08: 0000000000000001 R09: ffff9b6b3caa4180 R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000002 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 FS: 00007f10ed1f2700(0000) GS:ffff9b6b3ea00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 000000007b6f3000 CR4: 00000000000006f0 Call Trace: pkcs7_parse_message+0xee/0x240 crypto/asymmetric_keys/pkcs7_parser.c:139 verify_pkcs7_signature+0x33/0x180 certs/system_keyring.c:216 pkcs7_preparse+0x41/0x70 crypto/asymmetric_keys/pkcs7_key_type.c:63 key_create_or_update+0x180/0x530 security/keys/key.c:855 SYSC_add_key security/keys/keyctl.c:122 [inline] SyS_add_key+0xbf/0x250 security/keys/keyctl.c:62 entry_SYSCALL_64_fastpath+0x1f/0xbe RIP: 0033:0x4585c9 RSP: 002b:00007f10ed1f1bd8 EFLAGS: 00000216 ORIG_RAX: 00000000000000f8 RAX: ffffffffffffffda RBX: 00007f10ed1f2700 RCX: 00000000004585c9 RDX: 0000000020000000 RSI: 0000000020008ffb RDI: 0000000020008000 RBP: 0000000000000000 R08: ffffffffffffffff R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000216 R12: 00007fff1b2260ae R13: 00007fff1b2260af R14: 00007f10ed1f2700 R15: 0000000000000000 Code: dd ca ff 48 8b 45 88 48 83 e8 01 4c 39 f0 0f 86 a8 07 00 00 e8 53 dd ca ff 49 8d 46 01 48 89 85 58 ff ff ff 48 8b 85 60 ff ff ff <42> 0f b6 0c 30 89 c8 88 8d 75 ff ff ff 83 e0 1f 89 8d 28 ff ff RIP: asn1_ber_decoder+0x17f/0xe60 lib/asn1_decoder.c:233 RSP: ffff9b6b37973c78 CR2: 0000000000000000 Fixes: 42d5ec27f873 ("X.509: Add an ASN.1 decoder") Reported-by: syzbot <syzkaller@googlegroups.com> Cc: <stable@vger.kernel.org> # v3.7+ Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: James Morris <james.l.morris@oracle.com>
2017-11-08tty: ehv_bytechan: fix spelling mistakeArvind Yadav
Trivial fix to spelling mistakes "interupt" -> "interrupt". Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08VME: Return -EBUSY when DMA list in useMartyn Welch
The VME subsystem currently returns -EBUSY when trying to free a DMA resource that is busy, but returns -EINVAL when trying to free a DMA list that is in use. Switch to returning -EBUSY when trying to free a DMA list that is in use for consistency and correctness. Signed-off-by: Martyn Welch <martyn@welchs.me.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08w1: keep balance of mutex locks and refcntsAlexey Khoroshilov
w1_therm_eeprom() and w1_DS18B20_precision() decrement THERM_REFCNT on error paths, while they did not increment it yet. read_therm() unlocks bus mutex on some error paths, while it is not acquired. The patch makes sure all the functions keep the balance in usage of the mutex and the THERM_REFCNT. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08MAINTAINERS: Update VME subsystem tree.Martyn Welch
VME Subsystem lists driver-core repository as canonical tree. Greg has stated that char-misc should be used for submissions instead[1]. [1] https://lkml.org/lkml/2017/9/1/486 Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08gpio: Automatically add lockdep keysThierry Reding
In order to avoid lockdep boilerplate in individual drivers, turn the gpiochip_add_data() function into a macro that creates a unique class key for each driver. Note that this has the slight disadvantage of adding a key for each driver registered with the system. However, these keys are 8 bytes in size, which is negligible and a small price to pay for generic infrastructure. Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> [renane __gpiochip_add_data() to gpiochip_add_data_with_key] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08nvmem: sunxi-sid: add support for A64/H5's SID controllerIcenowy Zheng
Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but without the silicon bug that makes the initial value at 0x200 wrong, so the value at 0x200 can be directly read. Add support for this kind of SID controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Update module descriptionBryan O'Donoghue
This imx-ocotp driver encapsulates support for a subset of both i.MX6 and i.MX7 processors. Update the module description to reflect. Fixes: 711d45477931 ("nvmem: octop: Add i.MX7D support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Enable i.MX7D OTP write supportBryan O'Donoghue
After applying patches for both banked access and write timings we can re-enable the OTP write interface on i.MX7D processors. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Add i.MX7D timing write clock setup supportBryan O'Donoghue
This patch adds logic to correctly setup the write timing parameters when blowing an OTP fuse for the i.MX7S/D. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated functionBryan O'Donoghue
The i.MX7S/D has a different set of timing requirements, as a pre-cursor to adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated function. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Add support for banked OTP addressingBryan O'Donoghue
The i.MX7S/D takes the bank address in the CTRLn.ADDR field and the data value in one of the DATAx {0, 1, 2, 3} register fields. The current write routine is based on writing the CTRLn.ADDR field and writing a single DATA register only. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Pass parameters via a structBryan O'Donoghue
It will be useful in later patches to know the register access mode and bit-shift to apply to a given input offset. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-ocotp: Restrict OTP write to IMX6 processorsBryan O'Donoghue
i.MX7S/D have a different scheme for addressing the OTP registers inside the OCOTP block. Currently it's possible to address the wrong OTP registers given the disparity between IMX6 and IMX7 OTP addressing. Since OTP programming is one-time destructive its important we restrict this interface ASAP. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: uniphier: add UniPhier eFuse driverKeiji Hayashibara
Add eFuse driver for Socionext UniPhier series SoC. Note that eFuse device is under soc-glue and this register implements as read only. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08dt-bindings: nvmem: add description for UniPhier eFuseKeiji Hayashibara
Add uniphier-efuse dt-bindings documentation. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08gpio: Introduce struct gpio_irq_chip.firstThierry Reding
Some GPIO chips cannot support sparse IRQ numbering and therefore need to manually allocate their interrupt descriptors statically. For these cases, a driver can pass the first allocated IRQ via the struct gpio_irq_chip's "first" field and thereby cause the IRQ domain to map all IRQs during initialization. Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Disambiguate struct gpio_irq_chip.nestedThierry Reding
The nested field in struct gpio_irq_chip currently has two meanings. On one hand it marks an IRQ chip as being nested (as opposed to chained), while on the other hand it also means that an IRQ chip uses nested thread handlers. However, nested IRQ chips can already be identified by the fact that they don't pass a parent handler (the driver would instead already have installed a nested handler using request_irq()). Therefore, the only use for the nested attribute is to inform gpiolib that an IRQ chip uses nested thread handlers (as opposed to regular, non-threaded handlers). To clarify its purpose, rename the field to "threaded". Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Add Tegra186 supportThierry Reding
Tegra186 has two GPIO controllers that are largely register compatible between one another but are completely different from the controller found on earlier generations. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Export gpiochip_irq_{map,unmap}()Thierry Reding
Export these functions so that drivers can explicitly use these when setting up their IRQ domain. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Implement tighter IRQ chip integrationThierry Reding
Currently GPIO drivers are required to add the GPIO chip and its corresponding IRQ chip separately, which can result in a lot of boilerplate. Use the newly introduced struct gpio_irq_chip, embedded in struct gpio_chip, that drivers can fill in if they want the GPIO core to automatically register the IRQ chip associated with a GPIO chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move lock_key into struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irq_valid_mask into struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irq_nested into struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08Merge tag 'kvm-ppc-fixes-4.14-2' of ↵Radim Krčmář
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc PPC KVM fixes for 4.14 Just one fix here for a host crash that can occur with HV KVM as a result of resizing the guest hashed page table (HPT).
2017-11-08gpio: Move irq_chained_parent to struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irq_default_type to struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irq_handler to struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irqdomain into struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irqchip into struct gpio_irq_chipThierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Introduce struct gpio_irq_chipThierry Reding
This new structure will be used to group all fields related to interrupt handling in a GPIO chip. Doing so will properly namespace these fields and make it easier to distinguish which fields are used for IRQ support. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08nvmem: set nvmem->owner to nvmem->dev->driver->owner if unsetMasahiro Yamada
All nvmem drivers are supposed to set the owner field of struct nvmem_config, but this matches nvmem->dev->driver->owner. As far as I see in drivers/nvmem/ directory, all the drivers are the case. So, make nvmem_register() set the nvmem's owner to the associated driver's owner unless nvmem_config sets otherwise. Remove .owner settings in the drivers that are now redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: qfprom: fix different address space warnings of sparseMasahiro Yamada
Fix the following sparse warnings: drivers/nvmem/qfprom.c:23:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/qfprom.c:23:30: expected void [noderef] <asn:2>*base drivers/nvmem/qfprom.c:23:30: got void *context drivers/nvmem/qfprom.c:36:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/qfprom.c:36:30: expected void [noderef] <asn:2>*base drivers/nvmem/qfprom.c:36:30: got void *context drivers/nvmem/qfprom.c:76:22: warning: incorrect type in assignment (different address spaces) drivers/nvmem/qfprom.c:76:22: expected void *static [toplevel] [assigned] priv drivers/nvmem/qfprom.c:76:22: got void [noderef] <asn:2>*[assigned] base The type of nvmem_config->priv is (void *), so sparse complains about assignment of the base address with (void __iomem *) type. Even if we cast it out, sparse still warns: warning: cast removes address space of expression Of course, we can shut up the sparse by marking __force, but a more correct way is to put the base address into driver private data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: mtk-efuse: fix different address space warnings of sparseMasahiro Yamada
Fix the following sparse warnings: drivers/nvmem/mtk-efuse.c:24:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/mtk-efuse.c:24:30: expected void [noderef] <asn:2>*base drivers/nvmem/mtk-efuse.c:24:30: got void *context drivers/nvmem/mtk-efuse.c:37:30: warning: incorrect type in initializer (different address spaces) drivers/nvmem/mtk-efuse.c:37:30: expected void [noderef] <asn:2>*base drivers/nvmem/mtk-efuse.c:37:30: got void *context drivers/nvmem/mtk-efuse.c:69:23: warning: incorrect type in assignment (different address spaces) drivers/nvmem/mtk-efuse.c:69:23: expected void *priv drivers/nvmem/mtk-efuse.c:69:23: got void [noderef] <asn:2>*[assigned] base The type of nvmem_config->priv is (void *), so sparse complains about assignment of the base address with (void __iomem *) type. Even if we cast it out, sparse still warns: warning: cast removes address space of expression Of course, we can shut up the sparse by marking __force, but a more correct way is to put the base address into driver private data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: mtk-efuse: use stack for nvmem_config instead of malloc'ing itMasahiro Yamada
nvmem_register() copies all the members of nvmem_config to nvmem_device. So, nvmem_config is one-time use data during probing. There is no point to keep it until the driver detach. Using stack should be no problem because nvmem_config is pretty small. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08nvmem: imx-iim: use stack for nvmem_config instead of malloc'ing itMasahiro Yamada
nvmem_register() copies all the members of nvmem_config to nvmem_device. So, nvmem_config is one-time use data during probing. There is no point to keep it until the driver detach. Using stack should be no problem because nvmem_config is pretty small. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08pinctrl: gemini: Fix GMAC groupsLinus Walleij
The GMII groups need to be split across GMAC0 and GMAC1 since GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 so we might want just one interface out. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08zd1201: remove unused variable framelenColin Ian King
Variable framelen is assigned but never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/net/wireless/zydas/zd1201.c:234:3: warning: Value stored to 'framelen' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2017-11-08orinoco_usb: remove redundant pointer devColin Ian King
The pointer dev is assigned but never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/net/wireless/intersil/orinoco/orinoco_usb.c:1468:2: warning: Value stored to 'dev' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2017-11-08iwlegacy: remove redundant pointer sta_privColin Ian King
Pointer sta_priv is assigned but never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/net/wireless/intel/iwlegacy/4965-rs.c:2163:2: warning: Value stored to 'sta_priv' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2017-11-08driver core: Fix device link deferred probeAdrian Hunter
A device probe deferred because of a device link is never probed again because it is not added to the deferred_probe_pending_list. Add it, taking care of the race with driver_deferred_probe_trigger(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-08pinctrl: qcom: spmi-gpio: Add pmi8994 gpio supportRajendra Nayak
Update the binding and driver for pmi8994-gpios Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: ti-iodelay: remove redundant unused variable devColin Ian King
The pointer dev is being assigned but is never used, hence it is redundant and can be removed. Cleans up clang warnings: drivers/pinctrl/ti/pinctrl-ti-iodelay.c:582:2: warning: Value stored to 'dev' is never read drivers/pinctrl/ti/pinctrl-ti-iodelay.c:701:2: warning: Value stored to 'dev' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: max77620: Use common error handling code in max77620_pinconf_set()Markus Elfring
* Add a jump target so that a specific error message is stored only once at the end of this function implementation. * Replace two calls of the function "dev_err" by goto statements. * Adjust two condition checks. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Implement clock skew/delay configLinus Walleij
This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Use generic DT parserLinus Walleij
We can just use the generic Device Tree parser code in this driver and save some code. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: Add skew-delay pin config and bindingsLinus Walleij
Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08rtlwifi: remove redundant initialization to cfg_cmdColin Ian King
cfg_cmd is initialized to zero and this value is never read, instead it is over-written in the start of a do-while loop. Remove the redundant initialization. Cleans up clang warning: drivers/net/wireless/realtek/rtlwifi/core.c:1750:22: warning: Value stored to 'cfg_cmd' during its initialization is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
generated by cgit (git 2.34.1) at 2025-09-24 12:51:57 +0000