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2021-04-09crypto: qat - Fix a double free in adf_create_ringLv Yunlong
In adf_create_ring, if the callee adf_init_ring() failed, the callee will free the ring->base_addr by dma_free_coherent() and return -EFAULT. Then adf_create_ring will goto err and the ring->base_addr will be freed again in adf_cleanup_ring(). My patch sets ring->base_addr to NULL after the first freed to avoid the double free. Fixes: a672a9dc872ec ("crypto: qat - Intel(R) QAT transport code") Signed-off-by: Lv Yunlong <lyl2019@mail.ustc.edu.cn> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/qm - delete redundant codeKai Ye
The "qdma" is a structure variable instead of actual data. This structure doesn't need to be zerod, The memset is useless and redundant. So delete it. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/sec - fixup checking the 3DES weak keyKai Ye
skcipher: Add a verifying to check whether the triple DES key is weak. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: sa2ul - Fix memory leak of rxdColin Ian King
There are two error return paths that are not freeing rxd and causing memory leaks. Fix these. Addresses-Coverity: ("Resource leak") Fixes: 00c9211f60db ("crypto: sa2ul - Fix DMA mapping API usage") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: sun8i-ss - Fix memory leak of padColin Ian King
It appears there are several failure return paths that don't seem to be free'ing pad. Fix these. Addresses-Coverity: ("Resource leak") Fixes: d9b45418a917 ("crypto: sun8i-ss - support hash algorithms") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Corentin Labbe <clabbe.montjoie@gmail.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: rockchip - delete unneeded variable initializationKai Ye
Delete unneeded variable initialization Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: ccp - Use DEFINE_SPINLOCK() for spinlockTang Yizhou
spinlock can be initialized automatically with DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init(). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Tang Yizhou <tangyizhou@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/hpre - fix a typo in hpre_crypto.cRuiqi Gong
Do a trivial typo fix. s/discribed/described Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Ruiqi Gong <gongruiqi1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: ccp - A value assigned to a variable is never usedJiapeng Chong
Fix the following whitescan warning: Assigning value "64" to "dst.address" here, but that stored value is overwritten before it can be used. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: John Allen <john.allen@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/sec - Fix a module parameter errorLongfang Liu
ctx_q_num is a module parameter set by the user to specify the number of qp queues required to create a ctx. When the number of qp queues allocated by PF or VF is less than the ctx_q_num, an error will be reported when ctx is initialized in kernel mode, which leads to the problem that the registered algorithms cannot be used. Therefore, when PF or VF is initialized, if the number of qp queues is not enough to create a ctx, the kernel mode cannot be used, and there is no need to register the kernel mode algorithms. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: allwinner - add missing CRYPTO_ prefixCorentin Labbe
Some CONFIG select miss CRYPTO_. Reported-by: Chen-Yu Tsai <wens@csie.org> Fixes: 56f6d5aee88d1 ("crypto: sun8i-ce - support hash algorithms") Fixes: d9b45418a9177 ("crypto: sun8i-ss - support hash algorithms") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09ARM: dts: clps711x: fix missing interrupt parentArnd Bergmann
The kernelci.org bot reports a build time regression: arch/arm/boot/dts/ep7209.dtsi:187.17-192.4: Warning (interrupts_property): /keypad: Missing interrupt-parent There is only one interrupt controller in this SoC, so I assume this is the parent. Fixes: 2bd86203acf3 ("ARM: dts: clps711x: Add keypad node") Reported-by: kernelci.org bot <bot@kernelci.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09ARM: dts: mvebu: fix SPI device nodeArnd Bergmann
dtc warns about a mismatched address: arch/arm/boot/dts/armada-385-atl-x530.dts:171.14-199.4: Warning (spi_bus_reg): /soc/spi@10680/spi-flash@0: SPI bus unit address format error, expected "1" I assume the "reg" property is correct here, so adjust the unit address accordingly. Fixes: c6dfc019c239 ("ARM: dts: mvebu: Add device tree for ATL-x530 Board") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: kernelci.org bot <bot@kernelci.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski
Pointers should be cast with uintptr_t instead of integer. This fixes warning when compile testing on ARM64: drivers/clk/socfpga/clk-gate.c: In function ‘socfpga_clk_recalc_rate’: drivers/clk/socfpga/clk-gate.c:102:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Fixes: b7cec13f082f ("clk: socfpga: Look for the GPIO_DB_CLK by its offset") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09Merge tag 'bmc-5.13-wpcm450' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/newsoc Nuvoton WPCM450 BMC SoC This adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older SoC but still commonly found on eBay, mostly in Supermicro X9 server boards. Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki The code has been contributed by Jonathan Neuschäfer who has also stepped forward to maintain the soc. * tag 'bmc-5.13-wpcm450' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: config: Add WPCM to multi v5 MAINTAINERS: Add entry for Nuvoton WPCM450 ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450 ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chip watchdog: npcm: Add support for WPCM450 ARM: npcm: Introduce Nuvoton WPCM450 SoC dt-bindings: watchdog: npcm: Add nuvoton,wpcm450-wdt dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible string dt-bindings: vendor-prefixes: Add Supermicro ARM: dts: Add board-specific compatible string to npcm750-evb devicetree dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML Link: https://lore.kernel.org/r/CACPK8Xdj20TcJckH8fx757ACa4hT4j3bZEctT0Przjv8XJd7KA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09Merge tag 'aspeed-5.13-lpc' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/drivers ASPEED LPC updates for 5.13 These patches fix the ASPEED LPC bindings and LPC-related device drivers so in the future the KCS driver can properly use the hardware. * tag 'aspeed-5.13-lpc' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: soc: aspeed: Adapt to new LPC device tree layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout ipmi: kcs: aspeed: Adapt to new LPC DTS layout ARM: dts: Remove LPC BMC and Host partitions dt-bindings: aspeed-lpc: Remove LPC partitioning Link: https://lore.kernel.org/r/CACPK8Xcb12LsVr7CUaXXjQskKbVjb7x+jgueG1Hik-kBPWtDSg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09Merge tag 'bmc-5.13-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt BMC device tree updates for 5.13 The ASPEED and Nuvoton pull request now comes as a combined BMC pull request. - New machines * ASRock E3C246D4I, an AST2500 BMC for an Xeon E-2100/E-2200 mini-ITX system * Quanta GBS, an NPCM730 BMC for an x86 server - Power10 BMC updates for Everest and Rainier - GPIO line names for Mihawk * tag 'bmc-5.13-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: (21 commits) ARM: dts: nuvoton: Add Quanta GBS BMC Device Tree ARM: dts: aspeed: mihawk: Add GPIO line names ARM: dts: aspeed: Add Rainier 1S4U machine ARM: dts: aspeed: everest: Add size/address cells ARM: dts: aspeed: everest: Enable fan watchdog ARM: dts: aspeed: everest: Add RTC ARM: dts: aspeed: everest: GPIOs support ARM: dts: aspeed: everest: Add UCD90320 power sequencer ARM: dts: aspeed: everest: Add power supply i2c devices ARM: dts: aspeed: everest: Add pca9552 fan presence ARM: dts: aspeed: everest: Add FSI CFAMs and re-number engines ARM: dts: aspeed: everest: Add max31785 fan controller device ARM: dts: aspeed: everest: Add I2C components ARM: dts: aspeed: rainier 4U: Fix fan configuration ARM: dts: aspeed: rainier: Add missing fan nodes ARM: dts: aspeed: rainier: Enable fan watchdog ARM: dts: aspeed: rainier: Add presence GPIOs ARM: dts: aspeed: rainier: Add additional processor CFAMs ARM: dts: aspeed: rainier: Add gpio-keys-polled for fans ARM: dts: aspeed: rainier: Add directly controlled LEDs ... Link: https://lore.kernel.org/r/CACPK8Xe-KV5BeQwOH6NKC1++FCVqwwNCGBh7hEbBORfrmxfTtQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09asm-generic/io.h: Unbork ioremap_np() declarationHector Martin
It accidentally slipped into the #ifdef for ioremap_uc(). Signed-off-by: Hector Martin <marcan@marcan.st> Link: https://lore.kernel.org/r/20210409052038.58925-1-marcan@marcan.st' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09ARM: config: Add WPCM to multi v5Joel Stanley
This is a newly added ARM926 platform that is not covered by any other defconfigs. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210409054511.1534181-1-joel@jms.id.au
2021-04-08libnvdimm: Notify disk drivers to revalidate region read-onlyDan Williams
Previous kernels allowed the BLKROSET to override the disk's read-only status. With that situation fixed the pmem driver needs to rely on notification events to reevaluate the disk read-only status after the host region has been marked read-write. Recall that when libnvdimm determines that the persistent memory has lost persistence (for example lack of energy to flush from DRAM to FLASH on an NVDIMM-N device) it marks the region read-only, but that state can be overridden by the user via: echo 0 > /sys/bus/nd/devices/regionX/read_only ...to date there is no notification that the region has restored persistence, so the user override is the only recovery. Fixes: 52f019d43c22 ("block: add a hard-readonly flag to struct gendisk") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Vishal Verma <vishal.l.verma@intel.com> Tested-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Cc: Christoph Hellwig <hch@lst.de> Cc: Ming Lei <ming.lei@redhat.com> Cc: Martin K. Petersen <martin.petersen@oracle.com> Cc: Hannes Reinecke <hare@suse.de> Cc: Jens Axboe <axboe@kernel.dk> Link: https://lore.kernel.org/r/161534060720.528671.2341213328968989192.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-04-09MAINTAINERS: Add entry for Nuvoton WPCM450Jonathan Neuschäfer
I am adding myself as the maintainer of WPCM450-related code. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-11-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450Jonathan Neuschäfer
The Supermicro X9SCi-LN4F is a server mainboard featuring the WPCM450 BMC. This patch adds a minimal devicetree for Linux running on the BMC. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-10-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chipJonathan Neuschäfer
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally marketed as Winbond WPCM450. This patch adds a devicetree with basic functionality. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-9-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09watchdog: npcm: Add support for WPCM450Jonathan Neuschäfer
Add a compatible string for WPCM450, which has essentially the same watchdog mechanism as NPCM750. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-8-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: npcm: Introduce Nuvoton WPCM450 SoCJonathan Neuschäfer
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally marketed as Winbond WPCM450. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-6-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: watchdog: npcm: Add nuvoton,wpcm450-wdtJonathan Neuschäfer
Add a compatible string for the WPCM450 SoC, which has the same watchdog timer. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-5-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible stringJonathan Neuschäfer
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally marketed as Winbond WPCM450. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-3-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: vendor-prefixes: Add SupermicroJonathan Neuschäfer
Super Micro Computer, Inc. (https://www.supermicro.com/en/), commonly known as Supermicro, is a manufacturer of server hardware. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-2-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09bus: mhi: core: Fix shadow declarationsManivannan Sadhasivam
This commit fixes below sparse warnings with W=2 about shadow declarations: drivers/bus/mhi/core/main.c: In function ‘parse_xfer_event’: drivers/bus/mhi/core/main.c:667:17: warning: declaration of ‘flags’ shadows a previous local [-Wshadow] 667 | unsigned long flags; | ^~~~~ drivers/bus/mhi/core/main.c:565:16: note: shadowed declaration is here 565 | unsigned long flags = 0; | ^~~~~ drivers/bus/mhi/core/main.c: In function ‘mhi_process_ctrl_ev_ring’: drivers/bus/mhi/core/main.c:856:23: warning: declaration of ‘new_state’ shadows a previous local [-Wshadow] 856 | enum mhi_pm_state new_state; | ^~~~~~~~~ drivers/bus/mhi/core/main.c:837:19: note: shadowed declaration is here 837 | enum mhi_state new_state; | ^~~~~~~~~ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2021-04-09soc: aspeed: Adapt to new LPC device tree layoutChia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-5-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09pinctrl: aspeed-g5: Adapt to new LPC device tree layoutChia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ipmi: kcs: aspeed: Adapt to new LPC DTS layoutChia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: dts: Remove LPC BMC and Host partitionsChia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. A concrete instance is that the HICRB[5:4] are for the I/O port address configurtaion of KCS channel 1/2. However, the KCS driver cannot access HICRB for channel 1/2 initialization via syscon regmap interface due to the parition boundary. (i.e. offset 80h) In addition, for the HW design backward compatibility, a newly added HW control bit could be located at any reserved one over the LPC addressing space. Thereby, this patch removes the lpc-bmc and lpc-host child node and thus the LPC partitioning. Note that this change requires the synchronization between device tree change and the driver change. To prevent the misuse of old devicetrees with new drivers, or vice versa, the v2 compatible strings are adopted for the LPC device as listed: "aspeed,ast2400-lpc-v2" "aspeed,ast2500-lpc-v2" "aspeed,ast2600-lpc-v2" Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-2-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: aspeed-lpc: Remove LPC partitioningChia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. This patch fixes the documentation by removing the description on LPC partitions. The register offsets illustrated in the DTS node examples are also fixed to adapt to the LPC DTS change. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-1-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-08Merge tag '5.12-rc6-smb3' of git://git.samba.org/sfrench/cifs-2.6Linus Torvalds
Pull cifs fixes from Steve French: "Three cifs/smb3 fixes, two for stable: a reconnect fix and a fix for display of devnames with special characters" * tag '5.12-rc6-smb3' of git://git.samba.org/sfrench/cifs-2.6: cifs: escape spaces in share names fs: cifs: Remove unnecessary struct declaration cifs: On cifs_reconnect, resolve the hostname again.
2021-04-09Merge tag 'drm-msm-fixes-2021-04-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/msm into drm-fixes some more minor fixes: - a5xx/a6xx timestamp fix - microcode version check - fail path fix - block programming fix - error removal fix. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsMj7Nv3vVaVWMxPy8Y=Z_SnZmVKhKgKDxDYTr9rGN_+w@mail.gmail.com
2021-04-08net: ipv6: check for validity before dereferencing cfg->fc_nlinfo.nlhMuhammad Usama Anjum
nlh is being checked for validtity two times when it is dereferenced in this function. Check for validity again when updating the flags through nlh pointer to make the dereferencing safe. CC: <stable@vger.kernel.org> Addresses-Coverity: ("NULL pointer dereference") Signed-off-by: Muhammad Usama Anjum <musamaanjum@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08Merge branch 'lantiq-GSWIP-fixes'David S. Miller
Martin Blumenstingl says: ==================== lantiq: GSWIP: two more fixes after my last patch got accepted and is now in net as commit 3e6fdeb28f4c33 ("net: dsa: lantiq_gswip: Let GSWIP automatically set the xMII clock") [0] some more people from the OpenWrt community (many thanks to everyone involved) helped test the GSWIP driver: [1] It turns out that the previous fix does not work for all boards. There's no regression, but it doesn't fix as many problems as I thought. This is why two more fixes are needed: - the first one solves many (four known but probably there are a few extra hidden ones) reported bugs with the GSWIP where no traffic would flow. Not all circumstances are fully understood but testing shows that switching away from PHY auto polling solves all of them - while investigating the different problems which are addressed by the first patch some small issues with the existing code were found. These are addressed by the second patch Changes since v1 at [0]: - Don't configure the link parameters in gswip_phylink_mac_config (as we're using the "modern" way in gswip_phylink_mac_link_up). Thanks to Andrew for the hint with the phylink documentation. - Clarify that GSWIP_MII_CFG_RMII_CLK is ignored by the hardware in the description of the second patch as suggested by Hauke - Don't set GSWIP_MII_CFG_RGMII_IBS in the second patch as we don't have any hardware available for testing this. The patch description now also reflects this. - Added Andrew's Reviewed-by to the first patch (thank you!) ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: dsa: lantiq_gswip: Configure all remaining GSWIP_MII_CFG bitsMartin Blumenstingl
There are a few more bits in the GSWIP_MII_CFG register for which we did rely on the boot-loader (or the hardware defaults) to set them up properly. For some external RMII PHYs we need to select the GSWIP_MII_CFG_RMII_CLK bit and also we should un-set it for non-RMII PHYs. The GSWIP_MII_CFG_RMII_CLK bit is ignored for other PHY connection modes. The GSWIP IP also supports in-band auto-negotiation for RGMII PHYs when the GSWIP_MII_CFG_RGMII_IBS bit is set. Clear this bit always as there's no known hardware which uses this (so it is not tested yet). Clear the xMII isolation bit when set at initialization time if it was previously set by the bootloader. Not doing so could lead to no traffic (neither RX nor TX) on a port with this bit set. While here, also add the GSWIP_MII_CFG_RESET bit. We don't need to manage it because this bit is self-clearning when set. We still add it here to get a better overview of the GSWIP_MII_CFG register. Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Cc: stable@vger.kernel.org Suggested-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: dsa: lantiq_gswip: Don't use PHY auto pollingMartin Blumenstingl
PHY auto polling on the GSWIP hardware can be used so link changes (speed, link up/down, etc.) can be detected automatically. Internally GSWIP reads the PHY's registers for this functionality. Based on this automatic detection GSWIP can also automatically re-configure it's port settings. Unfortunately this auto polling (and configuration) mechanism seems to cause various issues observed by different people on different devices: - FritzBox 7360v2: the two Gbit/s ports (connected to the two internal PHY11G instances) are working fine but the two Fast Ethernet ports (using an AR8030 RMII PHY) are completely dead (neither RX nor TX are received). It turns out that the AR8030 PHY sets the BMSR_ESTATEN bit as well as the ESTATUS_1000_TFULL and ESTATUS_1000_XFULL bits. This makes the PHY auto polling state machine (rightfully?) think that the established link speed (when the other side is Gbit/s capable) is 1Gbit/s. - None of the Ethernet ports on the Zyxel P-2812HNU-F1 (two are connected to the internal PHY11G GPHYs while the other three are external RGMII PHYs) are working. Neither RX nor TX traffic was observed. It is not clear which part of the PHY auto polling state- machine caused this. - FritzBox 7412 (only one LAN port which is connected to one of the internal GPHYs running in PHY22F / Fast Ethernet mode) was seeing random disconnects (link down events could be seen). Sometimes all traffic would stop after such disconnect. It is not clear which part of the PHY auto polling state-machine cauased this. - TP-Link TD-W9980 (two ports are connected to the internal GPHYs running in PHY11G / Gbit/s mode, the other two are external RGMII PHYs) was affected by similar issues as the FritzBox 7412 just without the "link down" events Switch to software based configuration instead of PHY auto polling (and letting the GSWIP hardware configure the ports automatically) for the following link parameters: - link up/down - link speed - full/half duplex - flow control (RX / TX pause) After a big round of manual testing by various people (who helped test this on OpenWrt) it turns out that this fixes all reported issues. Additionally it can be considered more future proof because any "quirk" which is implemented for a PHY on the driver side can now be used with the GSWIP hardware as well because Linux is in control of the link parameters. As a nice side-effect this also solves a problem where fixed-links were not supported previously because we were relying on the PHY auto polling mechanism, which cannot work for fixed-links as there's no PHY from where it can read the registers. Configuring the link settings on the GSWIP ports means that we now use the settings from device-tree also for ports with fixed-links. Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Fixes: 3e6fdeb28f4c33 ("net: dsa: lantiq_gswip: Let GSWIP automatically set the xMII clock") Cc: stable@vger.kernel.org Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08arm64: allow CONFIG_CFI_CLANG to be selectedSami Tolvanen
Select ARCH_SUPPORTS_CFI_CLANG to allow CFI to be enabled. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-19-samitolvanen@google.com
2021-04-08KVM: arm64: Disable CFI for nVHESami Tolvanen
Disable CFI for the nVHE code to avoid address space confusion. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-18-samitolvanen@google.com
2021-04-08arm64: ftrace: use function_nocfi for ftrace_callSami Tolvanen
With CONFIG_CFI_CLANG, the compiler replaces function pointers with jump table addresses, which breaks dynamic ftrace as the address of ftrace_call is replaced with the address of ftrace_call.cfi_jt. Use function_nocfi() to get the address of the actual function instead. Suggested-by: Ben Dai <ben.dai@unisoc.com> Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-17-samitolvanen@google.com
2021-04-08arm64: add __nocfi to __apply_alternativesSami Tolvanen
__apply_alternatives makes indirect calls to functions whose address is taken in assembly code using the alternative_cb macro. With non-canonical CFI, the compiler won't replace these function references with the jump table addresses, which trips CFI. Disable CFI checking in the function to work around the issue. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-16-samitolvanen@google.com
2021-04-08arm64: add __nocfi to functions that jump to a physical addressSami Tolvanen
Disable CFI checking for functions that switch to linear mapping and make an indirect call to a physical address, since the compiler only understands virtual addresses and the CFI check for such indirect calls would always fail. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-15-samitolvanen@google.com
2021-04-08arm64: use function_nocfi with __pa_symbolSami Tolvanen
With CONFIG_CFI_CLANG, the compiler replaces function address references with the address of the function's CFI jump table entry. This means that __pa_symbol(function) returns the physical address of the jump table entry, which can lead to address space confusion as the jump table points to the function's virtual address. Therefore, use the function_nocfi() macro to ensure we are always taking the address of the actual function instead. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-14-samitolvanen@google.com
2021-04-08arm64: implement function_nocfiSami Tolvanen
With CONFIG_CFI_CLANG, the compiler replaces function addresses in instrumented C code with jump table addresses. This change implements the function_nocfi() macro, which returns the actual function address instead. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-13-samitolvanen@google.com
2021-04-08psci: use function_nocfi for cpu_resumeSami Tolvanen
With CONFIG_CFI_CLANG, the compiler replaces function pointers with jump table addresses, which results in __pa_symbol returning the physical address of the jump table entry. As the jump table contains an immediate jump to an EL1 virtual address, this typically won't work as intended. Use function_nocfi to get the actual address of cpu_resume. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-12-samitolvanen@google.com
2021-04-08lkdtm: use function_nocfiSami Tolvanen
To ensure we take the actual address of a function in kernel text, use function_nocfi. Otherwise, with CONFIG_CFI_CLANG, the compiler replaces the address with a pointer to the CFI jump table, which is actually in the module when compiled with CONFIG_LKDTM=m. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Acked-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-11-samitolvanen@google.com
2021-04-08treewide: Change list_sort to use const pointersSami Tolvanen
list_sort() internally casts the comparison function passed to it to a different type with constant struct list_head pointers, and uses this pointer to call the functions, which trips indirect call Control-Flow Integrity (CFI) checking. Instead of removing the consts, this change defines the list_cmp_func_t type and changes the comparison function types of all list_sort() callers to use const pointers, thus avoiding type mismatches. Suggested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210408182843.1754385-10-samitolvanen@google.com
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