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2023-02-08dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yamlDmitry Baryshkov
The GPU clock controller bindings for the Qualcomm sm8350 platform are not correct. The driver uses .fw_name instead of using indices to bind parent clocks, thus demanding the clock-names usage. With the proper clock-names in place, the bindings becomes equal to the bindings defined by qcom,gpucc.yaml, so it is impractical to keep them in a separate file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230206145707.122937-2-dmitry.baryshkov@linaro.org
2023-02-08clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSCDmitry Baryshkov
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org
2023-02-08clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSCDmitry Baryshkov
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while registering the GDSC (writing the value 0x2 by default). This will override the setting done in the driver's probe function. Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe function. Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180") Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230201172305.993146-1-dmitry.baryshkov@linaro.org
2023-02-08dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains propertyBartosz Golaszewski
The binding document is missing the power-domains property. Add it and update the example. Fixes: 0fff9fa043f9 ("dt-bindings: clock: Add Qualcomm SA8775P GCC") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130145154.195562-1-brgl@bgdev.pl
2023-02-08clk: qcom: cpu-8996: add missing cputype includeKrzysztof Kozlowski
Include asm/cputype.h to fix ARMv7 compile test error: drivers/clk/qcom/clk-cpu-8996.c: In function ‘qcom_cpu_clk_msm8996_acd_init’: drivers/clk/qcom/clk-cpu-8996.c:468:16: error: implicit declaration of function ‘read_cpuid_mpidr’ [-Werror=implicit-function-declaration] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved asm-include after linux/, per Stephen's request] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230123201812.1230039-1-krzysztof.kozlowski@linaro.org
2023-02-08clk: qcom: gcc-sa8775p: remove unused variablesBartosz Golaszewski
There are four struct definitions in the driver that aren't used so remove them. Reported-by: kernel test robot <lkp@intel.com> Fixes: ed432b1ed00a ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230123103338.230320-1-brgl@bgdev.pl
2023-02-08clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platformDmitry Baryshkov
Extend the list of RPM clocks provided on MSM8996 platform to also include RPM_SMD_XO_CLK_SRC and RPM_SMD_XO_A_CLK_SRC. Fixes: 7066fdd0d742 ("clk: qcom: clk-smd-rpm: add msm8996 rpmclks") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-6-dmitry.baryshkov@linaro.org
2023-02-08clk: qcom: add msm8996 Core Bus Framework (CBF) supportDmitry Baryshkov
Add CBF clock driver as a part of MSM8996 CPU clocks. Significantly based on AngeloGioacchino del Regno's work at [1]. The CBF is an interconnect between two CPU clusters, setting it up properly is required for booting the MSM8996 with all four cores enabled. [1] https://github.com/sonyxperiadev/kernel/blob/aosp/LE.UM.2.3.2.r1.4/drivers/clk/qcom/clk-cpu-8996.c Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Dropped partially uninitialized variable "ret" from cbf_clk_notifier_cb()] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-4-dmitry.baryshkov@linaro.org
2023-02-08dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controllerDmitry Baryshkov
MSM8996 Core Bus Fabric (CBF) clock controller clocks an interconnect between two CPU clusters. The CBF clock should follow the CPU frequencies to provide enough bandwidth between clusters. Thus a single driver implements both a clock and an interconnect to set the clock rate. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230120061417.2623751-2-dmitry.baryshkov@linaro.org
2023-02-08clk: qcom: add the driver for the MSM8996 APCS clocksDmitry Baryshkov
Add a simple driver handling the APCS clocks on MSM8996. For now it supports just a single aux clock, linking GPLL0 to CPU and CBF clocks. Note, there is little sense in registering sys_apcs_aux as a child of gpll0. The PLL is always-on. And listing the gpll0 as a property of the apcs would delay its probing until the GCC has been probed (while we would like for the apcs to be probed as early as possible). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Fixed spelling of register, per Stephen's feedback] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230126230319.3977109-8-dmitry.baryshkov@linaro.org
2023-01-30clk: qcom: gcc-qcs404: fix duplicate initializer warningArnd Bergmann
In one of the clocks, a redundant initialization for .num_parents got left behind by a recent patch: drivers/clk/qcom/gcc-qcs404.c:63:32: error: initialized field overwritten [-Werror=override-init] 63 | .num_parents = 1, | ^ Fixes: 2ce81afa0c7c ("clk: qcom: gcc-qcs404: sort out the cxo clock") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130135555.3268172-1-arnd@kernel.org
2023-01-18clk: qcom: cpu-8996: change setup sequence to follow vendor kernelDmitry Baryshkov
Add missing register writes to CPU clocks setup procedure. This makes it follow the setup procedure used in msm-3.18 kernel. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-14-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix PLL clock opsDmitry Baryshkov
Switch CPU PLLs to use clk_alpha_pll_hwfsm_ops, it seems to suit better. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-13-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix ACD initializationDmitry Baryshkov
The vendor kernel applies different order while programming SSSCTL and L2ACDCR registers on power and performance clusters. However it was demonstrated that doing this upstream results in the board reset. Make both clusters use the same sequence, which fixes the reset. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-12-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix PLL configuration sequenceDmitry Baryshkov
Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux) before PLL configuration. Switch them to the ACD afterwards. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-11-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init callDmitry Baryshkov
Initialize ACD configuration from qcom_cpu_clk_msm8996_register_clks(), before registering all clocks. This way we can be sure that the clock is fully configured before letting CCF touch it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-10-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: setup PLLs before registering clocksDmitry Baryshkov
Setup all PLLs before registering clocks in the common clock framework. This ensures that the clocks are not accessed before being setup in the known way and that the CCF is in sync with the actual HW programming. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-9-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cbDmitry Baryshkov
- Do not use the Alt PLL completely. Switch to smux when necessary to prevent overvolting - Restore the parent in case the rate change aborts for some reason - Do not duplicate resetting the parent in set_parent operation. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-8-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: skip ACD init if the setup is validDmitry Baryshkov
Check whether L2 registers contain correct values and skip programming if they are valid. This follows the code present downstream. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-7-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: support using GPLL0 as SMUX inputDmitry Baryshkov
In some cases the driver might need using GPLL0 to drive CPU clocks. Bring it in through the sys_apcs_aux clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-6-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix the init clock rateDmitry Baryshkov
Current multiplier (60) results in CPU getting the rate which is unlisted in the CPU frequency tables (60 * 19.2 = 1152 MHz). This results in warnings from the cpufreq during startup. Change PLL programming (l = 54) to init CPU clocks to start with the frequency of 54 * 19.2 = 1036.8 MHz which is supported by both power and performance clusters from all speed bins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-5-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: correct PLL programmingDmitry Baryshkov
Change PLL programming to follow the downstream setup. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-4-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: clk-alpha-pll: program PLL_TEST/PLL_TEST_U if requiredDmitry Baryshkov
Program PLL_TEST and PLL_TEST_U registers if required by the pll configuration. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-3-dmitry.baryshkov@linaro.org
2023-01-18dt-bindings: clock: qcom,msm8996-apcc: add sys_apcs_aux clockDmitry Baryshkov
The MSM8996 CPU clock controller can make use of the sys_apcs_aux clock. Add it to the bindings. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-2-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: Add QDU1000 and QRU1000 GCC supportTaniya Das
Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Made gcc_pcie_0_pipe_clk_src use clk_regmap_phy_mux_ops] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230112204446.30236-3-quic_molvera@quicinc.com
2023-01-18Merge branch '20230112204446.30236-2-quic_molvera@quicinc.com' into HEADBjorn Andersson
2023-01-18dt-bindings: clock: Add QDU1000 and QRU1000 GCC clocksMelody Olvera
Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230112204446.30236-2-quic_molvera@quicinc.com
2023-01-18clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_namesDmitry Baryshkov
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-12-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: mmcc-apq8084: remove spdm clocksDmitry Baryshkov
SPDM is used for debug/profiling and does not have any other functionality. These clocks can safely be removed. Suggested-by: Stephen Boyd <sboyd@kernel.org> Suggested-by: Georgi Djakov <djakov@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: mmcc-apq8084: move clock parent tables downDmitry Baryshkov
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-10-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-9-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRCDmitry Baryshkov
Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-8-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_namesDmitry Baryshkov
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-7-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: move PLL clocks upDmitry Baryshkov
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-6-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-5-dmitry.baryshkov@linaro.org
2023-01-18dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084Dmitry Baryshkov
Define clock/clock-names properties of the MMCC device node to be used on APQ8084 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-4-dmitry.baryshkov@linaro.org
2023-01-18dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRCDmitry Baryshkov
Add GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-3-dmitry.baryshkov@linaro.org
2023-01-18dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-namesDmitry Baryshkov
Define clock/clock-names properties of the GCC device node to be used on APQ8084 platform. Note: the driver uses a single pcie_pipe clock, however most probably there are two pipe clocks, one from each of PCIe QMP PHYs. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-2-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: ipq8074: populate fw_name for usb3phy-sRobert Marko
Having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for usb3phy clocks in parent_data as they were missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents"). Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230108130440.670181-1-robimarko@gmail.com
2023-01-18Merge branch ↵Bjorn Andersson
'20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org' into clk-for-6.3
2023-01-18dt-bindings: clock: document SM8550 DISPCC clock controllerNeil Armstrong
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
2023-01-18clk: qcom: add the GCC driver for sa8775pShazad Hussain
Add support for the Global Clock Controller found in the QTI SA8775P platforms. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved to core_initcall(), per request of Konrad] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117180429.305266-3-brgl@bgdev.pl
2023-01-18dt-bindings: clock: Add Qualcomm SA8775P GCCBartosz Golaszewski
Add DT bindings for the GCC clock on SA8775P platforms. Add relevant DT include definitions as well. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117180429.305266-2-brgl@bgdev.pl
2023-01-17clk: qcom: smd-rpm: msm8936: Add PMIC gated RPM_SMD_XO_*Bryan O'Donoghue
The XO crystal input is buffered through the PMIC and controlled by RPM. Create the relevant clock gate representation in the RPM clock definitions. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117024846.1367794-5-bryan.odonoghue@linaro.org
2023-01-17clk: qcom: rpmh: remove duplicate IPA clock referenceArnd Bergmann
One of the ones that were recently added was already there: drivers/clk/qcom/clk-rpmh.c:578:35: error: initialized field overwritten [-Werror=override-init] 578 | [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, Fixes: aa055bf158cd ("clk: qcom: rpmh: define IPA clocks where required") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117170217.2462320-1-arnd@kernel.org
2023-01-16dt-bindings: clock: qcom,camcc-sm8250: extend clocks and power domainsKrzysztof Kozlowski
Add clocks and properties (power-domains, required-opps) already used in SM8250 DTS: sm8250-hdk.dtb: clock-controller@ad00000: clocks: [[46, 10], [44, 0], [44, 1], [45]] is too long sm8250-hdk.dtb: clock-controller@ad00000: clock-names:0: 'bi_tcxo' was expected sm8250-hdk.dtb: clock-controller@ad00000: 'power-domains', 'required-opps' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221224214404.18280-1-krzysztof.kozlowski@linaro.org
2023-01-16dt-bindings: clock: qcom,videocc: correct clocks per variantKrzysztof Kozlowski
Different SoCs come with a bit different clock inputs: sm8250-mtp.dtb: clock-controller@abf0000: clock-names:0: 'bi_tcxo' was expected sm8250-mtp.dtb: clock-controller@abf0000: clock-names: ['iface', 'bi_tcxo', 'bi_tcxo_ao'] is too long Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221224154152.43272-1-krzysztof.kozlowski@linaro.org
2023-01-16clk: qcom: Remove need for clk_ignore_unused on sc8280xpBjorn Andersson
With the transition of disabling unused clocks at sync_state, rather than late_initcall() it's now possible to drop clk_ignore_unused and unused clock disabled once client drivers have probed. Do this on SC8280XP. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113041038.4188995-1-quic_bjorande@quicinc.com
2023-01-11clk: qcom: rpmh: define IPA clocks where requiredDmitry Baryshkov
Follow the example of sc7180 and sdx55 and implement IP0 resource as clocks rather than interconnects. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109002935.244320-11-dmitry.baryshkov@linaro.org
2023-01-11clk: qcom: camcc-sm6350: Make camcc_sm6350_hws staticKonrad Dybcio
There's no reason for it not to be static, and some compilers don't like not it being that way. Make it so. Reported-by: kernel test robot <lkp@intel.com> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230107120434.1902666-1-konrad.dybcio@linaro.org
generated by cgit (git 2.34.1) at 2025-09-09 21:44:05 +0000