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2023-04-06arm64: dts: qcom: sc8280xp: simplify interrupts-extendedKrzysztof Kozlowski
The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230405060906.143058-3-krzysztof.kozlowski@linaro.org
2023-04-06arm64: dts: qcom: sm8450: label the Soundwire nodesKrzysztof Kozlowski
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230405060906.143058-2-krzysztof.kozlowski@linaro.org
2023-04-06arm64: dts: qcom: sc8280xp: label the Soundwire nodesKrzysztof Kozlowski
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230405060906.143058-1-krzysztof.kozlowski@linaro.org
2023-04-06ARM: dts: qcom: sdx65: move status properties to end of nodesAlex Elder
Move a few device tree "status" properties so that they are the last specified property, in "qcom-sdx65-mtp.dts" and "qcom-sdx65.dtsi". Note that properties must always be specified before sub-nodes. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327195605.2854123-3-elder@linaro.org
2023-04-06ARM: dts: qcom: sdx65: add IPA informationAlex Elder
Add IPA-related nodes and definitions to "sdx65.dtsi". The SMP2P nodes (ipa_smp2p_out and ipa_smp2p_in) are already present. Enable IPA in "sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327195605.2854123-2-elder@linaro.org
2023-04-06arm64: dts: imx8mp: Add display pipeline componentsMarek Vasut
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Plus. This makes the DSI display pipeline available on this SoC. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mn: Add display pipeline componentsMarek Vasut
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano. This makes the DSI display pipeline available on this SoC. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mm: Add display pipeline componentsMarek Vasut
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Mini. This makes the DSI display pipeline available on this SoC. Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06ARM: dts: imx6ull: Add chargebyte Tarragon supportStefan Wahren
This adds the support for chargebyte Tarragon, which is an Electrical Vehicle Supply Equipment (EVSE) for AC charging stations (according to IEC 61851, ISO 15118). The Tarragon board is based on an i.MX6ULL SoC and is available in 4 variants (Master, Slave, SlaveXT, Micro), which provide more or less peripherals. Supported features: * 512 MB DDR RAM * eMMC * Debug UART * 100 Mbit Ethernet * USB 2.0 Host interface * Powerline communication (QCA700x) * 2x RS485 * Digital in- and outputs (12 V) * One-Wire master for external temp sensors * 2x relay outputs * 2x motor interfaces Link: https://chargebyte.com/products/charging-station-communication/charge-control-c Signed-off-by: Stefan Wahren <stefan.wahren@chargebyte.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: freescale: imx8qxp-mek: enable cadence usb3Frank Li
Enable USB3 controller, phy and typec related nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8qxp: add cadence usb3 supportFrank Li
There are cadence usb3.0 controller in 8qxp and 8qm. Add usb3 node at common connect subsystem. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mq-librem5: add missing #clock-cellsPeng Fan
'#clock-cells' is a dependency of 'clock-output-names', following binding doc, add it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschemaPeng Fan
The dtschema requires 'grp' in the end, so update the name Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschemaPeng Fan
The dtschema requires 'grp' in the end, so update the name Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mm-emcon: update pinctrl to match dtschemaPeng Fan
The dtschema requires 'grp' in the end, so update the name Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mq-librem5: update pinctrl to match dtschemaPeng Fan
The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mm-ddr4-evk: update gpmi pinctrl to match dtschemaPeng Fan
The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mn-evk: update i2c pinctrl to match dtschemaPeng Fan
The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8mp: Add GPT blocksUwe Kleine-König
The i.MX8MP includes the same GPT blocks as the i.MX6DL. Add all 6 instances. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-06arm64: dts: imx8-apalis-v1.1: drop ci-disable-lpmPeng Fan
This is an NXP downstream property. And no binding doc, and no driver use this property. So drop it Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-04-05Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-nextConor Dooley
Merge Hal's series adding support for the new StarFive JH7110 SoC. There's a few bindings here for core components that were not picked up by the various maintainers for the subsystems (previously Palmer would pick these up via the RISC-V tree) & the first two commits in the branch are shared with the clk tree, since the dts depends on defines in the dt-binding headers. This is based on -rc2, as the board does not actually boot on -rc1 due to the bug Linus introduced. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05arm64: dts: rockchip: correct panel supplies on Odroid Go SuperKrzysztof Kozlowski
The Anbernic and Odroid Go have different panels and take differently named supplies, so move all the supplies to DTS defining actual panel to fix warnings like: rk3326-odroid-go3.dtb: panel@0: 'IOVCC-supply' is a required property rk3326-odroid-go3.dtb: panel@0: 'iovcc-supply', 'vdd-supply' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230326204520.80859-1-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Add rk3588-rock-5b analog audioCristian Ciocaltea
Add the necessary DT nodes for the Rock 5B board to enable the analog audio support provided by the Everest Semi ES8316 codec. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Link: https://lore.kernel.org/r/20230402095054.384739-6-cristian.ciocaltea@collabora.com [adapted to the fan addition I applied slightly earlier] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Add I2S rk3588 nodesCristian Ciocaltea
In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides another group of four I2S/PCM/TDM controllers. Add the DT nodes corresponding to the additional controllers. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20230402095054.384739-5-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Add rk3588s I2S nodesCristian Ciocaltea
There are five I2S/PCM/TDM controllers and two I2S/PCM controllers embedded in the RK3588 and RK3588S SoCs. Add the DT nodes corresponding to the above mentioned Rockchip controllers. Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers, which are handled via a separate patch. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20230402095054.384739-4-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588sCristian Ciocaltea
The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz instead of 1.1 GHz. Fix it. Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Reported-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588sCristian Ciocaltea
Since commit df4fdd0db475 ("dt-bindings: firmware: arm,scmi: Restrict protocol child node properties") the following dtbs_check warning is shown: rk3588-rock-5b.dtb: scmi: protocol@14: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Because adding the missing properties to firmware/arm,scmi.yaml binding document was not an acceptable solution, move SCMI_CLK_CPUB01 and SCMI_CLK_CPUB23 assigned clocks to the related CPU nodes and also add the missing SCMI_CLK_CPUL. Additionally, adjust frequency to 816 MHz for all the above mentioned assigned clocks, in order to match the firmware defaults. Suggested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20230402095054.384739-2-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: add rk3588 thermal sensorSebastian Reichel
Add thermal sensor IP, which allows monitoring temperatures at seven different places in the SoC: * Chip Center * CPU Cluster 1 (Dual A76 "Big" Cores) * CPU Cluster 2 (Dual A76 "Big" Cores) * CPU Cluster 0 (Quad A55 "Little" Cores) * Power Domain Center * Graphics Processing Unit * Neural Processing Unit Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230404154429.51601-1-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Add pwm-fan to rk3588-rock-5bCristian Ciocaltea
Add the necessary DT changes for the Rock 5B board to enable support for the PWM controlled heat sink fan. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Link: https://lore.kernel.org/r/20230404173807.490520-3-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: rockchip: Enable RTC support for Rock 5BShreeya Patel
Add DT node to enable RTC support for Rock 5B board. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Link: https://lore.kernel.org/r/20230405082711.46303-1-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-05arm64: dts: qcom: sm6115: Use the correct DSI compatibleKonrad Dybcio
Use the non-deprecated, SoC-specific DSI compatible. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307-topic-dsi_qcm-v6-9-70e13b1214fa@linaro.org
2023-04-05riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device treeEmil Renner Berthing
Add a minimal device tree for StarFive JH7110 VisionFive 2 board which has version A and version B. Support booting and basic clock/reset/pinctrl/uart drivers. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05riscv: dts: starfive: Add StarFive JH7110 pin function definitionsJianlong Huang
Add pin function definitions for StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05riscv: dts: starfive: Add initial StarFive JH7110 device treeEmil Renner Berthing
Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> [conor: squashed in the removal of the S7's non-existent mmu] Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05dt-bindings: riscv: Add SiFive S7 compatibleHal Feng
Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05dt-bindings: interrupt-controller: Add StarFive JH7110 plicEmil Renner Berthing
Add compatible string for StarFive JH7110 plic. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05dt-bindings: timer: Add StarFive JH7110 clintEmil Renner Berthing
Add compatible string for the StarFive JH7110 clint. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generatorEmil Renner Berthing
Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05dt-bindings: clock: Add StarFive JH7110 system clock and reset generatorEmil Renner Berthing
Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05arm64: tegra: Add vccmq on Jetson TX2Ben Dooks
The TX2 SoM's SDIO WiFI card is connected via mmc@3440000 however it does not look like the upstream kernel is even bothering to power this (and the regulator framework shuts down this power rail post kernel init). The issue seems to be a missing link for vccq from the MAX77620 PMIC's LDO5 which is labeled vddio_sdmmc3 (and not used anywhere else) to the mmc@3440000 node to ensure there is at leasr bus power. Note this does not fix the WiFi issue on upstream kernels, there is still something else missing that gets the BCM WiFi device to detect properly. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-05arm64: tegra: Populate USB Type-C Controller for Jetson AGX OrinJon Hunter
Add the USB Type-C controller that is present on the Jetson AGX Orin board. The ports for the Type-C controller are not populated yet, but will be added later once the USB host and device support for Jetson AGX Orin is enabled. This is based upon a patch from Wayne Chang <waynec@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-05dt-bindings: soc: samsung: exynos-pmu: allow phys as child on Exynos3 and ↵Krzysztof Kozlowski
Exynos4 Just like on Exynos5250, Exynos5420 and Exynos5433 the MIPI phy is actually part of the Power Management Unit system controller thus allow it as PMU's child. Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230207192851.549242-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-04-04arm64: dts: qcom: sc8280xp-x13s: Add bluetoothSteev Klimaszewski
The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2, add this. Signed-off-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230326233812.28058-5-steev@kali.org
2023-04-04arm64: dts: qcom: sc8280xp: Define uart2Bjorn Andersson
Add the definition for uart2 for sc8280xp devices. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230326233812.28058-4-steev@kali.org
2023-04-04arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodesManivannan Sadhasivam
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316081117.14288-19-manivannan.sadhasivam@linaro.org
2023-04-04arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodesManivannan Sadhasivam
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org
2023-04-04arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodesManivannan Sadhasivam
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316081117.14288-17-manivannan.sadhasivam@linaro.org
2023-04-04arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOsBartosz Golaszewski
Set line names for GPIO lines exposed by PMICs on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodesBartosz Golaszewski
Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-15-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: pmic: add thermal zonesBartosz Golaszewski
Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-12-brgl@bgdev.pl
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