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2023-03-30ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum ↵Tudor Ambarus
frequency sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~33%. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230328101517.1595738-5-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2023-03-30ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum ↵Tudor Ambarus
frequency sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com> # on sama5d2 ICP Link: https://lore.kernel.org/r/20230328101517.1595738-4-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2023-03-30ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum ↵Tudor Ambarus
frequency sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230328101517.1595738-3-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2023-03-30ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum ↵Tudor Ambarus
frequency sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230328101517.1595738-2-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2023-03-30arm64: dts: ti: k3-j784s4-evm: Add eMMC mmc0 supportApurva Nandan
Add support for eMMC connected to main sdhci0 instance. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230327083100.12587-1-a-nandan@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: mediatek: add ethernet support for mt8365 SoCAlexandre Mergnat
This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards. It supports power management with Energy Efficient Ethernet and Wake-on-LAN specification. Flow control is provided for half-duplex and full-duplex mode. For packet transmission and reception, the controller supports IPv4/UDP/TCP checksum offload and VLAN tag insertion. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-12-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: add mmc support for mt8365 SoCAlexandre Mergnat
There are three ports of MSDC (MMC and SD Controller), which are: - MSDC0: EMMC5.1 - MSDC1: SD3.0/SDIO3.0 - MSDC2: SDIO3.0+ Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-8-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: add pwrap support to mt8365 SoCAlexandre Mergnat
In order to use the PMIC, the pwrap support should be added to allow communication between the SoC and the PMIC. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-6-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: add mt6357 device-treeFabien Parent
This new device-tree add the regulators, rtc and keys support for the MT6357 PMIC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-5-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: Increase the size BL31 reserved memoryAlexandre Bailon
The reserved size for BL31 is too small. This has been highlighted by the MPU that now restrict access to BL31 memory to secure world only. This increase the size of the reserved memory. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-3-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: enable i2c0 for mt8365-evk boardAlexandre Mergnat
Enable the I2C0 bus provides communication with: - The integrated RT9466 Switching Battery Charger. - The integrated MT6691 LP4X buck for VDDQ. - The integrated MT6691 LP4X buck for VDD2. - The pin header, to plug external I2C devices. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221122-mt8365-i2c-support-v6-2-e1009c8afd53@baylibre.com [mb: move bias-pull-up below pinmux] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: add i2c support for mt8365 SoCAlexandre Mergnat
There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20221122-mt8365-i2c-support-v6-1-e1009c8afd53@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: ti: Enable audio on SK-AM62(-LP)Jai Luthra
Add nodes for audio codec and sound card, enable the audio serializer (McASP1) under use from SK-AM62 E2 [1] onwards and update pinmux. Keep all audio related nodes in the common dtsi as they are exactly the same between SK-AM62 and SK-AM62-LP [2]. Link: https://www.ti.com/lit/zip/sprr448 [1] Link: https://www.ti.com/lit/zip/sprr471 [2] Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-2-94332149657a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am62-main: Add McASP nodesJayesh Choudhary
Add the nodes for McASP 0-2. Use the audio-friendly 96MHz main_1_hsdivout6_clk as clock parent instead of the default 100Mhz main_2_hsdivout8_clk source. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-1-94332149657a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j784s4: Add MCSPI nodesVaishnav Achath
J784S4 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-5-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j721s2: Add MCSPI nodesVaishnav Achath
J721S2 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-4-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j7200: Add MCSPI nodesVaishnav Achath
J7200 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-3-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j721e: Add MCSPI nodesVaishnav Achath
J721E has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Co-developed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-2-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: ti: dts: Add support for AM62x LP SKAnand Gadiyar
The AM62x LP SK board is similar to the AM62x SK board, but has some not-so-minor changes that requires different device tree. The differences are mainly: - AM62x SoC in the AMC package that meets AECQ100 automotive standard. - LPDDR4 versus DDR4 on the AM62x SK. - TPS65219 PMIC instead of discrete regulators. - IO expander pin names are wired differently. - Second ethernet port is currently disabled as the boards do not have the part physically installed. - OSPI NAND vs OSPI NOR. - No WLAN chip instead a SDIO M.2 connector. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> [vigneshr@ti.com: Add PMIC node] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-3-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Refractor AM625 SK dtsAnand Gadiyar
To prepare for upcoming derivative boards based on the AM625 SK, refactor the dts file for this board into a common dtsi file that the derivative boards will inherit and retain only those parts that are different in the current dts file. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-2-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30dt-bindings: arm: ti: k3: Add compatible for AM62x LP SKVignesh Raghavendra
Add compatible for AM62x SoC based Low Power Starter Kit board[1] [1] https://www.ti.com/tool/SK-AM62-LP Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-1-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am625-sk: Add ti,vbus-divider property to usbss1Dhruva Gole
The property "ti,vbus-divider" is needed for both usbss0 and usbss1 as both USB0 and USB1 have the same external voltage divider circuit. Fixes: 2d94dfc43885 ("arm64: dts: ti: k3-am625-sk: Add support for USB") Signed-off-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230328124315.123778-2-rogerq@kernel.org Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am68-sk-base-board: Update IO EXP GPIO lines for Rev E2Sinthu Raja
Rev E2 of the AM68 SK baseboard has updated the GPIO IO expander pins functionality. To match the Rev E2 schematics, update existing IO expander GPIO line names and the corresponding node which uses the expansion(exp1) node. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Link: https://lore.kernel.org/r/20230315120934.16954-1-sinthu.raja@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Add k3-am625-beagleplayRobert Nelson
BeagleBoard.org BeaglePlay is an easy to use, affordable open source hardware single board computer based on the Texas Instruments AM625 SoC that allows you to create connected devices that work even at long distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L. Expansion is provided over open standards based mikroBUS, Grove and QWIIC headers among other interfaces. This board family can be identified by the 24c32 eeprom: [aa 55 33 ee 01 37 00 10 2e 00 42 45 41 47 4c 45 |.U3..7....BEAGLE|] [50 4c 41 59 2d 41 30 2d 00 00 30 32 30 30 37 38 |PLAY-A0-..020078|] https://beagleplay.org/ https://git.beagleboard.org/beagleplay/beagleplay Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230316152143.2438928-3-nm@ti.com Co-developed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI supportLad Prabhakar
Enable CRU, CSI on RZ/G2L SMARC EVK and tie the CSI to OV5645 sensor using Device Tree overlay. rz-smarc-cru-csi-ov5645.dtsi is created so that RZ/G2L alike EVKs can make use of it. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: r9a07g044: Add CSI and CRU nodesLad Prabhakar
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlayBiju Das
Enable sci0 node using dt overlay and disable can{0,1}-stb-hog nodes in DT overlay as its pins are shared with sci0 pins. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230321114753.75038-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30ARM: dts: r8a7790: Add PWM device nodesGeert Uytterhoeven
Add support for the 7 PWM channels provided by PWM Timers on R-Car H2, by adding device nodes describing the PWM Timers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9755b3af4296060ee31c4652def639574cbbd2fb.1679330878.git.geert+renesas@glider.be
2023-03-30ARM: dts: r8a7790: Add TPU device nodeGeert Uytterhoeven
Add support for the 4 PWM channels provided by the 16-bit Timer Pulse Unit on R-Car H2, by adding a device node describing the TPU. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/75da1e63135a3fc8a3aaafbff7139bd5d7509be3.1679330727.git.geert+renesas@glider.be
2023-03-30ARM: dts: marzen: Enable I2C supportGeert Uytterhoeven
Enable the single I2C bus available on the Marzen development board. As this bus contains an AK4643 codec, it must be limited to 100 kHz. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/77b87378397fd26f39c73f68e3ea465db6d38fb1.1679330016.git.geert+renesas@glider.be
2023-03-30ARM: dts: marzen: Add slide switchesGeert Uytterhoeven
Describe the four General Purpose Switches on the Marzen development board, so they can be used for user input and/or for wake-up from s2ram. The GPIO block on R-Car H1 does not support triggering interrupts on both edges of a changing input signal, hence one cannot use gpio-keys with gpios properties. Instead, one of two alternatives needs to be used: 1. Use gpio-keys with interrupts instead of gpios properties, at the expense of receiving only key presses (release events will be auto-generated), 2. Use gpio-keys-polled with gpios properties, at the expense of making these keys unusable as wake-up sources. As the DTS for the Marzen development board serves mainly as an example, the approach taken is to use the first alternative for the first two switches, and the second alternative for the last two switches. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f834a3c397362f2424fcae6a0c0440356208b182.1679329829.git.geert+renesas@glider.be
2023-03-30ARM: dts: r8a7779: Add PWM supportGeert Uytterhoeven
Add support for the 7 PWM channels provided by PWM Timers on R-Car H1, by describing the PWM Timers and their module clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/71622584db692f571d542ef2dcf088ce549aed3f.1679329211.git.geert+renesas@glider.be
2023-03-30dt-bindings: clock: r8a7779: Add PWM module clockGeert Uytterhoeven
Add the module clock used by the PWM Timers on the Renesas R-Car H1 (R8A7779) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1397b517fccbe716a71cfae770512ed577730a25.1679329211.git.geert+renesas@glider.be
2023-03-30arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodesBiju Das
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTSTianling Shen
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise identical to OrangePi R1 Plus. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30dt-bindings: Add doc for Xunlong OrangePi R1 Plus LTSTianling Shen
Add devicetree binding documentation for the Xunlong OrangePi R1 Plus LTS. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20230325074022.9818-4-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30arm64: dts: rockchip: Add FriendlyARM NanoPi R2CTianling Shen
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30dt-bindings: Add doc for FriendlyARM NanoPi R2CTianling Shen
Add devicetree binding documentation for the FriendlyARM NanoPi R2C. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20230325074022.9818-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30arm64: dts: rockchip: Add touchscreen support to rk3399-pinephone-proMartijn Braam
The phone has a Goodix GT1158 touchscreen, add a DT node for it. Signed-off-by: Martijn Braam <martijn@brixit.nl> Co-developed-by: Kamil Trzciński <ayufan@ayufan.eu> Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu> Co-developed-by: Ondrej Jirman <megi@xff.cz> Signed-off-by: Ondrej Jirman <megi@xff.cz> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20230328073309.1743112-3-javierm@redhat.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30arm64: dts: rockchip: Add internal display support to rk3399-pinephone-proMartijn Braam
The phone's display is using a Hannstar LCD panel. Support it by adding a panel DT node and all needed nodes (backlight, MIPI DSI, regulators, etc). Signed-off-by: Martijn Braam <martijn@brixit.nl> Co-developed-by: Kamil Trzciński <ayufan@ayufan.eu> Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu> Co-developed-by: Ondrej Jirman <megi@xff.cz> Signed-off-by: Ondrej Jirman <megi@xff.cz> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Tested-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20230328073309.1743112-2-javierm@redhat.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30dt-bindings: watchdog: rockchip: Add rockchip,rk3588-wdt stringShreeya Patel
Add rockchip,rk3588-wdt compatible string. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230328210048.195124-3-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30arm64: dts: rockchip: Enable watchdog support for RK3588Shreeya Patel
Add DT node for watchdog support in RK3588. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20230328210048.195124-2-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-03-30arm64: dts: mt8195: add display node for vdosys1Nancy.Lin
Add display node for vdosys1. Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230323013730.1378-1-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: mt8183-evb: Override vgpu/vsram_gpu constraintsAngeloGioacchino Del Regno
Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU with the platform specific vmin/vmax for the highest possible SoC binning. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Suggested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-20-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: mt8183-pumpkin: Override vgpu/vsram_gpu constraintsAngeloGioacchino Del Regno
Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU with the platform specific vmin/vmax for the highest possible SoC binning. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Suggested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-19-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: mt8186: Add GPU nodeAngeloGioacchino Del Regno
Add a GPU node for MT8186 SoC but keep it disabled. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPUAngeloGioacchino Del Regno
Enable the Mali-G57 found on this platform with the open-source Panfrost driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-17-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPUAngeloGioacchino Del Regno
Add GPU support through panfrost for the Mali-G57 GPU on MT8195 with its OPP table but keep it in disabled state. This is expected to be enabled only on boards which make use of the GPU. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-16-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domainAngeloGioacchino Del Regno
Similarly to what can be seen in MT8192, on MT8195 the mfg_core_tmp clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-15-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-03-30arm64: dts: mediatek: mt8192-asurada: Enable GPUAlyssa Rosenzweig
Enable the GPU with its power supplies described. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> [wenst@: patch split out from MT8192 GPU node patch] Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> [Angelo: Minor commit title fix] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-14-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
generated by cgit (git 2.34.1) at 2025-09-12 10:17:18 +0000