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2023-03-21arm64: dts: qcom: sa8775p: add the spi16 nodeBartosz Golaszewski
Add the SPI controller node for the interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-6-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable i2c18Bartosz Golaszewski
This enables the I2C interface on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p: add the i2c18 nodeBartosz Golaszewski
Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-4-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2Bartosz Golaszewski
Enable the second instance of the QUPv3 engine on the sa8775p-ride board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p: add the QUPv3 #2 nodeBartosz Golaszewski
Add the second instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-2-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: pm8150l: add spmi-flash-led nodeDanila Tikhonov
Add a node describing the flash block found on pm8150l. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230321182319.24958-1-danila@jiaxyga.com
2023-03-21arm64: dts: qcom: sdm845: Fix the BAM DMA engine compatible stringBhupesh Sharma
As per documentation, Qualcomm SDM845 SoC supports BAM DMA engine v1.7.4, so use the correct compatible strings. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230321190118.3327360-2-bhupesh.sharma@linaro.org
2023-03-21arm64: dts: qcom: sm8550-mtp: add pmic glink nodeNeil Armstrong
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-11-552f3b721f9e@linaro.org
2023-03-21arm64: dts: qcom: sm8450-hdk: add pmic glink nodeNeil Armstrong
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-10-552f3b721f9e@linaro.org
2023-03-21arm64: dts: qcom: sm8350-hdk: add pmic glink nodeNeil Armstrong
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-9-552f3b721f9e@linaro.org
2023-03-21arm64: dts: qcom: sm8550: add port subnodes in dwc3 nodeNeil Armstrong
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-8-552f3b721f9e@linaro.org
2023-03-21arm64: dts: qcom: sm8450: add port subnodes in dwc3 nodeNeil Armstrong
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-7-552f3b721f9e@linaro.org
2023-03-21arm64: dts: qcom: sm8350: add port subnodes in dwc3 nodeNeil Armstrong
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-6-552f3b721f9e@linaro.org
2023-03-20dt-bindings: arm: ti: Add BeaglePlayRobert Nelson
This board is based on ti,am625 https://beagleplay.org/ https://git.beagleboard.org/beagleplay/beagleplay Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230316152143.2438928-2-nm@ti.com Co-developed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII modeSiddharth Vadapalli
The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: j7200-main: Add CPSW5G nodesSiddharth Vadapalli
TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external ports and 1 host port, referred to as CPSW5G. Add device-tree nodes for CPSW5G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII modeSiddharth Vadapalli
The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e: Add CPSW9G nodesSiddharth Vadapalli
TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2GSiddharth Vadapalli
Add device tree support to enable MCU CPSW with J784S4 EVM. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315042548.1500528-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721s2-common-proc-board: Add pinmux information for ADCBhavya Kapoor
J721s2 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230316095146.498999-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62: Add watchdog nodesJulien Panis
Add nodes for watchdogs : - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Julien Panis <jpanis@baylibre.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230320165123.80561-3-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62-wakeup: Introduce RTC nodeNishanth Menon
Introduce digital RTC node in wakeup domain. Even though this has no specific battery backup supply, this on-chip RTC is used in cost-optimized board designs as a wakeup source. Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230320165123.80561-2-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support for ADC nodesBhavya Kapoor
J721s2 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230316095146.498999-2-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j784s4-main: Enable crypto acceleratorJayesh Choudhary
Add the node for SA2UL to support hardware crypto algorithms, including SHA-1/256/512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230314152611.140969-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20dt-bindings: pinctrl: k3: Deprecate header with register constantsNishanth Menon
For convenience (less code duplication), the pin controller pin configuration register values were defined in the bindings header. These are not some IDs or other abstraction layer but raw numbers used in the registers. These constants do not fit the purpose of bindings. They do not provide any abstraction, any hardware and driver independent ID. In fact, the Linux pinctrl-single driver actually do not use the bindings header at all. All of the constants were moved already to headers local to DTS (residing in DTS directory), so remove any references to the bindings header and add a warning that it is deprecated. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/linux-arm-kernel/71c7feff-4189-f12f-7353-bce41a61119d@linaro.org/ Link: https://lore.kernel.org/r/20230315155228.1566883-4-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: Use local header for pinctrl register valuesNishanth Menon
The DTS uses hardware register values directly in pin controller pin configuration and not an abstraction of any form. These definitions were previously put in the bindings header to avoid code duplication and to provide some context meaning (name), but they do not fit the purpose of bindings. Store the constants in a header next to DTS and use them instead of bindings. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/c4d53e9c-dac0-8ccc-dc86-faada324beba@linaro.org/ Link: https://lore.kernel.org/r/20230315155228.1566883-3-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20dt-bindings: net: ti: k3-am654-cpsw-nuss: Drop pinmux headerNishanth Menon
Drop the pinmux header reference as it is not used. Examples should just show the node definition. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230315155228.1566883-2-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e-sk: Remove firmware-name override for R5FAndrew Davis
The firmware name for this core should stay as the default name "j7-main-r5f0_0-fw". This is expected to by a symlink to the actual firmware file. If one wants to use a different firmware they should change where the symlink points. This is usually achieved with an update-alternative or other distro specific selection mechanisms. The actual selection is policy and does not belong in DT. Remove this name override. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230307180942.2719-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KBVignesh Raghavendra
Per AM62Ax SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am62a7 Page 1. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am625: Correct L2 cache size to 512KBVignesh Raghavendra
Per AM62x SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am625 Page 1. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15xx-osd32 SoMLeonard Göhrs
To support the detach feature, add a new mailbox channel to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. See 6257dfc1c412dcdbd76ca5fa92c8444222dbe5b0 for a patch that does the same for stm32mp15x-dkx boards. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-03-19arm64: dts: qcom: sm6115: Move SDHC node(s)'s 'pinctrl' properties to dtsBhupesh Sharma
Normally the 'pinctrl' properties of a SDHC controller and the chip detect pin settings are dependent on the type of the slots (for e.g uSD card slot), regulators and GPIO(s) available on the board(s). So, move the same from the sm6115 dtsi file to the respective board file(s). Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314074001.1873781-1-bhupesh.sharma@linaro.org
2023-03-19arm64: dts: qcom: sm6115: Move USB node's 'maximum-speed' and 'dr_mode' ↵Bhupesh Sharma
properties to dts Normally the 'maximum-speed' and 'dr_mode' properties of a USB controller + port is dependent on the type of the ports, regulators and mode change interrupt routing available on the board(s). So, move the same from the sm6115 dtsi file to respective board file(s). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314083633.1882214-3-bhupesh.sharma@linaro.org
2023-03-19arm64: dts: qcom: sm6115: Cleanup USB node's labelBhupesh Sharma
There is only one USB controller present on SM6115 / SM4250 Qualcomm SoC, so drop the numbering used with USB node's label names in the dtsi and the related sm4250-oneplus-billie2.dts. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314083633.1882214-2-bhupesh.sharma@linaro.org
2023-03-17arm64: dts: sprd: Add support for Unisoc's UMS512Chunyan Zhang
Add basic support for Unisoc's UMS512, with this patch, the board ums512-1h10 can run into console. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lore.kernel.org/r/20230306085717.420353-1-chunyan.zhang@unisoc.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-03-17ARM: dts: ixp4xx: use "okay" for statusKrzysztof Kozlowski
"okay" over "ok" is preferred for status property. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230127101832.93789-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230310231420.583121-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-03-17arm64: dts: exynos: add mmc aliasesHenrik Grimler
Add aliases for eMMC and SD card where applicable, so that assigned mmc indeces are always the same. Signed-off-by: Henrik Grimler <henrik@grimler.se> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230315212814.15908-3-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-03-17arm64: dts: exynos: drop mshc aliasesHenrik Grimler
Previously, the mshc0 alias has been necessary so that MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA are set for mshc_0/mmc_0. However, these capabilities should be described in the device tree so that we do not have to rely on the alias. The property mmc-ddr-1_8v replaces MMC_CAP_1_8V_DDR, while bus_width = <8>, which is already set for all the mshc0/mmc0 nodes, replaces MMC_CAP_8_BIT_DATA. Also drop other mshc aliases as they are not needed. Signed-off-by: Henrik Grimler <henrik@grimler.se> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230315212814.15908-2-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-03-17arm64: dts: cavium: Fix GICv3 ITS nodesRob Herring
The GICv3 ITS is an MSI controller, therefore its node name should be 'msi-controller'. The ITS node is also expected to have '#msi-cells'. Add it on Thunder as there are no users. Thunder2 uses 'msi-parent', but Robin says that should be 'msi-map' instead and I'm not sure what's correct for it. The unit-addresses of both the ITS and main GIC node on thunder2 are also wrong, so fix them while we're here. Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230208185506.2305349-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-03-16arm64: dts: qcom: sc8280xp: fix external display power domainJohan Hovold
Fix the external display controller nodes which erroneously described the controllers as belonging to CX rather than MMCX. Fixes: 19d3bb90754f ("arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316141252.2436-1-johan+linaro@kernel.org
2023-03-16arm64: dts: renesas: r8a779a0: Update CAN-FD to R-Car Gen4 compatible valueGeert Uytterhoeven
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible property in the CAN-FD device node to include the family-specific compatible value for R-Car Gen4. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9823058fa57156e88a084a4a99fc8525af1686ff.1678705389.git.geert+renesas@glider.be
2023-03-16arm64: dts: renesas: ulcb: Add I2C EEPROM for PMICGeert Uytterhoeven
Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b52c6c21a94aa7320ac0c900f7023a5dfca76a29.1678375464.git.geert+renesas@glider.be
2023-03-16arm64: dts: renesas: condor: Add I2C EEPROM for PMICGeert Uytterhoeven
Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/84971f48eca0b696f592a922268af8c150d9bae3.1678375464.git.geert+renesas@glider.be
2023-03-16ARM: dts: armadillo800eva: Add I2C EEPROM for MAC addressGeert Uytterhoeven
Add a device node for the M24C01 I2C EEPROM which serves as external storage for the Ethernet MAC address. While at it, restore sort order (by unit address) of the devices on the I2C bus. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/6d402b289fd20125d9f6f6b2a4f239aa1887daa6.1678375464.git.geert+renesas@glider.be
2023-03-15arm64: dts: qcom: msm8916: Fix tsens_mode unit addressStephan Gerhold
The reg address of the tsens_mode nvmem cell is correct but the unit address does not match (0xec vs 0xef). Fix it. No functional change. Fixes: 24aafd041fb2 ("arm64: dts: qcom: msm8916: specify per-sensor calibration cells") Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308123617.101211-1-stephan.gerhold@kernkonzept.com
2023-03-15arm64: dts: qcom: sm8550: misc style fixesNeil Armstrong
Miscellaneous DT fixes to remove spurious blank line and enhance readability. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-3-595b02067672@linaro.org
2023-03-15arm64: dts: qcom: sm8550: fix qup_spi0_cs nodeNeil Armstrong
The node is incomplete and doesn't need a subnode, add the missing properties and move everything to the root of qup-spi0-cs-state node. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-2-595b02067672@linaro.org
2023-03-15ARM: dts: qcom: sdx55-t55: Move "status" property downManivannan Sadhasivam
To align with rest of the devicetree files, let's move the "status" property down Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-11-manivannan.sadhasivam@linaro.org
2023-03-15ARM: dts: qcom: sdx55-t55: Enable PCIe RC supportManivannan Sadhasivam
Enable PCIe RC support on Thundercomm T55 board. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-10-manivannan.sadhasivam@linaro.org
2023-03-15ARM: dts: qcom: sdx55: List the property values verticallyManivannan Sadhasivam
To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-9-manivannan.sadhasivam@linaro.org
generated by cgit (git 2.34.1) at 2025-09-13 08:12:36 +0000