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2021-06-27clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-7-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: clkgen-pll: add new introduced compatibleAlain Volmat
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210331201632.24530-6-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-5-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: flexgen: add new introduced compatibleAlain Volmat
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210331201632.24530-4-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-3-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat
ODF field within the struct clkgen_pll is never used by the driver and can thus be removed. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-2-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: Support bypassing dividersPaul Cercueil
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatiblesPaul Cercueil
Add ingenic,jz4760-cgu and ingenic,jz4760b-cgu compatible strings for the JZ4760 and JZ4760B SoCs respectively. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210530164923.18134-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek
Caught this when looking at alpha-pll code. Untested but it is clear that this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL. Fixes: 691865bad627 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea
Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/d62e4f1f85c5cef05be14d9e8143e88bbddd2e0f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoCCristian Ciocaltea
Add the missing NIC and ETHERNET clock bindings constants for Actions Semi Owl S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1d0902cf073f76a1a602410061481ccb3fc36a72.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea
There are a few issues with the setup of the Actions Semi Owl S500 SoC's clock chain involving AHPPREDIV, H and AHB clocks: * AHBPREDIV clock is defined as a muxer only, although it also acts as a divider. * H clock is using a wrong divider register offset * AHB is defined as a multi-rate factor clock, but it is actually just a fixed pass clock. Let's provide the following fixes: * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition. * Use the correct register shift value in the OWL_DIVIDER definition for H clock * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an ungated OWL_COMP_FIXED_FACTOR definition. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Link: https://lore.kernel.org/r/21c1abd19a7089b65a34852ac6513961be88cbe1.1623354574.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea
The following clocks of the Actions Semi Owl S500 SoC have been defined to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, VDE, BISP, SENSOR[0-1] There are several issues involved in this approach: * 'bisp_factor_table[]' describes the configuration of a regular 8-rates divider, so its usage is redundant. Additionally, judging by the BISP clock context, it is incomplete since it maps only 8 out of 12 possible entries. * The clocks mentioned above are not identical in terms of the available rates, therefore cannot rely on the same factor table. Specifically, BISP and SENSOR* are standard 12-rate dividers so their configuration should rely on a proper clock div table, while VCE and VDE require a factor table that is a actually a subset of the one needed for DE[1-2] clocks. Let's fix this by implementing the following: * Add new factor tables 'de_factor_table' and 'hde_factor_table' to properly handle DE[1-2], VCE and VDE clocks. * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] clocks converted to OWL_COMP_DIV. * Drop the now unused 'bisp_factor_table[]'. Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since there is no reason to always keep ON those clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/e675820a46cd9930d8d576c6cae61d41c1a8416f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea
Drop the unsupported entries in the factor table used for the SD[0-2] clocks definitions on the Actions Semi Owl S500 SoC. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/196c948d708a22b8198c95f064a0f6b6820f9980.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea
Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/4714d05982b19ac5fec2ed74f54be42d8238e392.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: bd718xx: Drop BD70528 supportMatti Vaittinen
The only known BD70528 use-cases are such that the PMIC is controlled from separate MCU which is not running Linux. I am not aware of any Linux driver users. Furthermore, it seems there is no demand for this IC. Let's ease the maintenance burden and drop the driver. We can always add it back if there is sudden need for it. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Link: https://lore.kernel.org/r/937ed0828486a08e2d00bce2815d491c1c9c49b4.1621937490.git.matti.vaittinen@fi.rohmeurope.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: stm32mp1: move RCC reset controller into RCC clock driverGabriel Fernandez
RCC clock and reset controller shared same memory mapping. As RCC clock driver is now a module, the best way to register clock and reset controller is to do it in same driver. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-6-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: stm32mp1: convert to module driverGabriel Fernandez
Adds support for probe deferral in way to prepare integration of the security in RCC clock and reset drivers. Some kernel clocks will be provided by the SCMI drivers. Since RCC clock driver create clocks which parents are SCMI clocks, RCC clock driver probe can be deferred. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-5-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: stm32mp1: remove intermediate pll clocksGabriel Fernandez
This patch is to prepare STM32MP1 clocks in trusted mode. Integrate the mux clock into pll clock will facilitate to have a more coherent clock tree in no trusted / trusted mode. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-4-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clockGabriel Fernandez
'ck_rtc' has multiple clocks as input (ck_hsi, ck_lsi, and ck_hse). A divider is available only on the specific rtc input for ck_hse. This Merge will facilitate to have a more coherent clock tree in no trusted / trusted world. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-3-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clockGabriel Fernandez
This patch is to prepare STM32MP1 clocks in trusted mode. This Merge will facilitate to have a more coherent clock tree in no trusted / trusted world. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: lmk04832: add support for digital delayLiam Beguin
The digital delay allows outputs to be delayed from 8 to 1023 VCO cycles. The delay step can be as small as half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps. The digital delay value takes effect on the clock output phase after a SYNC event. This is required to support JESD204B subclass 1. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20210423004057.283926-3-liambeguin@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: add support for the lmk04832Liam Beguin
The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20210423004057.283926-2-liambeguin@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: add ti,lmk04832 bindingsLiam Beguin
Document devicetree bindings for Texas Instruments' LMK04832. The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with JEDEC JESD204B support. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20210423004057.283926-4-liambeguin@gmail.com Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: socfpga: clk-pll: Remove unused variable 'rc'Jian Xin
Fix the following build warning: drivers/clk/socfpga/clk-pll.c: In function ‘__socfpga_pll_init’: drivers/clk/socfpga/clk-pll.c:83:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable] Signed-off-by: Jian Xin <xinjian@yulong.com> Link: https://lore.kernel.org/r/20210609073742.722911-1-xinjian34324@163.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: Add camera clock controller driver for SM8250Jonathan Marek
Add support for the camera clock controller found on SM8250. Based on the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca [sboyd@kernel.org: Add UL to avoid decimal problems] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: add QCOM SM8250 camera clock bindingsJonathan Marek
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SM8250 SoC. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-3-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: add support for zonda pllJonathan Marek
Ported over from the downstream driver. Will be used by SM8250 CAMCC. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk/qcom: Remove unused variablesPu Lehui
Fix gcc '-Wunused-const-variable' warnings: drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined but not used [-Wunused-const-variable=] drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map' defined but not used [-Wunused-const-variable=] Let's remove them. Signed-off-by: Pu Lehui <pulehui@huawei.com> Link: https://lore.kernel.org/r/20210609061848.87415-1-pulehui@huawei.com Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocksBartosz Dudziak
Add compatible for rpm smd clocks, PMIC and bus clocks which are required on MSM8226 for clients to vote on. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210605104040.12960-1-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: gcc: Add support for Global Clock controller found on MSM8226Bartosz Dudziak
Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies which are different in this older chip. Register all the clocks to the framework for the clients to be able to request for them. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-3-bartosz.dudziak@snejp.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: qcom: Add MSM8226 GCC clock bindingsBartosz Dudziak
Add compatible device strings and the include files for the MSM8226 GCC. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20210418122909.71434-2-bartosz.dudziak@snejp.pl Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: Add SM6125 (TRINKET) GCC driverKonrad Dybcio
Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Mark gcc_sm6125_hws array static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driverMartin Botka
Document the newly added SM6125 GCC driver. Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-1-martin.botka@somainline.org Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: gcc: Add support for a new frequency for SC7280Taniya Das
There is a requirement to support 52MHz for qup clocks for bluetooth usecase, thus update the frequency table to support the frequency. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1624449471-9984-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen
If the bypass_reg is set, then we can return the bypass parent, however, if there is not a bypass_reg, we need to figure what the correct parent mux is. The previous code never handled the parent mux if there was a bypass_reg. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-4-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that was not being accounted for. The bypass selects between emaca_clk/emacb_clk and boot_clk. Because the bypass register offset is different between Stratix10 and Agilex/N5X, it's best to create a new function to calculate the bypass. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10: fix bypass representationDinh Nguyen
Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp, emac0/1/2) have a bypass setting that can use the boot_clk. The previous representation was not correct. Fix the representation. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10: remove noc_clkDinh Nguyen
Early documentation had a noc_clk, but in reality, it's just the noc_free_clk. Remove the noc_clk clock and just use the noc_free_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27block/mq-deadline: Remove a WARN_ON_ONCE() callBart Van Assche
The purpose of the WARN_ON_ONCE() statement in dd_insert_request() is to verify that dd_prepare_request() cleared rq->elv.priv[0]. Since dd_prepare_request() is called during request initialization but not if a request is requeued, a warning is triggered if a request is requeued. Fix this by removing the WARN_ON_ONCE() statement. This patch suppresses the following kernel warning: WARNING: CPU: 28 PID: 432 at block/mq-deadline-main.c:740 dd_insert_request+0x4d4/0x5b0 Workqueue: kblockd blk_mq_requeue_work Call Trace: dd_insert_requests+0xfa/0x130 blk_mq_sched_insert_request+0x22c/0x240 blk_mq_requeue_work+0x21c/0x2d0 process_one_work+0x4c2/0xa70 worker_thread+0x2e5/0x6d0 kthread+0x21c/0x250 ret_from_fork+0x1f/0x30 Reported-by: Sachin Sant <sachinp@linux.vnet.ibm.com> Fixes: 08a9ad8bf607 ("block/mq-deadline: Add cgroup support") Signed-off-by: Bart Van Assche <bvanassche@acm.org> Link: https://lore.kernel.org/r/20210627211112.12720-1-bvanassche@acm.org Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-06-27Linux 5.13v5.13Linus Torvalds
2021-06-28MAINTAINERS: erofs: update my email addressChao Yu
Old email address will be invalid after a few days, update it to kernel.org one. Link: https://lore.kernel.org/r/20210627133229.8025-1-chao@kernel.org Signed-off-by: Chao Yu <chao@kernel.org> Acked-by: Gao Xiang <xiang@kernel.org> Signed-off-by: Gao Xiang <xiang@kernel.org>
2021-06-27Revert "signal: Allow tasks to cache one sigqueue struct"Linus Torvalds
This reverts commits 4bad58ebc8bc4f20d89cff95417c9b4674769709 (and 399f8dd9a866e107639eabd3c1979cd526ca3a98, which tried to fix it). I do not believe these are correct, and I'm about to release 5.13, so am reverting them out of an abundance of caution. The locking is odd, and appears broken. On the allocation side (in __sigqueue_alloc()), the locking is somewhat straightforward: it depends on sighand->siglock. Since one caller doesn't hold that lock, it further then tests 'sigqueue_flags' to avoid the case with no locks held. On the freeing side (in sigqueue_cache_or_free()), there is no locking at all, and the logic instead depends on 'current' being a single thread, and not able to race with itself. To make things more exciting, there's also the data race between freeing a signal and allocating one, which is handled by using WRITE_ONCE() and READ_ONCE(), and being mutually exclusive wrt the initial state (ie freeing will only free if the old state was NULL, while allocating will obviously only use the value if it was non-NULL, so only one or the other will actually act on the value). However, while the free->alloc paths do seem mutually exclusive thanks to just the data value dependency, it's not clear what the memory ordering constraints are on it. Could writes from the previous allocation possibly be delayed and seen by the new allocation later, causing logical inconsistencies? So it's all very exciting and unusual. And in particular, it seems that the freeing side is incorrect in depending on "current" being single-threaded. Yes, 'current' is a single thread, but in the presense of asynchronous events even a single thread can have data races. And such asynchronous events can and do happen, with interrupts causing signals to be flushed and thus free'd (for example - sending a SIGCONT/SIGSTOP can happen from interrupt context, and can flush previously queued process control signals). So regardless of all the other questions about the memory ordering and locking for this new cached allocation, the sigqueue_cache_or_free() assumptions seem to be fundamentally incorrect. It may be that people will show me the errors of my ways, and tell me why this is all safe after all. We can reinstate it if so. But my current belief is that the WRITE_ONCE() that sets the cached entry needs to be a smp_store_release(), and the READ_ONCE() that finds a cached entry needs to be a smp_load_acquire() to handle memory ordering correctly. And the sequence in sigqueue_cache_or_free() would need to either use a lock or at least be interrupt-safe some way (perhaps by using something like the percpu 'cmpxchg': it doesn't need to be SMP-safe, but like the percpu operations it needs to be interrupt-safe). Fixes: 399f8dd9a866 ("signal: Prevent sigqueue caching after task got released") Fixes: 4bad58ebc8bc ("signal: Allow tasks to cache one sigqueue struct") Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Christian Brauner <christian.brauner@ubuntu.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-06-26MAINTAINERS: add entry for polarfire soc mailboxConor Dooley
Add Lewis Hanly as a maintainer for the Microchip SoC directory and the system services mailbox driver Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26dt-bindings: add bindings for polarfire soc system controllerConor Dooley
Add device tree bindings for the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mbox: add polarfire soc system controller mailboxConor Dooley
This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-18 13:46:01 +0000