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Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the (previously omitted) SCIF2 pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Define the generic R8A7745 part of the PFC device node.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add camera support to N900 dts. Also add a note about MMC & debugging.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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dra76-evm is a board based on TI's dra76 processor targeting
for infotainment systems. Adding support for this platform.
dra76-evm and dra7-evm has a similar layout except with few differences.
So create a dra7-evm-common.dtsi with similarities on dra76-evm and
dra7-evm. Include this common dtsi in both dra7-evm.dts and dra76-evm.dts
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 2 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN
Adding basic dts support for DRA76 family while reusing the
data available in dra7.dtsi, dra74x.dtsi.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add support for Moxa UC-8100-ME-T open platform
The UC-8100-ME-T computing platform is designed
for embedded data acquisition industrial applications
The features of UC-8100-ME-T series are:
* eMMC
* SPI flash
* SD slot
* 2x LAN
* 2 RS-232/422/485 ports, software-selectable
* Mini PCIe form factor with USB signal
* USB host
* EEPROM
* TPM
* Watchdog
* RTC
* User gpio-keys
* User LEDs
* User button
Signed-off-by: SZ Lin <sz.lin@moxa.com>
Acked-by: Rob Herring <robh@kernel.org>
[tony@atomide.com: fix unit adress as suggested by Rob]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add vibrator to Droid4's device tree.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Set default mode for vaudio, which may be left in standby mode
if the system is booted via kexec from Android.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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All nodes inhert "interrupt-parent" property from root
node. Removed the aforementioned property from usbhsohci,
usbhsehci, ssi_port1, ssi_port2 nodes to avoid duplication.
Signed-off-by: Karthik Tummala <karthik@techveda.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Devices using an external encoder, ESD protection and level shifter
such as tpd12s015 or ip4791cz12 have the CEC pull in the encoder
chip. And on var-som-om44, there is external pull up resistor R30.
So the internal CEC pull-up resistor needs to be disabled as otherwise
the external and internal pull are parallel making the pull value
much smaller than intended. This leads into the CEC not working as
reported by Hans Verkuil <hverkuil@xs4all.nl>.
Reported-by: Hans Verkuil <hverkuil@xs4all.nl>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add support for onboard gpio buzzer. It works using
the gpio-beeper driver. Pinmux entries for GPIO
controlling the buzzer are also added.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This patch adds the missing 32-bit enable method for SMP on BCM2836 and
BCM2837. The BCM2837 already has an enabled method, but this one only
works for 64-bit.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Eric Anholt <eric@anholt.net>
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This adds a compatible string "brcm,bcm2836-smp" for Broadcom's
BCM2836 and BCM2837 to the 32 bit ARM CPU device tree binding.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Rob Herring <robh@kernel.org>
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Add the I2C[0-5] devices to the r8a7743 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This commit enables i2c recovery, supported by the i2c core subsystem.
It defines the required GPIOs for SDA and SCL lines.
Signed-off-by: Jose Alarcon <jose.alarcon@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add support for the Toradex Apalis Evaluation Board.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add support for the Toradex Ixora V1.1 carrier board.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Migrate to using functionally-reduced I2C master contained in the DWC
HDMI. Therefore drop the GPIO bitbanging based i2cddc definition and
modify resp. pinctrl.
While at it re-order the I2C aliases to start with the generic, followed
by the camera and concluded by the power I2C one.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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gen1_i2c comment
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Split the pinctrl property for usdhc1 into a 4-bit SD interface
and an extension to 8-bit. This is required to support both 8-bit
and 4-bit interface on usdhc1 as per the carrier board.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The SD1 pinctrl-0 property is overridden but only the card detect pin
is muxed, the control and data signals are not referenced at all.
It worked because the bootloader muxed them to a sensible state though.
Fix this.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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A CMA memory pool reserved memory node is added, and is attached
to the DSP node through the 'memory-region' property on the K2G
ICE board. This area will be used for allocating virtio rings and
buffers. This node allows the DSP Memory Protection and Address
Extension (MPAX) module to be configured properly for the DSP
processor, and matches the values used on the other Keystone 2
boards for software compatibility.
The reserved memory node and the user DSP node are also marked
okay to enable the DSP on the K2G ICE board.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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A CMA memory pool reserved memory node is added, and is attached
to the DSP node through the 'memory-region' property on the K2G
EVM board. This area will be used for allocating virtio rings and
buffers. This node allows the DSP Memory Protection and Address
Extension (MPAX) module to be configured properly for the DSP
processor, and matches the values used on the other Keystone 2
boards for software compatibility.
The reserved memory node and the user DSP node are also marked
okay to enable the DSP on the 66AK2G EVM board.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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The Keystone 2 66AK2G SoC has a single TMS320C66x DSP Core
Subsystem (C66x CorePac), containing a C66x Fixed/Floating-Point
DSP Core, and 32 KB of L1P & L1D SRAMs and a 1 MB L2 SRAM. Add
the DT node for this DSP processor sub-system.
The DT node has a new property 'power-domains' and no 'clocks'
properties, and uses slightly different property values for
'resets' compared to other Keystone 2 SoCs. The processor does
not have an MMU, and uses various IPC Generation registers and
shared memory for inter-processor communication. The alias with
a stem 'rproc' has also been added for the DSP, it provides a
fixed remoteproc id for the DSP processor.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add dra7 iodelay configuration.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Add nodes for the two DCAN instances included in 66AK2G
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[d-gerlach@ti.com: add power-domains and clock information]
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[fcooper@ti.com: update subject and commit message. Misc minor updates]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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CAN driver uses the clk_get_rate call to determine the frequency of the
functional clock. OMAP based SoCs do not require the clock property since
hwmod already handles creating a "fck" clock thats accessible to drivers.
However, this isn't the case for 66AK2G which makes the clocks property
require for that SoC.
66AK2G requires a new property. Therefore, update the binding to also make
this property requirement clear. Also clarify that for OMAP based SoCs
ti,hwmod is a required property.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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The interrupt for power button is static data that comes from the
datasheet, there is no reason to need to define this value on every
board so seams reasonable put this information into the common tps65217
file.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The interrupt specifiers for USB and AC charger input are static data that
comes from the datasheet, there is no reason to need to define these values
on every board so seem reasonable put this information into the common
tps65217 file.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Replace deprecated "vmmc_aux" with the generic "vqmmc" binding for
MMC IO supply.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Linux v4.13-rc1
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The GPIO polarity for MMC1 card detect is set to '0' which means
active-high. However the polarity should be active-low. Fix it
here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The GPIO polarity for MMC1 card detect is set to '0' which means
active-high. However the polarity should be active-low. Fix it
here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This SoC is too old. It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The UniPhier AIO2013 audio system needs I2S and clock signal pins
to connect external codec chip.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The UART bindings needs specifying a SoC family, use the meson6 family
for the UART nodes like the other nodes.
Switch to the stable UART bindings for meson6 by adding a XTAL node and
using the proper compatible strings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds and enables the device-tree definitions for
both qcom,ipq4019-wifi blocks for the IPQ4019.
Support for these have been added into the ath10k driver since:
commit 280e762e9c72 ("ath10k: enable ipq4019 device probe in ahb module")
The binding documentation was added in:
commit a47aaa69de88 ("dt: bindings: add new dt entry for pre calibration in qcom, ath10k.txt")
This has been tested on an ASUS RT-AC58U (IPQ4019),
an AVM Fritz!Box 4040 (IPQ4018), a Compex WPJ428 (IPQ4028)
and a Cisco Meraki MR33 (IPQ4029).
| a000000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff [...]
| a000000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
| a000000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p,mfp,[...]
| a000000.wifi: board_file api 2 bmi_id 0:16 crc32 5773b188
| a000000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
...
| a800000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff sub 0000:0000
| a800000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
| a800000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p, [...]
| a800000.wifi: board_file api 2 bmi_id 0:17 crc32 5773b188
| a800000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Replace the obsolete compatible string for Coresight programmable
replicator with the new one.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This architecture has a pseudo random number generator
supported by the existing "qcom,prng" binding.
rngtest: bits received from input: 5795960032
rngtest: FIPS 140-2 successes: 289591
rngtest: FIPS 140-2 failures: 207
rngtest: FIPS 140-2(2001-10-10) Monobit: 25
rngtest: FIPS 140-2(2001-10-10) Poker: 28
rngtest: FIPS 140-2(2001-10-10) Runs: 91
rngtest: FIPS 140-2(2001-10-10) Long run: 67
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=244; avg=46122; max=3906250)Kibits/s
rngtest: FIPS tests speed: (min=1.327; avg=20.966; max=26.345)Mibits/s
rngtest: Program run time: 386965827 microseconds
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The node for xo and timer belong to the SoC DTS file.
Else, new board DT files may not inherit these nodes.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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