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2022-08-01scsi: ufs: ufs-pci: Correct check for RESET DSMDaniil Lunev
dsm_fns is a bitmap, and it is 0-indexed according to the check in __intel_dsm function. But common initialization was checking it as if it was 1-indexed. This patch corrects the discrepancy. This change won't break any existing calls to the function, since before the change both bits 0 and 1 were checked and needed to be set. Link: https://lore.kernel.org/r/20220728111748.v3.1.I22460c4f4a9ccf2c96c3f9bb392b409926d80b2f@changeid Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Daniil Lunev <dlunev@chromium.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-01scsi: target: core: De-RCU of se_lun and se_lun aclDmitry Bogdanov
se_lun and se_lun_acl are immutable pointers of struct se_dev_entry. Remove RCU usage for access to those pointers. Link: https://lore.kernel.org/r/20220727214125.19647-3-d.bogdanov@yadro.com Reviewed-by: Mike Christie <michael.christie@oracle.com> Signed-off-by: Dmitry Bogdanov <d.bogdanov@yadro.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-01scsi: target: core: Fix race during ACL removalDmitry Bogdanov
Under huge load there is a possibility of race condition in updating se_dev_entry object in ACL removal procedure: NIP [c0080000154093d0] transport_lookup_cmd_lun+0x1f8/0x3d0 [target_core_mod] LR [c00800001542ab34] target_submit_cmd_map_sgls+0x11c/0x300 [target_core_mod] Call Trace: target_submit_cmd_map_sgls+0x11c/0x300 [target_core_mod] target_submit_cmd+0x44/0x60 [target_core_mod] tcm_qla2xxx_handle_cmd+0x88/0xe0 [tcm_qla2xxx] qlt_do_work+0x2e4/0x3d0 [qla2xxx] process_one_work+0x298/0x5c Despite usage of RCU primitives with deve->se_lun pointer, it has not become dereference-safe because deve->se_lun is updated and not synchronized with a reader. That change might be in a release function called by synchronize_rcu(). But, in fact, there is no point in setting that pointer to NULL for deleting deve. All access to deve->se_lun is already under rcu_read_lock. And either deve->se_lun is always valid or deve is not valid itself and will not be found in the list_for_*. The same applicable for deve->se_lun_acl too. So a better solution is to remove that NULLing. Link: https://lore.kernel.org/r/20220727214125.19647-2-d.bogdanov@yadro.com Reviewed-by: Mike Christie <michael.christie@oracle.com> Signed-off-by: Dmitry Bogdanov <d.bogdanov@yadro.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-01scsi: ufs: core: Correct ufshcd_shutdown() flowPeter Wang
After ufshcd_wl_shutdown() set device power off and link off, ufshcd_shutdown() could turn off clock/power. Also remove pm_runtime_get_sync. The reason why it is safe to remove pm_runtime_get_sync() is because: - ufshcd_wl_shutdown() -> pm_runtime_get_sync() will resume hba->dev too. - device resume(turn on clk/power) is not required, even if device is in RPM_SUSPENDED. Link: https://lore.kernel.org/r/20220727030526.31022-1-peter.wang@mediatek.com Fixes: b294ff3e3449 ("scsi: ufs: core: Enable power management for wlun") Cc: <stable@vger.kernel.org> # 5.15.x Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Peter Wang <peter.wang@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-01scsi: ufs: core: Increase the maximum data buffer sizeBart Van Assche
Measurements for one particular UFS controller + UFS device show a 25% higher read bandwidth if the maximum data buffer size is increased from 512 KiB to 1 MiB. Hence increase the maximum size of the data buffer associated with a single request from SCSI_DEFAULT_MAX_SECTORS (1024) * 512 bytes = 512 KiB to 1 MiB. Notes: - The maximum data buffer size supported by the UFSHCI specification is 65535 * 256 KiB or about 16 GiB. - The maximum data buffer size for READ(10) commands is 65535 logical blocks. To transfer more than 65535 * 4096 bytes = 255 MiB with a single SCSI command, the READ(16) command is required. Support for READ(16) is optional in the UFS 3.1 and UFS 4.0 standards. Link: https://lore.kernel.org/r/20220726225232.1362251-1-bvanassche@acm.org Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Avri Altman <avri.altman@wdc.com> Cc: Bean Huo <beanhuo@micron.com> Cc: Stanley Chu <stanley.chu@mediatek.com> Tested-by: Avri Altman <avri.altman@wdc.com> Acked-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-01scsi: lpfc: Check the return value of alloc_workqueue()William Dean
The function alloc_workqueue() in lpfc_sli4_driver_resource_setup() can fail, but there is no check of its return value. The return value should be checked. Link: https://lore.kernel.org/r/20220723064027.2956623-1-williamsukatube@163.com Fixes: 3cee98db2610 ("scsi: lpfc: Fix crash on driver unload in wq free") Reported-by: Hacash Robot <hacashRobot@santino.com> Reviewed-by: James Smart <jsmart2021@gmail.com> Signed-off-by: William Dean <williamsukatube@gmail.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2022-08-01cxl/region: Stop initializing interleave granularityDan Williams
In preparation for a patch that validates that the region ways setting is compatible with the granularity setting, the initial granularity setting needs to start at zero to indicate "unset". Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://lore.kernel.org/r/165853777484.2430596.3423921169034844397.stgit@dwillia2-xfh.jf.intel.com [djbw: fix up unused variable] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-08-01cxl/hdm: Fix DPA reservation vs cxl_endpoint_decoder lifetimeDan Williams
After adding support for emulating platform firmware established DPA reservations, the cxl-topology.sh [1] unit test started crashing with the following signature: general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b6bc3: 0000 [#1] PREEMPT SMP [..] RIP: 0010:to_cxl_port+0x8/0x60 [cxl_core] [..] Call Trace: <TASK> __cxl_dpa_release+0x1b/0xd0 [cxl_core] cxl_dpa_release+0x1d/0x30 [cxl_core] release_nodes+0x63/0x90 devres_release_all+0x88/0xc0 ...i.e. a use after free of a 'struct cxl_endpoint_decoder' object. This results from the ordering of init_hdm_decoder() before add_hdm_decoder() where, at release time, the decoder is unregistered and released before the DPA reservation. Fix this by extending the life of the object until all DPA reservations have been released which also preserves platform decoder settings being settled by the time the decoder is published in sysfs (KOBJ_ADD time). Note that the @len == 0 case in __cxl_dpa_reserve() is avoided in practice as this function is only called for committed decoders and new non-zero DPA allocations. Link: https://github.com/pmem/ndctl/blob/pending/test/cxl-topology.sh [1] Fixes: 9c57cde0dcbd ("cxl/hdm: Enumerate allocated DPA") Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Link: https://lore.kernel.org/r/165896020625.3546860.12390103413706292760.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-08-01cxl/acpi: Minimize granularity for x1 interleavesDan Williams
The kernel enforces that region granularity is >= to the top-level interleave-granularity for the given CXL window. However, when the CXL window interleave is x1, i.e. non-interleaved at the host bridge level, then the specified granularity does not matter. Override the window specified granularity to the CXL minimum so that any valid region granularity is >= to the root granularity. Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://lore.kernel.org/r/165853776917.2430596.16823264262010844458.stgit@dwillia2-xfh.jf.intel.com [djbw: add CXL_DECODER_MIN_GRANULARITY per vishal] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-08-01cxl/region: Delete 'region' attribute from root decodersDan Williams
For switch and endpoint decoders the relationship of decoders to regions is 1:1. However, for root decoders the relationship is 1:N. Also, regions are already children of root decoders, so the 1:N relationship is observed by walking the following glob: /sys/bus/cxl/devices/$decoder/region* Hide the vestigial 'region' attribute for root decoders. Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://lore.kernel.org/r/165853776328.2430596.4647259305040072751.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-08-01cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams
In support of CXL unit tests in the ndctl project, arrange for the cxl_acpi driver to load in response to the registration of cxl_test devices. Reported-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Vishal Verma <vishal.l.verma@intel.com> Link: https://lore.kernel.org/r/165853775783.2430596.13637998086505316619.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-08-01cxl/region: decrement ->nr_targets on error in cxl_region_attach()Dan Carpenter
The ++ needs a match -- on the clean up path. If the p->nr_targets value gets to be more than 16 it leads to uninitialized data in cxl_port_setup_targets(). drivers/cxl/core/region.c:995 cxl_port_setup_targets() error: uninitialized symbol 'eiw'. Fixes: 27b3f8d13830 ("cxl/region: Program target lists") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YuepCvUAoCtdpcoO@kili Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-08-01Merge tag 'qcom-clk-for-5.20' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Introduces support for the camera clock controller in SM8450 and the display and gpu clock controllers in SM8350. - Various fixes, new clocks and USB GDSCs are introduced for IPQ8074 and for MSM8939 a series of fixes for issues introduced by inheriting the MSM8916 GCC driver is introduced. - Support for a new type of voteable GDSCs are introduced and put in use for the SC8280XP PCIe GDSCs. SC8280XP pipe clocks transitioned to the new phy-mux implementation. - MSM8996 GCC, the RPM clock driver and some clocks in MSM8994 GCC are transitioned to use parent_data. - The topology for Titan (camera) GDSCs on SDM845 and SM8250 are corrected and MSM8916 gains more possible frequencies for its GP clocks. - The GCC and tsens handling on MSM8960 is reworked to mimic the design in IPQ8074 and allow the GCC driver to probe earlier. - The regulator based mmcx supply for dispcc and videocc is dropped, as the only upstream target that adapted this interface was transitioned several kernel versions ago. - GDSCs found to be enabled at boot will now reflect in the enable count of the supply, as was done with the regulator supplies previously. * tag 'qcom-clk-for-5.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (62 commits) clk: qcom: gcc-msm8994: use parent_hws for gpll0/4 clk: qcom: clk-rpm: convert to parent_data API dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled clk: qcom: Drop mmcx gdsc supply for dispcc and videocc clk: qcom: fix build error initializer element is not constant dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources clk: qcom: add support for SM8350 DISPCC clk: qcom: add support for SM8350 GPUCC clk: qcom: add camera clock controller driver for SM8450 SoC clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description ...
2022-08-01dt-bindings: PCI: host-generic-pci: Allow IOMMU and MSI propertiesRob Herring
Allow 'iommu-map', 'iommu-map-mask', and 'msi-parent' properties for generic host. This fixes unevaluated property warnings on Arm Juno, AMD Seattle, and FSL LS1028a. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220728175137.1172841-1-robh@kernel.org
2022-08-01PCI: imx6: Support more than Gen2 speed link modeRichard Zhu
Support more than Gen2 speed link mode, since i.MX8MP PCIe supports up to Gen3 link speed. Link: https://lore.kernel.org/r/1658287576-26908-1-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Set PCIE_DBI_RO_WR_EN before writing DBI registersRichard Zhu
The PCIE_DBI_RO_WR_EN bit should be set when write some DBI registers. To make sure that the DBI registers are writable, set the PCIE_DBI_RO_WR_EN properly when writing the DBI registers. Link: https://lore.kernel.org/r/1652866528-13220-1-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Reformat suspend callback to keep symmetric with resumeRichard Zhu
Create imx6_pcie_stop_link() and imx6_pcie_host_exit() functions. Encapsulate clocks, regulators disables and PHY uninitialization into imx6_pcie_host_exit(). To keep suspend/resume symmetric as much as possible, invoke these two new created functions in suspend callback. To be symmetric with imx6_pcie_host_exit(), move imx6_pcie_clk_enable() to imx6_pcie_host_init() from imx6_pcie_deassert_core_reset(). Link: https://lore.kernel.org/r/1657783869-19194-18-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Move the imx6_pcie_ltssm_disable() earlierRichard Zhu
Move the imx6_pcie_ltssm_disable() earlier and place it just behind the imx6_pcie_ltssm_enable(), since it might not be only used by suspend callback directly. To be symmetric with imx6_pcie_ltssm_enable(), add the IMX6Q and IMX8MQ switch cases in imx6_pcie_ltssm_disable(). Link: https://lore.kernel.org/r/1657783869-19194-17-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Disable clocks in reverse order of enableBjorn Helgaas
imx6_pcie_clk_enable() enables clocks in the order: pcie_phy pcie_bus pcie imx6_pcie_enable_ref_clk Change imx6_pcie_clk_disable() to disable them in the reverse order. Link: https://lore.kernel.org/r/1657783869-19194-16-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2022-08-01PCI: imx6: Do not hide PHY driver callbacks and refine the error handlingRichard Zhu
Move the phy_power_on() to host_init from imx6_pcie_clk_enable(). Move the phy_init() to host_init from imx6_pcie_deassert_core_reset(). Refine the error handling in imx6_pcie_host_init() accordingly. Link: https://lore.kernel.org/r/1657783869-19194-15-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Reduce resume time by only starting link if it was up before suspendRichard Zhu
i.MX PCIe doesn't support hotplug. During resume, only start PCIe link training when the link was up before system suspend to avoid the long latency in the link training period. Link: https://lore.kernel.org/r/1657783869-19194-14-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Mark the link down as non-fatal errorRichard Zhu
If the PCIe link is down, return zero from imx6_pcie_start_link() so the driver will probe successfully. Link: https://lore.kernel.org/r/1657783869-19194-13-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Move regulator enable out of imx6_pcie_deassert_core_reset()Richard Zhu
Move regulator enable out of imx6_pcie_deassert_core_reset(), since the regulator_enable() has nothing to do with imx6_pcie_deassert_core_reset(). Link: https://lore.kernel.org/r/1657783869-19194-12-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Turn off regulator when system is in suspend modeRichard Zhu
The driver should undo any enables it did itself. The regulator disable shouldn't be basing decisions on regulator_is_enabled(). Move the regulator_disable to the suspend function, turn off regulator when the system is in suspend mode. Link: https://lore.kernel.org/r/1657783869-19194-11-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: imx6: Call host init function directly in resumeRichard Zhu
Call imx6_pcie_host_init() instead of duplicating codes in resume. Note that this also means we do MPLL setup again during resume, which we didn't do before. [bhelgaas: add MPLL setup note, pointed out by Lucas] Link: https://lore.kernel.org/r/1657783869-19194-10-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Disable i.MX6QDL clock when disabling ref clocksRichard Zhu
When disabling PCIe clocks, disable i.MX6QDL ref clock too. Link: https://lore.kernel.org/r/1657783869-19194-9-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Propagate .host_init() errors to callerRichard Zhu
Since dw_pcie_host_init() checks for errors from ops->host_init(), check for errors when enabling power regulators and clocks and return them. [bhelgaas: commit log] Link: https://lore.kernel.org/r/1657783869-19194-8-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Collect clock enables in imx6_pcie_clk_enable()Richard Zhu
Encapsulate the i.MX PCIe clock enable operations into one standalone function, imx6_pcie_clk_enable(). No functional change intended. [bhelgaas: split pure code moves into separate patches] Link: https://lore.kernel.org/r/1657783869-19194-7-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Factor out ref clock disable to match enableBjorn Helgaas
The PCIe ref clocks are specific to different variants. The enables are already split out into imx6_pcie_enable_ref_clk(), but the disables were combined with the more generic bus/phy/pcie clock disables in imx6_pcie_clk_disable(). Split out the variant-specific disables into imx6_pcie_disable_ref_clk() to match imx6_pcie_enable_ref_clk(). No functional change intended. Link: https://lore.kernel.org/r/1657783869-19194-6-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2022-08-01PCI: imx6: Move imx6_pcie_clk_disable() earlierRichard Zhu
Move imx6_pcie_clk_disable() earlier to be near other clock-related functions. No functional change intended. [bhelgaas: reorder patch so pure moves are earlier] Link: https://lore.kernel.org/r/1657783869-19194-5-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2022-08-01PCI: imx6: Move imx6_pcie_enable_ref_clk() earlierBjorn Helgaas
Move imx6_pcie_enable_ref_clk() earlier so it's not in the middle between imx6_pcie_assert_core_reset() and imx6_pcie_deassert_core_reset(). No functional change intended. Link: https://lore.kernel.org/r/1657783869-19194-4-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2022-08-01PCI: imx6: Move PHY management functions togetherBjorn Helgaas
Collect imx6_pcie_init_phy(), imx7d_pcie_wait_for_phy_pll_lock(), and imx6_setup_phy_mpll() earlier with other PHY-related code. No functional change intended. Link: https://lore.kernel.org/r/1657783869-19194-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2022-08-01PCI: imx6: Move imx6_pcie_grp_offset(), imx6_pcie_configure_type() earlierBjorn Helgaas
Move imx6_pcie_grp_offset() and imx6_pcie_configure_type() earlier in the file since they depend on nothing and are used by several other functions that will be moved earlier. No functional change intended. Link: https://lore.kernel.org/r/1657783869-19194-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2022-08-01PCI: imx6: Convert to NOIRQ_SYSTEM_SLEEP_PM_OPS()Bjorn Helgaas
Replace SET_NOIRQ_SYSTEM_SLEEP_PM_OPS() with NOIRQ_SYSTEM_SLEEP_PM_OPS(), which has the advantage that the compiler always sees the PM callbacks as referenced, so they don't need to be wrapped with "#ifdef CONFIG_PM_SLEEP" or tagged with "__maybe_unused" to avoid "defined but not used" warnings. See 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones"). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2022-08-01PCI: exynos: Correct generic PHY usageMarek Szyprowski
The proper initialization for generic PHYs is to call first phy_init(), then phy_power_on(). While touching this, remove the phy_reset() call. It is just a left-over from the obsoleted Exynos5440 support and the current exynos-pcie PHY driver doesn't even support this function. It is also rarely used by other drivers. Link: https://lore.kernel.org/r/20220628220409.26545-2-m.szyprowski@samsung.com Reported-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-08-01phy: samsung: phy-exynos-pcie: sanitize init/power_on callbacksMarek Szyprowski
The exynos-pcie driver called phy_power_on() before phy_init() for some historical reasons. However the generic PHY framework assumes that the proper sequence is to call phy_init() first, then phy_power_on(). The operations done by both functions should be considered as one action and as such they are called by the exynos-pcie driver (without doing anything between them). The initialization is just a sequence of register writes, which cannot be altered without breaking the hardware operation. To match the generic PHY framework requirement, simply move all register writes to the phy_init()/phy_exit() and drop power_on()/power_off() callbacks. This way the driver will also work with the old (incorrect) PHY initialization call sequence. Link: https://lore.kernel.org/r/20220628220409.26545-1-m.szyprowski@samsung.com Reported-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-By: Vinod Koul <vkoul@kernel.org>
2022-08-01dt-bindings: PCI: qcom: Support additional MSI vectorsDmitry Baryshkov
On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Link: https://lore.kernel.org/r/20220707134733.2436629-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2022-08-01PCI: dwc: Handle MSIs routed to multiple GIC interruptsDmitry Baryshkov
On some Qualcomm platforms each group of 32 MSI vectors is routed to a separate GIC interrupt. Implement support for such configurations by parsing "msi0" ... "msiX" interrupts and attaching them to the chained handler. Note that if DT doesn't list an array of MSI interrupts and uses a single "msi" IRQ, the driver will limit the number of supported MSI vectors to 32. Link: https://lore.kernel.org/r/20220707134733.2436629-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Convert struct pcie_port.msi_irq to an arrayDmitry Baryshkov
The Qualcomm DWC PCIe controller supports more than 32 MSI interrupts, but they are routed to separate interrupts in groups of 32 vectors. To support this configuration, change the msi_irq field to an array. Let the DWC core handle all interrupts that were set in this array. [bhelgaas: reorder, drop "irq" temporary to make patch cleaner] Link: https://lore.kernel.org/r/20220707134733.2436629-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Split MSI IRQ parsing/allocation to a separate functionDmitry Baryshkov
Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separate function. [bhelgaas: reorder patch earlier] Link: https://lore.kernel.org/r/20220707134733.2436629-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()Dmitry Baryshkov
The dwc-based drivers set pp->msi_irq to -ENODEV if they do not want the dwc core to do anything with pp->msi_irq. dw_pcie_host_init() sets the handler and data when "pp->msi_irq > 0", so use the same condition when removing the handler and data in dw_pcie_free_msi(). Link: https://lore.kernel.org/r/20220707134733.2436629-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Use the bitmap API to allocate bitmapsChristophe JAILLET
Use devm_bitmap_zalloc() instead of hand-writing them. It is less verbose and it improves the semantic. Link: https://lore.kernel.org/r/bc6586a603abc0db7d4531308b698fbe7a6d7083.1657375829.git.christophe.jaillet@wanadoo.fr Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: dwc: Fix MSI msi_msg DMA mappingWill McVicker
As of 07940c369a6b ("PCI: dwc: Fix MSI page leakage in suspend/resume"), the PCIe designware host driver has been using the driver data allocation for the msi_msg DMA mapping which can result in a DMA_MAPPING_ERROR due to the DMA overflow check in dma_direct_map_page() when the address is greater than 32 bits (reported in [1]). The commit was trying to address a memory leak on suspend/resume by moving the MSI mapping to dw_pcie_host_init(), but subsequently dropped the page allocation thinking it wasn't needed. To fix the DMA mapping issue as well as make msi_msg DMA'able, switch back to allocating a 32-bit page for the msi_msg. To avoid the suspend/resume leak, allocate the page in dw_pcie_host_init() since that shouldn't be called during suspend/resume. [1] https://lore.kernel.org/all/Yo0soniFborDl7+C@google.com/ Signed-off-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-08-01PCI: dwc: Check iATU in/outbound range setup statusSerge Semin
Make the DWC PCIe RC/EP safer and more verbose for invalid or failed inbound and outbound iATU window setups. Silently ignoring iATU regions setup errors may cause unpredictable errors. For instance if a cfg or IO window fails to be activated, then any CFG/IO requested won't reach target PCIe devices and the corresponding accessors will return platform-specific random values. [bhelgaas: trim commit log] Link: https://lore.kernel.org/r/20220624143947.8991-15-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Validate iATU outbound mappings against hardware constraintsSerge Semin
Make __dw_pcie_prog_outbound_atu() check the requested region base and size against what the hardware can support. Return error if the region is not correctly aligned or of a supported size. [bhelgaas: commit log] Link: https://lore.kernel.org/r/20220624143947.8991-14-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Add iATU regions size detection procedureSerge Semin
The DWC PCIe RC/EP/DM IP core configuration parameters determine the number of inbound and outbound iATU windows, alignment requirements (which is also the minimum window size), minimum and maximum sizes. If internal ATU is enabled, the former settings are determined by CX_ATU_MIN_REGION_SIZE; the latter are determined by CX_ATU_MAX_REGION_SIZE. Determine the required alignment and maximum size supported by the controller and log it to help verify whether the requested inbound or outbound memory mappings can be fully created. Note 1. The extended iATU regions have been supported since DWC PCIe v4.60a. There is no need in testing the upper limit register availability for the older cores. Note 2. The regions alignment is determined with using the fls() method since the lower four bits of the ATU Limit register can be occupied with the Circular Buffer Increment setting, which can be initialized with zeros. Link: https://lore.kernel.org/r/20220624143947.8991-13-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Simplify in/outbound iATU setup methodsSerge Semin
Previously __dw_pcie_prog_outbound_atu() duplicated a lot of code between the iatu_unroll_enabled version and the PCIE_ATU_VIEWPORT version: __dw_pcie_prog_outbound_atu if (iatu_unroll_enabled) dw_pcie_prog_outbound_atu_unroll dw_pcie_writel_ob_unroll(PCIE_ATU_UNR_LOWER_BASE, ...) dw_pcie_writel_ob_unroll(PCIE_ATU_UNR_UPPER_BASE, ...) ... return dw_pcie_writel_dbi(PCIE_ATU_VIEWPORT, ...) dw_pcie_writel_dbi(PCIE_ATU_LOWER_BASE, ...) dw_pcie_writel_dbi(PCIE_ATU_UPPER_BASE, ...) ... Unify those by pushing the unroll address computation and viewport selection down into dw_pcie_writel_atu() so we can use the same dw_pcie_writel_atu_ob() accessor for both paths: __dw_pcie_prog_outbound_atu dw_pcie_writel_atu_ob(PCIE_ATU_LOWER_BASE, ...) dw_pcie_writel_atu dw_pcie_select_atu # new if (iatu_unroll_enabled) return pci->atu_base + PCIE_ATU_UNROLL_BASE(...) dw_pcie_writel_dbi(PCIE_ATU_VIEWPORT, ...) return pci->atu_base dw_pcie_write(base + reg) dw_pcie_writel_atu_ob(PCIE_ATU_UPPER_BASE, ...) ... In the non-unroll case, this does involve more MMIO writes to PCIE_ATU_VIEWPORT, but it's mainly in initialization paths and the code simplification is significant. [bhelgaas: commit log, simplify dw_pcie_select_atu()] Link: https://lore.kernel.org/r/20220624143947.8991-12-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2022-08-01PCI: dwc: Drop enum dw_pcie_region_type in favor of PCIE_ATU_REGION_DIR_IB/OBSerge Semin
Previously callers of dw_pcie_disable_atu() supplied enum dw_pcie_region_type (DW_PCIE_REGION_INBOUND, DW_PCIE_REGION_OUTBOUND), which dw_pcie_disable_atu() converted to the PCIE_ATU_REGION_DIR_IB or PCIE_ATU_REGION_DIR_OB values needed to program the ATU registers. Simplify the code by dropping the dw_pcie_region_type enum and passing PCIE_ATU_REGION_DIR_IB or PCIE_ATU_REGION_DIR_OB directly. Reorder dw_pcie_disable_atu() arguments to (dir, index) since "index" indicates an ATU window in the regions of the corresponding direction. [bhelgaas: commit log] Link: https://lore.kernel.org/r/20220624143947.8991-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Drop enum dw_pcie_as_type in favor of PCIE_ATU_TYPE_MEM/IOSerge Semin
Previously dw_pcie_ep_set_bar() converted the BAR PCI_BASE_ADDRESS_SPACE bit to the internal dw_pcie_as_type enum (DW_PCIE_AS_MEM, DW_PCIE_AS_IO) and passed it down to dw_pcie_prog_inbound_atu(), which converted the enum to the PCIE_ATU_TYPE_MEM/PCIE_ATU_TYPE_IO values needed to program the ATU registers. Simplify the code by dropping the dw_pcie_as_type enum and passing PCIE_ATU_TYPE_MEM or PCIE_ATU_TYPE_IO directly. Reorder inbound ATU function arguments to match the outbound functions, with address-related parameters at the end. [bhelgaas: commit log] Link: https://lore.kernel.org/r/20220624143947.8991-10-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-08-01PCI: dwc: Add dw_pcie_ops.host_deinit() callbackSerge Semin
dw_pcie_host_init() calls the dw_pcie_ops.host_init() callback to do platform-specific host initialization. Add a dw_pcie_ops.host_deinit() callback to perform the corresponding cleanups in dw_pcie_host_deinit() and in dw_pcie_host_init() failure paths. Link: https://lore.kernel.org/r/20220624143947.8991-9-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-15 06:15:24 +0000