summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2015-07-09drm/radeon: disable vce init on cayman (v2)Alex Deucher
Cayman does not have vce. There were a few places in the shared cayman/TV code where we were trying to do vce stuff. v2: remove -ENOENT check Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09drm/amdgpu: fix timeout calculationChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09drm/radeon: check if BO_VA is set before adding it to the invalidation listChristian König
Otherwise we try to clear BO_VAs without an address. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91141 Signed-off-by: Christian König <christian.koenig@amd.com> Test-by: hadack@gmx.de Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09drm/radeon: allways add the VM clear duplicateChristian König
We need to allways add the VM clear duplicate of the BO_VA, no matter what the old status was. Signed-off-by: Christian König <christian.koenig@amd.com> Test-by: hadack@gmx.de Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09Revert "Revert "drm/radeon: dont switch vt on suspend""Alex Deucher
This reverts commit ac9134906b3f5c2b45dc80dab0fee792bd516d52. We've fixed the underlying problem with cursors, so re-enable this.
2015-07-09drm/radeon: Fold radeon_set_cursor() into radeon_show_cursor()Michel Dänzer
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09drm/radeon: unpin cursor BOs on suspend and pin them again on resume (v2)Grigori Goronzy
Everything is evicted from VRAM before suspend, so we need to make sure all BOs are unpinned and re-pinned after resume. Fixes broken mouse cursor after resume introduced by commit b9729b17. [Michel Dänzer: Add pinning BOs on resume] v2: [Alex Deucher: merge cursor unpin into fb unpin loop] Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=100541 Cc: stable@vger.kernel.org Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: Grigori Goronzy <greg@chown.ath.cx> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09drm/radeon: Clean up reference counting and pinning of the cursor BOsMichel Dänzer
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in radeon_crtc_cursor_set2, and use radeon_crtc->cursor_addr in radeon_set_cursor. This fixes radeon_cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Cc: stable@vger.kernel.org Reviewed-by: Grigori Goronzy <greg@chown.ath.cx> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-09ARM: mvebu: update EEPROM description of Armada 388 GPThomas Petazzoni
Contrary to what the Device Tree indicates, the EEPROM at 0x54 is not populated, so we get rid of this comment. However, there is an EEPROM at 0x57, so we add support for this AT24C64 EEPROM: $ hexdump -C /sys/bus/i2c/devices/0-0057/eeprom 00000000 0c ff f3 ff ff ff ff ff ff ff ff ff ff ff ff ff |................| 00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00002000 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-07-09ARM: mvebu: fix description of pwr-sata0 regulator on Armada 388 GPThomas Petazzoni
This regulator was lacking the reference to the GPIO that controls it, and the regulator-min-microvolt and regulator-max-microvolt properties. Thanks to this commit, the pwr-sata0 regulator now looks more like the other pwr-sata{1,2,3} regulators in the same Device Tree, with of course the exception of a different GPIO reference. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-07-09ARM: dts: add buffalo linkstation ls-wvl/vlRoger Shimizu
Add dts file to support Buffalo Linkstation LS-WVL and LS-VL, which are 3.5" HDD NAS in 2-bay and 1-bay respectively. [gregory.clement@free-electrons.com: fix typo in pmx-led-function-red] Signed-off-by: Roger Shimizu <rogershimizu@gmail.com> Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-07-09ARM: dts: add buffalo linkstation ls-wxl/wsxlRoger Shimizu
Add dts file to support Buffalo Linkstation LS-WXL and LS-WSXL, which are 2-bay NAS with 3.5" and 2.5" HDD respectively. Signed-off-by: Roger Shimizu <rogershimizu@gmail.com> Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-07-09ARM: mvebu: use DT properties to fine-tune the L2 configurationThomas Petazzoni
In order to optimize the L2 cache performance, this commit adjusts the configuration of the L2 on the Cortex-A9 based Marvell EBU processors (Armada 375, 38x and 39x), using the appropriate DT properties. We enable double linefill, incr double linefill, data prefetch and disable double linefill on wrap. This matches the configuration that was fine tuned in the Marvell BSP. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-07-09ARM: mvebu: use armada-380-xor on Armada 38x and 39xThomas Petazzoni
The Armada 38x and 39x SoC support have an updated XOR hardware block compared to previous SoCs. These features can be enabled by using the 'armada-380-xor' compatible string, available since commit 6f166312c6ea ("dmaengine: mv_xor: add support for a38x command in descriptor mode"). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-07-09drm/amdkfd: validate pdd where it acquired firstManinder Singh
Currently pdd is validate after dereferencing it, which is not correct, Thus validate pdd before its first use. Signed-off-by: Maninder Singh <maninder1.s@samsung.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
2015-07-09Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit"Markos Chandras
This reverts commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e. SMP/CPS is now supported on 64bit cores. Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10592/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: cps-vec: Use macros for various arithmetics and memory operationsMarkos Chandras
Replace lw/sw and various arithmetic instructions with macros so the code can work on 64-bit kernels as well. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0Markos Chandras
In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0 so 64-bit kernels can be supported. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10590/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bitMarkos Chandras
The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This breaks the build on 64-bit. As a result of which, use the pseudo-registers ta0-ta3 to make the code compatible with 64-bit. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10589/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2Markos Chandras
mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2 in preparation for 64-bit CPS support. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10588/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LAMarkos Chandras
The PTR_LA macro will pick the correct "la" or "dla" macro to load an address to a register. This gets rids of the following warnings (and others) when building a 64-bit CPS kernel: arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address [...] Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10587/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer castingMarkos Chandras
Commit 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") added hotplug support in the SMP/CPS implementation but it introduced a few build problems on 64-bit kernels due to pointer being casted to and from 'int' C types. We fix this problem by using 'unsigned long' instead which should match the size of the pointers in 32/64-bit kernels. Finally, we fix the comment since the CM base address is loaded to v1($3) instead of v0. Fixes the following build problems: arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt': arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] [...] arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die': arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] cc1: all warnings being treated as errors Fixes: 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10586/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: Fix erroneous JR emulation for MIPS R6Markos Chandras
Commit 5f9f41c474befb4ebbc40b27f65bb7d649241581 ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") added support for emulating the JR instruction on MIPS R6 cores but that introduced a bug which could be triggered when hitting a JALR opcode because the code used the wrong field in the 'r_format' struct to determine the instruction opcode. This lead to crashes because an emulated JALR instruction was treated as a JR one when the R6 emulator was turned off. Fixes: 5f9f41c474be ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10583/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: Fix branch emulation for BLTC and BGEC instructionsMarkos Chandras
Commits f1b44067c19258b7614e3cd09dfe8d8e12ff5895 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") and commit a8ff66f52d3f17b5ae793955270675c197f73d6c ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") added support for emulating various branch compact instructions. However, it missed the case for those which use the old BLEZL and BGTZL opcodes leading to random crashes when the R6 emulator is disabled. We fix this by ensuring that the 'rt' field is not zero which is always true for these branch compact instructions. Fixes: f1b44067c192 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") Fixes: a8ff66f52d3f ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10582/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: kernel: traps: Fix broken indentationMarkos Chandras
Fix broken indentation caused by the SMTC removal commit b633648c5ad3cfbda0b3daea50d2135d44899259 ("MIPS: MT: Remove SMTC support") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: b633648c5ad3c ("MIPS: MT: Remove SMTC support") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09MIPS: bootmem: Don't use memory holes for page bitmapAlexander Sverdlin
Commit f9a7febd leads to a fact that mapstart and therefore a page bitmap for bootmem allocator immediately follows initrd_end. This doesn't always work well on Octeon, where there are holes in PFN ranges (refer to 5b3b1688 and 4MB-aligned PFN allocation). Depending on the inird location it could happen, that mapstart would be in an area not allocated by plat_mem_setup() in arch/mips/cavium-octeon/setup.c, but in the alignment hole between initrd and the next PFN area. Later on this memory will be unconditionally made available to buddy allocator at the end of free_all_bootmem_core() (mm/bootmem.c). All of this results in Linux using the memory not designated for Linux in Octeon's plat_mem_setup(), which in turn means corruption of the memory used by another OS/baremetal code on the same SoC. It doesn't look to me as a problem of Octeon platform code, but rather as an inability of f9a7febd to deal correctly with the fragmented memory-mappings. Proposed fix moves the check for initrd address to the same calculation-loop in bootmem_init() (arch/mips/kernel/setup.c), which also accounts for kernel code location. This should result in mapstart located starting from the first PFN area after kernel code AND initrd. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: linux-mips@linux-mips.org Cc: David Daney <david.daney@cavium.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: Joe Perches <joe@perches.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Yusuf Khan <yusuf.khan@nokia.com> Cc: Michael Kreuzer <michael.kreuzer@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Patchwork: https://patchwork.linux-mips.org/patch/10594/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-09time: Get rid of do_posix_clock_monotonic_gettimeThomas Gleixner
All users gone. Remove it before we get another one. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-09cris: Replace do_posix_clock_monotonic_gettime()Thomas Gleixner
ktime_get_ts() is the proper interface today. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
2015-07-09ARM: dts: A10s-OLinuxIno: Add a node for axp152 pmicMichal Suchanek
Add a node for axp152 pmic used on the A10s-OLinuxIno SBC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-07-09ARM: dts: axp152: Add a dtsi file for the axp152 pmicMichal Suchanek
Add a dtsi file for the axp152 pmic, this mirrors the way things are handled for the axp202 pmic. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-07-09Revert "drm/i915: Allocate context objects from stolen"Ville Syrjälä
Stolen gets trashed during hibernation, so storing contexts there is not a very good idea. On my IVB machines this leads to a totally dead GPU on resume. A reboot is required to resurrect it. So let's not store contexts where they will get trampled. This reverts commit 149c86e74fe44dcbac5e9f8d145c5fbc5dc21261. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09drm/i915: Declare the swizzling unknown for L-shaped configurationsChris Wilson
The old style of memory interleaving swizzled upto the end of the first even bank of memory, and then used the remainder as unswizzled on the unpaired bank - i.e. swizzling is not constant for all memory. This causes problems when we try to migrate memory and so the kernel prevents migration at all when we detect L-shaped inconsistent swizzling. However, this issue also extends to userspace who try to manually detile into memory as the swizzling for an individual page is unknown (it depends on its physical address only known to the kernel), userspace cannot correctly swizzle objects. v2: Mark the global swizzling as unknown rather than adjust the value reported to userspace. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91105 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-08Merge tag 'pm+acpi-4.2-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management and ACPI updates from Rafael Wysocki: "These are fixes on top of the previous PM+ACPI pull requests (including one fix for a 4.1 regression) and two commits adding _CLS-based device enumeration support to the ACPI core and the ATA subsystem that waited for the latest ACPICA changes to be merged. Specifics: - Fix for an ACPI resources management regression introduced during the 4.1 cycle (that unfortunately went into -stable) effectively reverting the bad commit along with the recent fixups on top of it and using an alternative approach to address the underlying issue (Rafael J Wysocki). - Fix for a memory leak and an incorrect return value in an error code path in the ACPI LPSS (Low-Power Subsystem) driver (Rafael J Wysocki). - Fix for a leftover dangling pointer in an error code path in the new wakeup IRQ support code (Rafael J Wysocki). - Fix to prevent infinite loops (due to errors in other places) from happening in the core generic PM domains support code (Geert Uytterhoeven). - Hibernation documentation update/clarification (Uwe Geuder). - Support for _CLS-based device enumeration in the ACPI core and in the ATA subsystem (Suravee Suthikulpanit)" * tag 'pm+acpi-4.2-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: PM / wakeirq: Avoid setting power.wakeirq too hastily ata: ahci_platform: Add ACPI _CLS matching ACPI / scan: Add support for ACPI _CLS device matching PM / hibernate: clarify resume documentation PM / Domains: Avoid infinite loops in attach/detach code ACPI / LPSS: Fix up acpi_lpss_create_device() ACPI / PNP: Reserve ACPI resources at the fs_initcall_sync stage
2015-07-08Merge branch 'stable' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile Pull arch/tile fix from Chris Metcalf: "This fix eliminates a "section mismatch" warning caused by the new __ex_table checking code in modpost" * 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: modpost: work correctly with tile coldtext sections
2015-07-08Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux Pull module fix from Rusty Russell: "Single fix: missing rbtree removal in the module load failure path. Easy to trigger with bad params. Thanks to Peter Zijlstra and Arthur Marsh for going around on this one" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux: module: Fix load_module() error path
2015-07-08modpost: work correctly with tile coldtext sectionsChris Metcalf
The tilegx and tilepro compilers use .coldtext for their unlikely executed text section name, so an __attribute__((cold)) function will (when compiled with higher optimization levels) land in the .coldtext section. Modify modpost to add .coldtext to the set of OTHER_TEXT_SECTIONS so we don't get warnings about referencing such a section in an __ex_table block, and then also modify arch/tile/lib/memcpy_user_64.c so that it uses plain ".coldtext" instead of ".coldtext.memcpy". The latter naming is a relic of an earlier use of -ffunction-sections, which we no longer use by default. Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com> Acked-by: Rusty Russell <rusty@rustcorp.com.au>
2015-07-08arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MGKristina Martsenko
Add a DTS file for the MP2 Cortex-A53 Soft Macrocell Model implemented on a LogicTile Express 20MG (V2F-1XV7) daughterboard. This is based on the version that's currently available from the ARM DTS repository [1]. [1] git://linux-arm.org/arm-dts.git Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-07-08arm: dts: vexpress: add missing CCI PMU device node to TC2Sudeep Holla
The CCI device node was added to vexpress CA15_A7(i.e. TC2) much before the CCI PMU support and binding was added. This patch adds the missing PMU node so that CCI PMUs can be used on TC2. Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-07-08arm: dts: vexpress: describe all PMUs in TC2 dtsMark Rutland
The dts for the CoreTile Express A15x2 A7x3 (TC2) only describes the PMUs of the Cortex-A15 CPUs, and not the Cortex-A7 CPUs. Now that we have a mechanism for describing disparate PMUs and their interrupts in device tree, this patch makes use of these to describe the PMUs for all CPUs in the system. For consistency, the existing A15 PMU interrupt-affinity property is reflowed across two lines. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-07-09module: Fix load_module() error pathPeter Zijlstra
The load_module() error path frees a module but forgot to take it out of the mod_tree, leaving a dangling entry in the tree, causing havoc. Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Reported-by: Arthur Marsh <arthur.marsh@internode.on.net> Tested-by: Arthur Marsh <arthur.marsh@internode.on.net> Fixes: 93c2e105f6bc ("module: Optimize __module_address() using a latched RB-tree") Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
2015-07-08GICv3: Add ITS entry to THUNDER dtsTirumalesh Chalamarla
The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on Thunder SoCs by adding an entry to DT. Signed-off-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-07-08Merge tag 'sirf-iobrg2regmap-for-4.2' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into fixes Merge "CSR SiRFSoC rtc iobrg move to regmap for 4.2" from Barry Song: move CSR rtc iobrg read/write API to be regmap this moves to general APIs, and all drivers will be changed based on it. * tag 'sirf-iobrg2regmap-for-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux: ARM: prima2: move to use REGMAP APIs for rtciobrg
2015-07-08Merge tag 'atlas7-pinctrl-dts-for-4.2' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into fixes Merge "CSR atlas7 pinctrl descriptions for 4.2" from Barry Song: add atlas7 pinctrl dts stuff add atlas7 pin groups and gpio/pin mapping descriptions * tag 'atlas7-pinctrl-dts-for-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux: ARM: dts: atlas7: add pinctrl and gpio descriptions
2015-07-08arm64: dts: Add poweroff button device node for APM X-Gene platformY Vo
This patch adds poweroff button device node to support poweroff feature on APM X-Gene Mustang platform. Signed-off-by: Y Vo <yvo@apm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-07-08arm64: entry: handle debug exceptions in el*_invMark Rutland
Currently we enable debug exceptions before reading ESR_EL1 in both el0_inv and el1_inv. If a debug exception is taken before we read ESR_EL1, the value will have been corrupted. As el*_inv is typically fatal, an intervening debug exception results in misleading debug information being logged to the console, but is not otherwise harmful. As with the other entry paths, we can use the ESR_EL1 value stashed earlier in the exception entry (in x25 for el0_sync{,_compat}, and x1 for el1_sync), giving us better error reporting in this case. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-07-08drm/radeon: fix underflow in r600_cp_dispatch_texture()Dan Carpenter
The "if (pass_size > buf->total)" can underflow so I have changed the type of size and pass_size to unsigned to avoid this problem. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-08drm/radeon: default to 2048 MB GART size on SI+Grigori Goronzy
Newer ASICs have more VRAM on average and allocating more GART as well can have advantages. Also see commit edcd26e8. Ideally, we should scale GART size based on actual VRAM size, but that requires significant restructuring of initialization. v2: extract small helper, apply to error paths Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Grigori Goronzy <greg@chown.ath.cx> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-08drm/radeon: fix HDP flushingGrigori Goronzy
This was regressed by commit 39e7f6f8, although I don't know of any actual issues caused by it. The storage domain is read without TTM locking now, but the lock never helped to prevent any races. Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Grigori Goronzy <greg@chown.ath.cx> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-08drm/radeon: use RCU query for GEM_BUSY syscallGrigori Goronzy
We don't need to call the (expensive) radeon_bo_wait, checking the fences via RCU is much faster. The reservation done by radeon_bo_wait does not save us from any race conditions. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Grigori Goronzy <greg@chown.ath.cx> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-08drm/amdgpu: Handle irqs only based on irq ring, not irq status regs.Mario Kleiner
This is a translation of the patch ... "drm/radeon: Handle irqs only based on irq ring, not irq status regs." ... for the vblank irq handling, to fix the same problem described in that patch on the new driver. Only compile tested due to lack of suitable hw. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> CC: Michel Dänzer <michel.daenzer@amd.com> CC: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-27 10:57:15 +0000