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2017-08-30MIPS: Unify checks for sibling CPUsPaul Burton
Up until now we have open-coded checks for whether CPUs are siblings, with slight variations on whether we consider the package ID or not. This will only get more complex when we introduce cluster support, so in preparation for that this patch introduces a cpus_are_siblings() function which can be used to check whether or not 2 CPUs are siblings in a consistent manner. By checking globalnumber with the VP ID masked out this also has the neat side effect of being ready for multi-cluster systems already. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rafael J. Wysocki <rjw@rjwysocki.net> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17011/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Store core & VP IDs in GlobalNumber-style variablePaul Burton
This patch modifies the way we store core & VP IDs such that we store them in a single 32 bit integer whose format matches that of the MIPSr6 GlobalNumber register. Whereas we have previously stored core & VP IDs in separate fields, storing them in a single GlobalNumber-like field: 1) Reduces the size of struct cpuinfo_mips by 4 bytes, and will allow it to not grow when cluster support is added. 2) Gives us a natural place to store cluster number, which matches up with what the architecture provides. 3) Will be useful in the future as a parameter to the MIPSr6 GINVI instruction to specify a target CPU whose icache that instruction should operate on. The cpu_set*() accessor functions are moved out of the asm/cpu-info.h header in order to allow them to use the WARN_ON macro, which is unusable in asm/cpu-info.h due to include ordering. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Abstract CPU core & VP(E) ID access through accessor functionsPaul Burton
We currently have fields in struct cpuinfo_mips for the core & VP(E) ID of a particular CPU, and various pieces of code directly access those fields. This patch abstracts such access by introducing accessor functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id() and having code that needs to access these values call those functions rather than directly accessing the struct cpuinfo_mips fields. This prepares us for changes to the way in which those values are stored in later patches. The cpu_vpe_id() function is introduced even though we already had a cpu_vpe_id() macro for a couple of reasons: 1) It's more consistent with the core, and future cluster, accessors. 2) It ensures a sensible return type without explicit casts. 3) It's generally preferable to use functions rather than macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Use GlobalNumber macros rather than magic numbersPaul Burton
We now have definitions for the GlobalNumber register in asm/mipsregs.h, so use them in place of magic numbers in cps-vec.S. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17008/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Add accessor & bit definitions for GlobalNumberPaul Burton
MIPSr6 introduces a GlobalNumber register, which is required when VPs are implemented (ie. when multi-threading is supported) but otherwise optional. The register contains sufficient information to uniquely identify a VP within a system using its cluster number, core number & VP ID. In preparation for using this register & its fields, introduce an accessor macro for it & define its various bits with the typical style preprocessor macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Add CM/CPC 3.5 register definitionsPaul Burton
Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM v3.5 & the MIPS I6500. These are primarily registers that will be used in supporting multiple CPU clusters. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Use change_*, set_* & clear_* where appropriatePaul Burton
Make use of the new change_*, set_* & clear_* accessor functions for CPS (CM, CPC & GIC) registers where doing so makes the code easier to read or shortens it without adversely affecting readability. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17005/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Introduce register modify (set/clear/change) accessorsPaul Burton
For read-write registers introduce accessor functions that simplify the task of modifying a subset of bits within the register. set_* functions set bits to 1, clear_* functions clear bits to 0 & change_* functions set bits specified in a mask to an arbitrary value. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton
Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" did for asm/mips-cm.h. We use BIT() & GENMASK() to simplify the definition of register fields, drop the _SHF definitions since that information can be found in the _MSK ones, and then drop the _MSK suffix. Fields definitions are moved to be next to the appropriate register definition, making it easier to link the two & keep everything ordered by register address. Comments are added including the name of each register & a brief description of its purpose which helps to understand what registers are for, link them back to hardware documentation or grep for them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPC: Use common CPS accessor generation macrosPaul Burton
Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS) macros shared with the Coherence Manager (CM). Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17002/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29remoteproc: qcom: Use PTR_ERR_OR_ZEROHimanshu Jha
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Signed-off-by: Himanshu Jha <himanshujha199640@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2017-08-29ipv6: Use rt6i_idev index for echo replies to a local addressDavid Ahern
Tariq repored local pings to linklocal address is failing: $ ifconfig ens8 ens8: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 inet 11.141.16.6 netmask 255.255.0.0 broadcast 11.141.255.255 inet6 fe80::7efe:90ff:fecb:7502 prefixlen 64 scopeid 0x20<link> ether 7c:fe:90:cb:75:02 txqueuelen 1000 (Ethernet) RX packets 12 bytes 1164 (1.1 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 30 bytes 2484 (2.4 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 $ /bin/ping6 -c 3 fe80::7efe:90ff:fecb:7502%ens8 PING fe80::7efe:90ff:fecb:7502%ens8(fe80::7efe:90ff:fecb:7502) 56 data bytes Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29amd-xgbe: Interrupt summary bits are h/w version dependentTom Lendacky
There is a difference in the bit position of the normal interrupt summary enable (NIE) and abnormal interrupt summary enable (AIE) between revisions of the hardware. For older revisions the NIE and AIE bits are positions 16 and 15 respectively. For newer revisions the NIE and AIE bits are positions 15 and 14. The effect in changing the bit position is that newer hardware won't receive AIE interrupts in the current version of the driver. Specifically, the driver uses this interrupt to collect statistics on when a receive buffer unavailable event occurs and to restart the driver/device when a fatal bus error occurs. Update the driver to set the interrupt enable bit based on the reported version of the hardware. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29PCI: Disable VF decoding before pcibios_sriov_disable() updates resourcesGavin Shan
A struct resource represents the address space consumed by a device. We should not modify that resource while the device is actively using the address space. For VFs, pci_iov_update_resource() enforces this by printing a warning and doing nothing if the VFE (VF Enable) and MSE (VF Memory Space Enable) bits are set. Previously, both sriov_enable() and sriov_disable() called the pcibios_sriov_disable() arch hook, which may update the struct resource, while VFE and MSE were enabled. This effectively dropped the resource update pcibios_sriov_disable() intended to do. Disable VF memory decoding before calling pcibios_sriov_disable(). Reported-by: Carol L Soto <clsoto@us.ibm.com> Tested-by: Carol L Soto <clsoto@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: shan.gavin@gmail.com Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org>
2017-08-29PCI: layerscape: Add support for ls2088aHou Zhiqiang
The ls2088a PCIe controller's register addresses are different from ls2080a, so add a match entry to identify ls2088a PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
2017-08-29Merge branch 'nsh-headers-GSO'David S. Miller
Jiri Benc says: ==================== nsh: headers, GSO This adds header structs and helpers for NSH together with GSO support. Note there is no code in this patchset that actually manipulates the NSH headers. That was sent to netdev by Yi Yang ("[PATCH net-next v6 0/3] openvswitch: add NSH support"). The aim of this series is to lay the groundwork and ease the implementation for him. In addition to openvswitch, the NSH support should be added to tc (flower to match, act_nsh to push/pop NSH headers). That will come later. There's currently no plan to support NSH by other means than those two. The patch 3 in this patchset was written by Yi Yang, I took it from the aforementioned series and slightly modified it - see the note in the patch. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29nsh: add GSO supportJiri Benc
Add a new nsh/ directory. It currently holds only GSO functions but more will come: in particular, code shared by openvswitch and tc to manipulate NSH headers. For now, assume there's no hardware support for NSH segmentation. We can always introduce netdev->nsh_features later. Signed-off-by: Jiri Benc <jbenc@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net: add NSH header structures and helpersYi Yang
NSH (Network Service Header)[1] is a new protocol for service function chaining, it can be handled as a L3 protocol like IPv4 and IPv6, Eth + NSH + Inner packet or VxLAN-gpe + NSH + Inner packet are two typical use cases. This patch adds NSH header structures and helpers for NSH GSO support and Open vSwitch NSH support. [1] https://datatracker.ietf.org/doc/draft-ietf-sfc-nsh/ [Jiri: added nsh_hdr() helper and renamed the header struct to "struct nshhdr" to match the usual pattern. Removed packet type defines, these are now shared with VXLAN-GPE.] Signed-off-by: Yi Yang <yi.y.yang@intel.com> Signed-off-by: Jiri Benc <jbenc@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29vxlan: factor out VXLAN-GPE next protocolJiri Benc
The values are shared between VXLAN-GPE and NSH. Originally probably by coincidence but I notified both working groups about this last year and they seem to keep the values in sync since then. Hopefully they'll get a single IANA registry for the values, too. (I asked them for that.) Factor out the code to be shared by the NSH implementation. NSH and MPLS values are added in this patch, too. For MPLS, the drafts incorrectly assign only a single value, while we have two MPLS ethertypes. I raised the problem with both groups. For now, I assume the value is for unicast. Signed-off-by: Jiri Benc <jbenc@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29ether: add NSH ethertypeJiri Benc
The NSH draft says: An IEEE EtherType, 0x894F, has been allocated for NSH. Signed-off-by: Jiri Benc <jbenc@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29Merge branch 'ife-ethertype'David S. Miller
Alexander Aring says: ==================== tc: act_ife: handle IEEE IFE ethertype as default this patch series will introduce the IFE ethertype which is registered by IEEE. If the netlink act_ife type netlink attribute is not given it will use this value by default now. At least it will introduce some UAPI testcases to check if the default type is used if not specified and vice versa. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29tc-testing: add test for testing ife typeAlexander Aring
This patch adds a new testcase for the IFE type setting in tc. In case of user specified the type it will check if the ife is correctly configured to react on it. If it's not specified the default IFE type should be used. Signed-off-by: Alexander Aring <aring@mojatatu.com> Acked-by: Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29act_ife: use registered ife_type as fallbackAlexander Aring
This patch handles a default IFE type if it's not given by user space netlink api. The default IFE type will be the registered ethertype by IEEE for IFE ForCES. Signed-off-by: Alexander Aring <aring@mojatatu.com> Acked-by: Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29if_ether: add forces ife lfb typeAlexander Aring
This patch adds the forces IFE lfb type according to IEEE registered ethertypes. See http://standards-oui.ieee.org/ethertype/eth.txt for more information. Since there exists the IFE subsystem it can be used there. This patch also use the correct word "ForCES" instead of "FoRCES" which is a spelling error inside the IEEE ethertype specification. Signed-off-by: Alexander Aring <aring@mojatatu.com> Acked-by: Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29Documentation: networking: Add blurb about patches in patchworkFlorian Fainelli
Explain that the patch queue in patchwork should not be touched by patch submitters. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29Merge branch 'aquantia-fixes'David S. Miller
Pavel Belous says: ==================== net:ethernet:aquantia: Atlantic driver Update 2017-08-23 This series contains updates for aQuantia Atlantic driver. It has bugfixes and some improvements. Changes in v2: - "MCP state change" fix removed (will be sent as a separate fix after further investigation.) ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net:ethernet:aquantia: Show info message if bad firmware version detected.Pavel Belous
We should inform user about wrong firmware version by printing message in dmesg. Fixes: 3d2ff7eebe26 ("net: ethernet: aquantia: Atlantic hardware abstraction layer") Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net:ethernet:aquantia: Fix for multicast filter handling.Igor Russkikh
Since the HW supports up to 32 multicast filters we should track count of multicast filters to avoid overflow. If we attempt to add >32 multicast filter - just set NETIF_ALLMULTI flag instead. Fixes: 94f6c9e4cdf6 ("net: ethernet: aquantia: Support for NIC-specific code") Signed-off-by: Igor Russkikh <Igor.Russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net:ethernet:aquantia: Fix for incorrect speed index.Pavel Belous
The driver choose the optimal interrupt throttling settings depends of current link speed. Due this bug link_status field from aq_hw is never updated and as result always used same interrupt throttling values. Fixes: 3d2ff7eebe26 ("net: ethernet: aquantia: Atlantic hardware abstraction layer") Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net:ethernet:aquantia: Workaround for HW checksum bug.Pavel Belous
The hardware has the HW Checksum Offload bug when small TCP patckets (with length <= 60 bytes) has wrong "checksum valid" bit. The solution is - ignore checksum valid bit for small packets (with length <= 60 bytes) and mark this as CHECKSUM_NONE to allow network stack recalculate checksum itself. Fixes: ccf9a5ed14be ("net: ethernet: aquantia: Atlantic A0 and B0 specific functions.") Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net:ethernet:aquantia: Fix for number of RSS queues.Pavel Belous
The number of RSS queues should be not more than numbers of CPU. Its does not make sense to increase perfomance, and also cause problems on some motherboards. Fixes: 94f6c9e4cdf6 ("net: ethernet: aquantia: Support for NIC-specific code") Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net:ethernet:aquantia: Extra spinlocks removed.Pavel Belous
This patch removes datapath spinlocks which does not perform any useful work. Fixes: 6e70637f9f1e ("net: ethernet: aquantia: Add ring support code") Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29sparc64: vcc: make ktermios constBhumika Goyal
Make this const as it is not modified anywhere. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29packet: Don't write vnet header beyond end of bufferBenjamin Poirier
... which may happen with certain values of tp_reserve and maclen. Fixes: 58d19b19cd99 ("packet: vnet_hdr support for tpacket_rcv") Signed-off-by: Benjamin Poirier <bpoirier@suse.com> Cc: Willem de Bruijn <willemb@google.com> Acked-by: Willem de Bruijn <willemb@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29tipc: permit bond slave as bearerParthasarathy Bhuvaragan
For a bond slave device as a tipc bearer, the dev represents the bond interface and orig_dev represents the slave in tipc_l2_rcv_msg(). Since we decode the tipc_ptr from bonding device (dev), we fail to find the bearer and thus tipc links are not established. In this commit, we register the tipc protocol callback per device and look for tipc bearer from both the devices. Signed-off-by: Parthasarathy Bhuvaragan <parthasarathy.bhuvaragan@ericsson.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29Merge branch 'mlx4-misc-patches'David S. Miller
Tariq Toukan says: ==================== mlx4 misc patches This patchset contains misc patches from the team to the mlx4 Core and Eth drivers. Patch 1 by Eran replaces large static allocations by dynamic ones. Patch 2 by Leon makes an explicit conversion and solves a smatch warning. In patch 3 I fix a misplaced brackets of the sizeof operation. Patch 4 by Moshe adds the ability to inform the FW regarding user mac updates. Series generated against net-next commit: 901c5d2fbfcd ARM: dts: rk3228-evb: Fix the compiling error ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net/mlx4: Add user mac FW update supportMoshe Shemesh
Adding support for updating the FW on new port mac, when port mac change is requested by the user. This info is required by the FW as OEM management tools require this info directly from the NIC FW. Check device capability bit to verify the FW supports user mac. If the FW does support it, use set_port command to notify the FW on the new mac. The feature is relevant only to PF port mac. Signed-off-by: Moshe Shemesh <moshe@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net/mlx4_core: Fix misplaced brackets of sizeofTariq Toukan
When changing the sizeof style usage in the patch cited below, one brackets misplacement was introduced. Here we fix it. Fixes: 31975e27a4b5 ("mlx4: sizeof style usage") Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Cc: Stephen Hemminger <stephen@networkplumber.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net/mlx4_core: Make explicit conversion to 64bit valueLeon Romanovsky
The "lg" variable is declared as int so in all places where this variable is used as a shift operand, the output will be int too. This produces the following smatch warning: drivers/net/ethernet/mellanox/mlx4/fw.c:1532 mlx4_map_cmd() warn: should '1 << lg' be a 64 bit type? Simple declaration of "1" to be "1ULL" will fix the issue. Fixes: 225c7b1feef1 ("IB/mlx4: Add a driver Mellanox ConnectX InfiniBand adapters") Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net/mlx4_core: Dynamically allocate structs at mlx4_slave_capEran Ben Elisha
In order to avoid temporary large structs on the stack, allocate them dynamically. Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> Signed-off-by: Tal Alon <talal@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29bridge: fdb add and delete tracepointsRoopa Prabhu
A few useful tracepoints to trace bridge forwarding database updates. Signed-off-by: Roopa Prabhu <roopa@cumulusnetworks.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Nikolay Aleksandrov <nikolay@cumulusnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29Merge branch 'systemport-sf2-mdio-endian'David S. Miller
Florian Fainelli says: ==================== Endian fixes for SYSTEMPORT/SF2/MDIO While trying an ARM BE kernel for kinks, the 3 drivers below started not working and the reasons why became pretty obvious because the register space remains LE (hardwired), except for Broadcom MIPS where it follows the CPU's native endian (let's call that a feature). ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net: phy: mdio-bcm-unimac: Use correct I/O accessorsFlorian Fainelli
The driver currently uses __raw_{read,write}l which works for all platforms supported: Broadcom MIPS LE/BE (native endian), ARM LE (native endian) but not ARM BE (registers are still LE). Switch to using the proper accessors for all platforms and explain why Broadcom MIPS BE is special here, in doing so, we introduce a couple of helper functions to abstract these differences. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net: systemport: Set correct RSB endian bits based on hostFlorian Fainelli
RSB_SWAP0 needs to match the host CPU endian, and it needs to be set for LE and clear for BE. RSB_SWAP1 must always be cleared for SYSTEMPORT Lite. With these settings, we have the Receive Status Block always match the host endian and we do not need to perform any conversion. Since there is not necessarily a CONFIG_CPU_LITTLE_ENDIAN option defined, we test for !CONFIG_CPU_BIG_ENDIAN which is guaranteed to be set. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net: dsa: bcm_sf2: Use correct I/O accessorsFlorian Fainelli
The Starfigther 2 driver currently uses __raw_{read,write}l which means native I/O endian. This works correctly for an ARM LE kernel (default) but fails miserably on an ARM BE (BE8) kernel where registers are kept little endian, so replace uses with {read,write}l_relaxed here which is what we want because this is all performance sensitive code. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29net: systemport: Use correct I/O accessorsFlorian Fainelli
The SYSTEMPORT driver currently uses __raw_{read,write}l which means native I/O endian. This works correctly for an ARM LE kernel (default) but fails miserably on an ARM BE (BE8) kernel where registers are kept little endian, so replace uses with {read,write}l_relaxed here which is what we want because this is all performance sensitive code. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-08-29PCI: artpec6: Stop enabling writes to DBI read-only registersHou Zhiqiang
Previously we enabled writes to the DBI read-only registers so the Class Code fix in dw_pcie_setup_rc() would work. But now dw_pcie_setup_rc() enables write permission itself, so we don't need to do it here. Stop enabling writes to the DBI read-only registers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Remove unnecessary class code fixupHou Zhiqiang
Now that the Class Code fixup in dw_pcie_setup_rc() works, remove the fixup from the Layerscape driver. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29drbd: switch from kmalloc() to kmalloc_array()Roland Kammerer
We had one call to kmalloc that actually allocates an array. Switch that one to the kmalloc_array() function. Signed-off-by: Philipp Reisner <philipp.reisner@linbit.com> Signed-off-by: Lars Ellenberg <lars.ellenberg@linbit.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2017-08-29drbd: abort drbd_start_resync if there is no connectionRoland Kammerer
This was found by a static analysis tool. While highly unlikely, be sure to return without dereferencing the NULL pointer. Reported-by: Shaobo <shaobo@cs.utah.edu> Signed-off-by: Philipp Reisner <philipp.reisner@linbit.com> Signed-off-by: Lars Ellenberg <lars.ellenberg@linbit.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
generated by cgit (git 2.34.1) at 2025-10-01 17:09:51 +0000