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2021-12-08ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrlMihai Sain
I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is tied with 10K resistor to GND. U13 switch S1 is always selected as voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash. Removing PA11 from pinctrl because it remains unused. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com
2021-12-08ARM: dts: at91: update alternate function of signal PD20Hari Prasath
The alternate function of PD20 is 4 as per the datasheet of sama7g5 and not 5 as defined earlier. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Cc: <stable@vger.kernel.org> # v5.15+ Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com
2021-12-07arm64: dts: renesas: Add Renesas Spider boards supportYoshihiro Shimoda
Initial support for the Renesas Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Takehito Nakamura <takehito.nakamura.nx@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-14-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07arm64: dts: renesas: Add Renesas R8A779F0 SoC supportYoshihiro Shimoda
Add initial support for the Renesas R8A779F0 (R-Car S4-8) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-13-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07Merge tag 'renesas-r8a779f0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.17Geert Uytterhoeven
Renesas R-Car S4-8 DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car S4-8 (R8A77FA0) SoC, shared by driver and DT source files.
2021-12-07dt-bindings: clock: Add r8a779f0 CPG Core Clock DefinitionsYoshihiro Shimoda
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07dt-bindings: power: Add r8a779f0 SYSC power domain definitionsYoshihiro Shimoda
Add power domain indices for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07dt-bindings: arm: renesas: Document Renesas Spider boardsYoshihiro Shimoda
Add device tree bindings documentation for Renesas R-Car S4-8 Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07arm64: dts: renesas: Fix thermal bindingsKieran Bingham
The binding node names for the thermal zones are not successfully validated by the dt-schemas. Fix the validation by changing from sensor-thermalN or thermal-sensor-N to sensorN-thermal. Provide node labels of the form sensorN_thermal to ensure consistency with the other platform implementations. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20211104224033.3997504-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-07arm64: dts: apple: t8103: Remove PCIe max-link-speed propertiesHector Martin
The driver doesn't support these, they shouldn't be in the SoC include anyway, and we're now configuring this in the bootloader instead. This also solves the j274 1G/10G Ethernet variant discrepancy, since that will now be configured properly based on the dynamic ADT property. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in ↵Aswath Govindraju
EVM and disable them on SK AM642 EVM has two CAN connecters brought out from the two MCAN instances in the main domain through transceivers. Add device tree nodes for transceivers and set the required properties in the mcan device tree nodes, in EVM device tree file. On AM642 SK there are no connectors brought out for CAN. Therefore, disable the mcan device tree nodes in the SK device tree file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-7-a-govindraju@ti.com
2021-12-07arm64: dts: ti: k3-am64-main: Add support for MCANAswath Govindraju
Add Support for two MCAN controllers present on the am64x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-6-a-govindraju@ti.com
2021-12-07arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main ↵Faiz Abbas
mcan nodes Add four MCAN nodes present on the common processor board and set a maximum data rate of 5 Mbps. Disable all other nodes as they are not brought out on the common processor board. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-5-a-govindraju@ti.com
2021-12-07arm64: dts: ti: k3-j721e: Add support for MCAN nodesFaiz Abbas
Add support for 14 MCAN controllers in main domain and 2 MCAN controllers present in mcu domain. All the MCAN controllers support classic CAN messages as well as CAN_FD messages. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-4-a-govindraju@ti.com
2021-12-07arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodesAswath Govindraju
AM654 base board and iot platforms do not have mcan instances pinned out. Therefore, disable all the mcan instances. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-3-a-govindraju@ti.com
2021-12-07arm64: dts: ti: k3-am65-mcu: Add Support for MCANFaiz Abbas
Add Support for two MCAN controllers present on the am65x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-2-a-govindraju@ti.com
2021-12-07arm64: dts: apple: t8103: Expose PCI node for the WiFi MAC addressMark Kettenis
Expose the PCI node corresponding to the WiFi device and give it a 'local-mac-address' property. The bootloader will update it (m1n1 already has the required feature). Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07arm64: dts: apple: t8103: Add UART2Hector Martin
This UART is connected to the debug port of the WLAN module. It is mostly useless, but makes for a good test case for runtime-pm without having to unbind the console from the main system UART. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07arm64: dts: apple: t8103: Add PMGR nodesHector Martin
This adds the two PMGR nodes and all known power state subnodes. Since there are a large number of them, let's put them in a separate file to include. Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07dt-bindings: arm: apple: Add apple,pmgr bindingHector Martin
The PMGR block in Apple Silicon SoCs is responsible for SoC power management. There are two PMGRs in T8103, with different register layouts but compatible registers. In order to support this as well as future SoC generations with backwards-compatible registers, we declare these blocks as syscons and bind to individual registers in child nodes. Each register controls one SoC device. The respective apple compatibles are defined in case device-specific quirks are necessary in the future, but currently these nodes are expected to be bound by the generic syscon driver. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07dt-bindings: power: Add apple,pmgr-pwrstate bindingHector Martin
This syscon child node represents a single SoC device controlled by the PMGR block. This layout allows us to declare all device power state controls (power/clock gating and reset) in the device tree, including dependencies, instead of hardcoding it into the driver. The register layout is uniform. Each pmgr-pwrstate node provides genpd and reset features, to be consumed by downstream device nodes. Future SoCs are expected to use backwards compatible registers, and the "apple,pmgr-pwrstate" represents any such interfaces (possibly with additional features gated by the more specific compatible), allowing them to be bound without driver updates. If a backwards incompatible change is introduced in future SoCs, it will require a new compatible, such as "apple,pmgr-pwrstate-v2". Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07MAINTAINERS: Add PMGR power state files to ARM/APPLE MACHINEHector Martin
This covers the PMGR power state driver and its DT bindings, as well as any other future stuff in drivers/soc/apple. Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07dt-bindings: watchdog: Add Apple WatchdogSven Peter
Apple SoCs come with a simple embedded watchdog. This watchdog is also required in order to reset the SoC. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sven Peter <sven@svenpeter.dev> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-06ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OFJagan Teki
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OFJagan Teki
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add bindings for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2Jagan Teki
Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06ARM: dts: Add Goramo MultiLink device treeLinus Walleij
This adds a device tree for the Goramo MultiLink IXP425-based WAN router. Cc: Krzysztof Hałasa <khalasa@piap.pl> Cc: openwrt-devel@lists.openwrt.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: dts: Add FSG3 system controller and LEDsLinus Walleij
This adds the system controller on CS2 and the LEDs on it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-03arm64: dts: ti: k3-am64-main: add timesync router nodeChristian Gmeiner
The Time Sync Event Router (TIMESYNC_INTRTR0) implements a set of multiplexers to provide selection of active CPTS time sync events for routing to CPTS capable modules. This patch adds DT node TIMESYNC_INTRTR0 using "pinctrl-single" bindings. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211202173114.9936-1-christian.gmeiner@gmail.com
2021-12-03arm64: dts: ti: k3-j7200: Correct the d-cache-sets infoNishanth Menon
A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - Line size are 64bytes 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways 512 ways / 2 (Dcache is 2-way per set) = 256 sets. So, correct the d-cache-sets info. [1] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.com
2021-12-03arm64: dts: ti: k3-j721e: Fix the L2 cache setsNishanth Menon
A72's L2 cache[1] on J721e[2] is 1MB. A72's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 1MB of L2 / 64 (line length) = 16384 ways 16384 ways / 16 = 1024 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system [2] http://www.ti.com/lit/pdf/spruil1 Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211113043639.4413-1-nm@ti.com
2021-12-03arm64: dts: ti: k3-j7200: Fix the L2 cache setsNishanth Menon
A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 1MB of L2 / 64 (line length) = 16384 ways 16384 ways / 16 = 1024 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system [2] https://www.ti.com/lit/pdf/spruiu1 Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com
2021-12-03arm64: dts: ti: k3-am642: Fix the L2 cache setsNishanth Menon
A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com
2021-12-03arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl nodeKishon Vijay Abraham I
Fix 'dtbs_check' in serdes_ln_ctrl (mux@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211126084555.17797-3-kishon@ti.com
2021-12-03arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl nodeKishon Vijay Abraham I
Fix 'dtbs_check' in serdes_ln_ctrl (serdes-ln-ctrl@4080) node by changing the node name to mux-controller@4080. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211126084555.17797-2-kishon@ti.com
2021-12-03arm64: dts: allwinner: h6: tanix-tx6: Enable bluetoothJernej Skrabec
Tanix TX6 comes either with RTL8822BS or RTL8822CS wifi+bt combo module. Wifi part is already enabled in tanix DTSI. Let's enable also bluetooth. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03arm64: dts: allwinner: h6: tanix: Add MMC1 nodeJernej Skrabec
Both, Tanix TX6 and Tanix TX6 mini, have SDIO wifi module, albeit different. However, driver can be autoprobed via SDIO ID. Add MMC1 node, so kernel can discover wifi module and load driver for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03arm64: dts: allwinner: h6: Add Tanix TX6 mini dtsJernej Skrabec
Tanix TX6 mini is less capable version of Tanix TX6 although it comes with some features not present on Tanix TX6. Basic specs: - H6 SoC - 2 GiB DDR3 RAM - HDMI - SPDIF - 2x USB - analogue audio - CVBS - SD card - IR remote - LED display - fast ethernet - XR819 wifi - 16 GiB eMMC Currently supported features doesn't differ that much from Tanix TX6, but that will change soon. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03dt-bindings: arm: sunxi: Add Tanix TX6 miniJernej Skrabec
Tanix TX6 mini is, as its name suggest, very similar to Tanix TX6, but with less features. It misses bluetooth support, it has less RAM, wifi supports only 2.4G, it comes with different IR remote, etc. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSIJernej Skrabec
There is another very similar device to Tanix TX6, namely Tanix TX6 mini. Because most of the board design is shared, it makes sense to have common nodes in DTSI file. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-02dt-bindings: interrupt-controller: apple,aic: Add power-domains propertyHector Martin
This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The AIC driver doesn't do runtime-pm and likely never will (since it is system-critical), but it makes sense to describe the power domain relationship the devicetree properly. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-02dt-bindings: pinctrl: apple,pinctrl: Add power-domains propertyHector Martin
This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The pinctrl driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-02dt-bindings: iommu: apple,dart: Add power-domains propertyHector Martin
This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The DART driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-02dt-bindings: i2c: apple,i2c: Add power-domains propertyHector Martin
This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The i2c driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01arm64: dts: apple: t8103: Add cd321x nodesJanne Grunau
All M1 Mac devices have 2 SoC connected USB-C ports and use cd321x USB type C port switch and power deliver controllers. I2c bus and addresses configuration are for all devices equal. The iMac (24-inch, 2021) has a configuration with 2 additional USB-C ports (j456) using two additional cd321x controllers. Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Sven Peter <sven@svenpeter.dev> Tested-by: Hector Martin <marcan@marcan.st> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01arm64: dts: apple: t8103: Add i2c nodesJanne Grunau
Apple M1 has at least 5 i2c controllers. i2c0, i2c1 and i2c3 are used on all M1 Mac devices. The 2020 Mac Mini uses i2c2 and the 13-inch MacBook Pro uses i2c2 and i2c4. Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Sven Peter <sven@svenpeter.dev> Tested-by: Hector Martin <marcan@marcan.st> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01arm64: dts: apple: Add missing M1 (t8103) devicesJanne Grunau
This adds support for following Apple M1 devices: - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) - iMac (24-inch 2021) Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Janne Grunau <j@jannau.net> Tested-by: Hector Martin <marcan@marcan.st> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01dt-bindings: arm: apple: Add iMac (24-inch 2021) to Apple bindingsJanne Grunau
This introduces compatible strings for both 2021 Apple iMac M1 devices: * apple,j456 - iMac (24-inch, 4x USB-C, M1, 2021) * apple,j457 - iMac (24-inch, 2x USB-C, M1, 2021) Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Janne Grunau <j@jannau.net> Tested-by: Hector Martin <marcan@marcan.st> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01arm64: dts: apple: add #interrupt-cells property to pinctrl nodesJanne Grunau
Required for devices trying to use pinctrl devices as interrupt controller. Fixes: 0a8282b83119 ("arm64: apple: Add pinctrl nodes") Signed-off-by: Janne Grunau <j@jannau.net> Cc: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Sven Peter <sven@svenpeter.dev> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Hector Martin <marcan@marcan.st> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01dt-bindings: i2c: apple,i2c: allow multiple compatiblesJanne Grunau
The intention was to have a SoC-specific and base compatible string to allow forward compatibility and SoC specific quirks, Fixes: df7c4a8c1b47 ("dt-bindings: i2c: Add Apple I2C controller bindings") Signed-off-by: Janne Grunau <j@jannau.net> Cc: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Sven Peter <sven@svenpeter.dev> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Hector Martin <marcan@marcan.st> Acked-by: Wolfram Sang <wsa@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
generated by cgit (git 2.34.1) at 2025-09-11 16:09:17 +0000