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2021-12-16ARM: config: multi v7: Enable NVIDIA Tegra20 APB DMA driverDmitry Osipenko
All Tegra20/30/114 serial and audio drivers depend on the Tegra20 APB DMA driver, enable this DMA driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16ARM: config: multi v7: Enable NVIDIA Tegra20 S/PDIF driverDmitry Osipenko
Enable Tegra20 S/PDIF driver that is a part of HDMI audio subsystem. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16ARM: tegra_defconfig: Enable S/PDIF driverDmitry Osipenko
Enable Tegra20 S/PDIF driver. It's a part of HDMI audio subsystem on Tegra. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16Merge tag 'tegra-for-5.16-soc-fixes' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes soc/tegra: Fixes for v5.16-rc6 This contains a single build fix without which ARM allmodconfig builds are broken if -Werror is enabled. * tag 'tegra-for-5.16-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: fuse: Fix bitwise vs. logical OR warning Link: https://lore.kernel.org/r/20211215162618.3568474-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16Merge tag 'omap-for-v5.17/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for v5.17 merge window These changes are mostly minor non-urgent fixes for typos and binding checks. The system-power-controller gets configured for more am3 devices as it's not am335x-boneblack speicif. For for am437x we add magnetic card reader support. Note that the asahi-kasei,ak8975 binding changes may produce a new binding check warning as the binding related change is merged separately. * tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp. ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value ARM: dts: am437x-gp-evm: enable ADC1 ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module ARM: dts: am437x-cm-t43: Use a correctly spelled DT property ARM: dts: am335x-icev2: Add system-power-controller to RTC node ARM: dts: am335x-boneblack-common: move system-power-controller ARM: dts: elpida_ecb240abacn: Change Elpida compatible Link: https://lore.kernel.org/r/pull-1639659798-679261@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16Merge tag 'socfpga_dts_update_for_v5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v5.17 - Update N5X to include qspi, usb and ethernet - Adjust NAND partition size for Agilex and Stratix10 * tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: Update NAND MTD partition for Agilex and Stratix 10 arm64: dts: n5x: add qspi, usb, and ethernet support Link: https://lore.kernel.org/r/20211215164545.300273-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging for v5.16-rc5. Resolves a conflict between drm-misc-next and drm-misc-fixes in the vc4 driver. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2021-12-16drm/tegra: Add back arm_iommu_detach_device()Dmitry Osipenko
DMA buffers of 2D/3D engines aren't mapped properly when CONFIG_ARM_DMA_USE_IOMMU=y. The memory management code of Tegra DRM driver has a longstanding overhaul overdue and it's not obvious where the problem is in this case. Hence let's add back the old workaround which we already had sometime before. It explicitly detaches DRM devices from the offending implicit IOMMU domain. This fixes a completely broken 2d/3d drivers in case of ARM32 multiplatform kernel config. Cc: stable@vger.kernel.org Fixes: fa6661b7aa0b ("drm/tegra: Optionally attach clients to the IOMMU") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16gpu: host1x: Add back arm_iommu_detach_device()Dmitry Osipenko
Host1x DMA buffer isn't mapped properly when CONFIG_ARM_DMA_USE_IOMMU=y. The memory management code of Host1x driver has a longstanding overhaul overdue and it's not obvious where the problem is in this case. Hence let's add back the old workaround which we already had sometime before. It explicitly detaches Host1x device from the offending implicit IOMMU domain. This fixes a completely broken Host1x DMA in case of ARM32 multiplatform kernel config. Cc: stable@vger.kernel.org Fixes: af1cbfb9bf0f ("gpu: host1x: Support DMA mapping of buffers") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16ARM: tegra: Add OPP tables and power domains to Tegra20 device-treesDmitry Osipenko
Add OPP tables and power domains to all peripheral devices which support power management on Tegra20 SoC. Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP tableDmitry Osipenko
Extend memory OPPs with 500 MHz entry. This clock rate is used by ASUS Transformer tablets. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16netfilter: ctnetlink: remove expired entries firstFlorian Westphal
When dumping conntrack table to userspace via ctnetlink, check if the ct has already expired before doing any of the 'skip' checks. This expires dead entries faster. /proc handler also removes outdated entries first. Reported-by: Vitaly Zuevsky <vzuevsky@ns1.com> Signed-off-by: Florian Westphal <fw@strlen.de> Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
2021-12-16drm/tegra: Consolidate runtime PM management of older UAPI codepathDmitry Osipenko
Move runtime PM management of older UAPI code paths into the common place. This removes boilerplate code from client drivers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: submit: Remove pm_runtime_enabled() checksDmitry Osipenko
Runtime PM is now universally available, make it mandatory by removing the pm_runtime_enabled() checks. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: nvdec: Stop channel on suspendDmitry Osipenko
CDMA must be stopped before hardware is suspended. Add channel stopping to RPM suspend callback. Add system level suspend-resume callbacks. Runtime PM initialization is moved to host1x client init phase because RPM callback now uses host1x channel that is available only when host1x client is registered. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: vic: Stop channel on suspendDmitry Osipenko
CDMA must be stopped before hardware is suspended. Add channel stopping to RPM suspend callback. Add system level suspend-resume callbacks. Runtime PM initialization is moved to host1x client init phase because RPM callback now uses host1x channel that is available only when host1x client is registered. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: gr3d: Support generic power domain and runtime PMDmitry Osipenko
Add runtime power management and support generic power domains. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: gr2d: Support generic power domain and runtime PMDmitry Osipenko
Add runtime power management and support generic power domains. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: hdmi: Add OPP supportDmitry Osipenko
The HDMI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now HDMI driver must use OPP API for driving the controller's clock rate because OPP API takes care of reconfiguring the domain's performance state based on HDMI clock rate. Add OPP support to the HDMI driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: dc: Support OPP and SoC core voltage scalingDmitry Osipenko
Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: submit: Add missing pm_runtime_mark_last_busy()Dmitry Osipenko
Runtime PM auto-suspension doesn't work without pm_runtime_mark_last_busy(), add it. Cc: <stable@vger.kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16gpu: host1x: Add host1x_channel_stop()Dmitry Osipenko
Add host1x_channel_stop() which waits till channel becomes idle and then stops the channel hardware. This is needed for supporting suspend/resume by host1x drivers since the hardware state is lost after power-gating, thus the channel needs to be stopped before client enters into suspend. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16gpu: host1x: Add initial runtime PM and OPP supportDmitry Osipenko
Add runtime PM and OPP support to the Host1x driver. For the starter we will keep host1x always-on because dynamic power management require a major refactoring of the driver code since lot's of code paths are missing the RPM handling and we're going to remove some of these paths in the future. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: vic: Handle tegra_drm_alloc() failureThierry Reding
This function can return one of several errors in an ERR_PTR()-encoded pointer, so make sure to propogate those on failure. Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16gpu: host1x: Add missing DMA API includeRobin Murphy
Host1x seems to be relying on picking up dma-mapping.h transitively from iova.h, which has no reason to include it in the first place. Fix the former issue before we totally break things by fixing the latter one. CC: Thierry Reding <thierry.reding@gmail.com> CC: Mikko Perttunen <mperttunen@nvidia.com> CC: dri-devel@lists.freedesktop.org Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: vic: Fix DMA API misuseRobin Murphy
Upon failure, dma_alloc_coherent() returns NULL. If that does happen, passing some uninitialised stack contents to dma_mapping_error() - which belongs to a different API in the first place - has precious little chance of detecting it. Also include the correct header, because the fragile transitive inclusion currently providing it is going to break soon. Fixes: 20e7dce255e9 ("drm/tegra: Remove memory allocation from Falcon library") CC: Thierry Reding <thierry.reding@gmail.com> CC: Mikko Perttunen <mperttunen@nvidia.com> CC: dri-devel@lists.freedesktop.org Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: hdmi: Register audio CODEC on Tegra20Dmitry Osipenko
Tegra20 SoC supports only S/PDIF source for HDMI audio. Register ASoC HDMI S/PDIF CODEC for Tegra20, it will be linked with the S/PDIF CPU DAI. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: hdmi: Unwind tegra_hdmi_init() errorsDmitry Osipenko
Add missing error unwinding to tegra_hdmi_init(), for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Mark nvdec PM functions as __maybe_unusedArnd Bergmann
The resume helper is called conditionally and causes a harmless warning when stubbed out: drivers/gpu/drm/tegra/nvdec.c:240:12: error: 'nvdec_runtime_resume' defined but not used [-Werror=unused-function] 240 | static int nvdec_runtime_resume(struct device *dev) Mark both suspend and resume as __maybe_unused for consistency to avoid this warning. Fixes: e76599df354d ("drm/tegra: Add NVDEC driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Mark nvdec_writel() as inlineArnd Bergmann
Without CONFIG_IOMMU_API, the nvdec_writel() function is unused, causing a warning: drivers/gpu/drm/tegra/nvdec.c:48:13: error: 'nvdec_writel' defined but not used [-Werror=unused-function] 48 | static void nvdec_writel(struct nvdec *nvdec, u32 value, unsigned int offset) | ^~~~~~~~~~~~ As this is a trivial wrapper around an inline function, mark it as inline itself, which avoids the warning as well. Fixes: e76599df354d ("drm/tegra: Add NVDEC driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: dc: rgb: Allow changing PLLD rate on Tegra30+Dmitry Osipenko
Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI bridge that requires a precise clock rate in order to operate properly. Tegra30 has a dedicated PLL for each display controller, hence the PLL rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB output. Configure the clock rate before display controller is enabled since DC itself may be running off this PLL and it's not okay to change the rate of the active PLL that doesn't support dynamic frequency switching since hardware will hang. Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Remove duplicate struct declarationWan Jiabing
struct tegra_dc is declared at 13rd line. The declaration here is unnecessary. Remove it. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: vic: Use autosuspendMikko Perttunen
When going idle, it's not unlikely that more work will follow. As such, use autosuspend with a 500ms suspend delay. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: gr2d: Explicitly control module resetThierry Reding
As of commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks"), module resets are no longer automatically deasserted when the module clock is enabled. To make sure that the gr2d module continues to work, we need to explicitly control the module reset. Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16gpu: host1x: select CONFIG_DMA_SHARED_BUFFERArnd Bergmann
Linking fails when dma-buf is disabled: ld.lld: error: undefined symbol: dma_fence_release >>> referenced by fence.c >>> gpu/host1x/fence.o:(host1x_syncpt_fence_enable_signaling) in archive drivers/built-in.a >>> referenced by fence.c >>> gpu/host1x/fence.o:(host1x_fence_signal) in archive drivers/built-in.a >>> referenced by fence.c >>> gpu/host1x/fence.o:(do_fence_timeout) in archive drivers/built-in.a Fixes: 687db2207b1b ("gpu: host1x: Add DMA fence implementation") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16gpu: host1x: Drop excess kernel-doc entry @keyRandy Dunlap
Fix kernel-doc warning in host1x: ../drivers/gpu/host1x/bus.c:774: warning: Excess function parameter 'key' description in '__host1x_client_register' Fixes: 0cfe5a6e758f ("gpu: host1x: Split up client initalization and registration") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-tegra@vger.kernel.org Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: dc: rgb: Move PCLK shifter programming to CRTCDmitry Osipenko
Asus TF700T tablet uses TC358768 DPI->DSI bridge that sits between Tegra's DPI output and display panel input. Bridge requires to have stable PCLK output before RGB encoder is enabled because it uses PCLK by itself to clock internal logic and bridge is programmed before Tegra's encoder is enabled. Hence the PCLK clock shifter must be programmed when CRTC is enabled, otherwise clock is unstable and bridge hangs because of it. Move the shifter programming from RGB encoder into CRTC. Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Bump VIC/NVDEC clock rates to FmaxMikko Perttunen
To get full performance out of these engines, bump their clock rates to maximum. In the future we may want something smarter but this should be fine for now. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Add NVDEC driverMikko Perttunen
Add support for booting and using NVDEC on Tegra210, Tegra186 and Tegra194 to the Host1x and TegraDRM drivers. Booting in secure mode is not currently supported. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Support asynchronous commits for cursorThierry Reding
This adds support for asynchronously updating the cursor plane, which enables support for the legacy cursor IOCTLs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Propagate errors from drm_gem_plane_helper_prepare_fb()Thierry Reding
Currently this function doesn't return an error, but that may change in the future, so make sure to propagate any error codes that it might return. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Do not reference tegra_plane_funcs directlyThierry Reding
Instead of referencing the tegra_plane_funcs struct directly, use each plane's vtable instead. This makes it more future-proof in case any of the planes ever use a different set of functions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Implement buffer object cacheThierry Reding
This cache is used to avoid mapping and unmapping buffer objects unnecessarily. Mappings are cached per client and stay hot until the buffer object is destroyed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16drm/tegra: Implement correct DMA-BUF semanticsThierry Reding
DMA-BUF requires that each device that accesses a DMA-BUF attaches to it separately. To do so the host1x_bo_pin() and host1x_bo_unpin() functions need to be reimplemented so that they can return a mapping, which either represents an attachment or a map of the driver's own GEM object. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16Merge branch 'tegra-for-5.17-soc-opp' of ↵Thierry Reding
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into drm/tegra/for-next
2021-12-16media: staging: tegra-vde: Support generic power domainDmitry Osipenko
Currently driver supports legacy power domain API, this patch adds generic power domain support. This allows us to utilize a modern GENPD API for newer device-trees. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16spi: tegra20-slink: Add OPP supportDmitry Osipenko
The SPI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SPI driver must use OPP API for driving the controller's clock rate because OPP API takes care of reconfiguring the domain's performance state in accordance to the rate. Add OPP support to the driver. Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16mtd: rawnand: tegra: Add runtime PM and OPP supportDmitry Osipenko
The NAND on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now NAND must be resumed using runtime PM API in order to initialize the NAND power state. Add runtime PM and OPP support to the NAND driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16mmc: sdhci-tegra: Add runtime PM and OPP supportDmitry Osipenko
The SDHCI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SDHCI must be resumed using runtime PM API in order to initialize the SDHCI power state. The SDHCI clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the SDHCI driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16pwm: tegra: Add runtime PM and OPP supportDmitry Osipenko
The PWM on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now PWM must be resumed using runtime PM API in order to initialize the PWM power state. The PWM clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the PWM driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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