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2016-07-12drm/vgem: Fix mmapingChris Wilson
The vGEM mmap code has bitrotted slightly and now immediately BUGs. Since vGEM was last updated, there are new core GEM facilities to provide more common functions, so let's use those here. v2: drm_gem_free_mmap_offset() is performed from drm_gem_object_release() so we can remove the redundant call. Testcase: igt/vgem_basic/mmap Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96603 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Sean Paul <seanpaul@chromium.org> Cc: Zach Reizner <zachr@google.com> Cc: Matthew Auld <matthew.auld@intel.com> Tested-by: Humberto Israel Perez Rodriguez <humberto.i.perez.rodriguez@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1466692534-28303-1-git-send-email-chris@chris-wilson.co.uk
2016-07-11drm/vc4: remove redundant ret status checkColin Ian King
At the current point where ret is being checked for non-zero it has not changed since it was initialized to zero, hence the check and the label unref are redundant and can be removed. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2016-07-11drm/vc4: Implement precise vblank timestamping.Mario Kleiner
Precise vblank timestamping is implemented via the usual scanout position based method. On VC4 the pixelvalves PV do not have a scanout position register. Only the hardware video scaler HVS has a similar register which describes which scanline for the output is currently composited and stored in the HVS fifo for later consumption by the PV. This causes a problem in that the HVS runs at a much faster clock (system clock / audio gate) than the PV which runs at video mode dot clock, so the unless the fifo between HVS and PV is full, the HVS will progress faster in its observable read line position than video scan rate, so the HVS position reading can't be directly translated into a scanout position for timestamp correction. Additionally when the PV is in vblank, it doesn't consume from the fifo, so the fifo gets full very quickly and then the HVS stops compositing until the PV enters active scanout and starts consuming scanlines from the fifo again, making new space for the HVS to composite. Therefore a simple translation of HVS read position into elapsed time since (or to) start of active scanout does not work, but for the most interesting cases we can still get useful and sufficiently accurate results: 1. The PV enters active scanout of a new frame with the fifo of the HVS completely full, and the HVS can refill any fifo line which gets consumed and thereby freed up by the PV during active scanout very quickly. Therefore the PV and HVS work effectively in lock-step during active scanout with the fifo never having more than 1 scanline freed up by the PV before it gets refilled. The PV's real scanout position is therefore trailing the HVS compositing position as scanoutpos = hvspos - fifosize and we can get the true scanoutpos as HVS readpos minus fifo size, so precise timestamping works while in active scanout, except for the last few scanlines of the frame, when the HVS reaches end of frame, stops compositing and the PV catches up and drains the fifo. This special case would only introduce minor errors though. 2. If we are in vblank, then we can only guess something reasonable. If called from vblank irq, we assume the irq is usually dispatched with minimum delay, so we can take a timestamp taken at entry into the vblank irq handler as a baseline and then add a full vblank duration until the guessed start of active scanout. As irq dispatch is usually pretty low latency this works with relatively low jitter and good results. If we aren't called from vblank then we could be anywhere within the vblank interval, so we return a neutral result, simply the current system timestamp, and hope for the best. Measurement shows the generated timestamps to be rather precise, and at least never off more than 1 vblank duration worst-case. Limitations: Doesn't work well yet for interlaced video modes, therefore disabled in interlaced mode for now. v2: Use the DISPBASE registers to determine the FIFO size (changes by anholt) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-07-11drm/vc4: Bind the HVS before we bind the individual CRTCs.Eric Anholt
We need to be able to look at the CRTC's registers in the HVS as part of initialization, while the HVS doesn't need to look at the PV registers. Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com>
2016-07-11drm/panel: simple: Add support for Starry KR122EA0SRA panelDouglas Anderson
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected using eDP interfaces. EDID shows: Detailed mode: Clock 147.000 MHz, 263 mm x 164 mm 1920 1936 1952 1984 hborder 0 1200 1215 1217 1235 vborder 0 -hsync -vsync Manufacturer-specified data, tag 15 ASCII string: STARRY ASCII string: KR122EA0SRA Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: Add Starry KR122EA0SRA panel bindingDouglas Anderson
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: Add vendor prefix for StarryDoug Anderson
>From their website: http://www.b001.com.cn/ Starry appears to be a company involved in LCD panels and related components. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: display: Add Sharp LQ101K1LY04 panel bindingJoshua Clayton
The Sharp LQ101K1LY04 is a 10" WXGA (1280x800) LVDS panel and is compatible with the simple-panel binding. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Sharp LQ101K1LY04Joshua Clayton
Add simple-panel support for the Sharp LQ101K1LY04, which is a 10" WXGA (1280x800) LVDS panel. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for LG LP079QX1-SP0V panelYakir Yang
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and 32 pins eDP interface. This module supports 1536x2048 mode. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: Add support for LG LP079QX1-SP0V panelYakir Yang
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and 32 pins eDP interface. This module supports 1536x2048 mode. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Sharp LQ123P1JX31 panelYakir Yang
The Sharp LQ123P1JX31 is an 12.3", 2400x1600 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: Add Sharp LQ123P1JX31 panel bindingYakir Yang
The Sharp LQ123P1JX31 is an 12.3" 2400x1600 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for Samsung LSN122DL01-C01 panelYakir Yang
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: Add Samsung LSN122DL01-C01 panel bindingYakir Yang
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Add support for LG LP097QX1-SPA1 panelYakir Yang
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11dt-bindings: Add LG LP097QX1-SPA1 panel bindingYakir Yang
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/panel: simple: Update backlight state propertyThierry Reding
Some backlight drivers ignore the power property and instead only use the state property. Fixup the panel driver to set the state property in addition to the power property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11drm/i915: Update DRIVER_DATE to 20160711Daniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-07-10drm/i915: Select DRM_VGEM for igtChris Wilson
igt/prime_vgem (and others) depends upon VGEM so automatically select it when enabling i915 debugging. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1468059777-10205-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld <matthew.auld@intel.com>
2016-07-10drm/i915: Select X86_MSR for igtChris Wilson
igt/pm_rpm depends upon /dev/*/msr so automatically select it when enabling i915 debugging. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1468054147-9821-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld <matthew.auld@intel.com>
2016-07-08drm/i915: Fill unused GGTT with scratch pages for VT-dChris Wilson
One of the numerous VT-d workarounds we require is that the display hardware reads past the end of the buffer triggering VT-d faults. This is acknowledged in the code as being safe "since we fill the unused portions of the GGTT with the scratch page". Alas, that is no longer always true and so we trigger DMAR read faults. Skylake also requires another workaround to avoid mixing VT-d and unpopulated PTE, and so there we also need to ensure we fill unused entries with the scratch page. Reported-by: Mike Lothian <mike@fireburn.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96584 Fixes: f7770bfd9fd2 ("drm/i915: Skip clearing the GGTT on full-ppgtt systems") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: David Weinehall <david.weinehall@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1466773634-8106-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: David Weinehall <david.weinehall@intel.com>
2016-07-08Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next This is the main 4.8 pull for radeon and amdgpu. Sorry for the delay, I meant to send this out last week, but I was moving house. Lots of changes here: - ATPX improvements for better dGPU power control on PX systems - New power features for CZ/BR/ST - Pipelined BO moves and evictions in TTM - GPU scheduler improvements - GPU reset improvements - Overclocking on dGPUs with amdgpu - Lots of code cleanup - Bug fixes * 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (191 commits) drm/amd/powerplay: don't add invalid voltage. drm/amdgpu: add read/write function for GC CAC programming drm/amd/powerplay: add definitions related to di/dt feature for fiji and polaris. drm/amd/powerplay: add shared definitions for di/dt feature. drm/amdgpu: remove gfx8 registers that vary between asics drm/amd/powerplay: add mvdd dpm support. drm/amdgpu: get number of shade engine by cgs interface. drm/amdgpu: remove more of the ring backup code drm/amd/powerplay: Unify family defines drm/amdgpu: clean up ring_backup code, no need more drm/amdgpu: ib test first after gpu reset drm/amdgpu: recovery hw jobs when gpu reset V3 drm/amdgpu: abstract amdgpu_vm_is_gpu_reset drm/amdgpu: add a bool to specify if needing vm flush V2 drm/amdgpu: add amd_sched_job_recovery drm/amdgpu: force completion for gpu reset drm/amdgpu: block ttm first before parking scheduler drm/amd: add amd_sched_hw_job_reset drm/amd: add parent for sched fence drm/amdgpu: remove evict vram ...
2016-07-08Merge tag 'drm-hisilicon-next-2016-07-04' of github.com:xin3liang/linux into ↵Dave Airlie
drm-next drm-hisilicon-next * tag 'drm-hisilicon-next-2016-07-04' of github.com:xin3liang/linux: drm/hisilicon: Fix ADE vblank on/off handling drm/hisilicon: add select HISI_KIRIN_DW_DSI drm/hisilicon: Fix return value check in ade_dts_parse()
2016-07-08Merge branch 'drm-etnaviv-next' of git://git.pengutronix.de/git/lst/linux ↵Dave Airlie
into drm-next etnaviv-next only contains two patches to get rid of a confusing error message and finally one patch to enable the autonomous GPU clock gating. * 'drm-etnaviv-next' of git://git.pengutronix.de/git/lst/linux: drm/etnaviv: remove generic GPU init failure reporting drm/etnaviv: improve error reporting in GPU init path drm/etnaviv: enable GPU module level clock gating support
2016-07-08Merge tag 'drm-amdkfd-next-2016-07-03' of ↵Dave Airlie
git://people.freedesktop.org/~gabbayo/linux into drm-next A few amdkfd patches for 4.8. One patch replaces deprecated kernel api call (create_workqueue) and the other patch properly cleans up resources in case of failing to create a process object. * tag 'drm-amdkfd-next-2016-07-03' of git://people.freedesktop.org/~gabbayo/linux: drm/amdkfd: destroy mutex if process creation fails drm/amdkfd: Remove create_workqueue()
2016-07-07Merge tag 'drm-vc4-fixes-2016-06-06' into drm-vc4-nextEric Anholt
Merge Mario's get_vblank_counter fix forward to prevent conflicts with his followon patch to add precise vblank timestamping.
2016-07-07gpu: drm: vc4_hdmi: add missing of_node_put after calling of_parse_phandlePeter Chen
of_node_put needs to be called when the device node which is got from of_parse_phandle has finished using. Signed-off-by: Peter Chen <peter.chen@nxp.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2016-07-07drm: vc4: enable XBGR8888 and ABGR8888 pixel formatsRob Herring
DRM_FORMAT_XBGR8888 and DRM_FORMAT_ABGR8888 are 2 of the native formats used in Android, so enable them for VC4. There seems to be no logic behind HVS_PIXEL_ORDER_xxxx naming, but HVS_PIXEL_ORDER_ARGB seems to work correctly. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2016-07-07drm/amd/powerplay: don't add invalid voltage.Rex Zhu
if atomctrl_get_voltage_evv_on_sclk_ai returns non zero (fail) in the expansion of the PP_ASSERT_WITH_CODE macro the continue will actually do nothing, So invalid voltage will be added to ppbable. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: add read/write function for GC CAC programmingRex Zhu
Create a GC_CAC_IND_INDEX/DATA pair of funcitons to program all the CAC registers Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd/powerplay: add definitions related to di/dt feature for fiji and ↵Rex Zhu
polaris. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd/powerplay: add shared definitions for di/dt feature.Rex Zhu
v1: delete some comflict definitions between polaris and fiji. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: remove gfx8 registers that vary between asicsKen Wang
those register mask definitions are different in polaris compare to former gfx 8 gpus, so remove them from misusing. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd/powerplay: add mvdd dpm support.Rex Zhu
SMC requires master switch bit to be set. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: get number of shade engine by cgs interface.Rex Zhu
the num of shade engine was needed to measure the activity of the graphics core and to enable di/dt feature. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: remove more of the ring backup codeAlex Deucher
Not used anymore. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd/powerplay: Unify family definesTom St Denis
s/AMD_FAMILY_/AMDGPU_FAMILY_/ Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: clean up ring_backup code, no need moreChunming Zhou
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: ib test first after gpu resetChunming Zhou
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: recovery hw jobs when gpu reset V3Chunming Zhou
V3: directly use pd_addr. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: abstract amdgpu_vm_is_gpu_resetChunming Zhou
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: add a bool to specify if needing vm flush V2Chunming Zhou
which avoids job->vm_pd_addr be changed. V2: pass job structure to amdgpu_vm_grab_id and amdgpu_vm_flush directly. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: add amd_sched_job_recoveryChunming Zhou
Which is to recover hw jobs when gpu reset. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: force completion for gpu resetChunming Zhou
After all hw jobs are reset, hw fence is meaningless, so force_completion Cc: William Lewis <minutemaidpark@hotmail.com> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: block ttm first before parking schedulerChunming Zhou
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd: add amd_sched_hw_job_resetChunming Zhou
amd_sched_hw_job_reset will remove callback from hw fence. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amd: add parent for sched fenceChunming Zhou
Parent of sched fence is hw fence which is to signal sched fence. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: remove evict vramChunming Zhou
Previous vm fault is since page talbe losts connection with vmid after gpu reset. Now the issue is fixed by recovery. No need more. If we want to save vram for some EDC card, we will need to consider a complete solution. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: put old hw fence of job if gpu resetChunming Zhou
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-12 02:30:52 +0000