summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2013-11-26ARM: dts: omap3-igep: Fix bus-width for mmc1Enric Balletbo i Serra
Both, IGEPv2 and IGEP COM MODULE have a bus-width of 4 not 8, so fix this and do not mux data pins from mmc1_data4 to mmc1_data7. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-11-26ARM: OMAP2+: dss-common: change IGEP's DVI DDC i2c busJavier Martinez Canillas
IGEP's DVI connector's DDC pins are connected to OMAP's third i2c bus. When booting with Device Trees the requested bus number is set to -1 which means that the bus number should be dynamically assigned. So the third i2c bus has 2 has a bus number. Since now only DT booting is supported for IGEP boards after commit 06ff74fd ("ARM: OMAP2+: remove legacy support for IGEP boards"), the i2c bus number has to be changed. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-11-26ARM: OMAP2+: Disable POSTED mode for errata i103 and i767Joel Fernandes
Enabling of Posted mode is seen to cause problems on dmtimer modules on AM33xx (much like other OMAPs). Reference discussions on forums [1] [2]. Earlier patch solving this on other OMAPs [3]. For OMAP SoCs with this errata, the fix has been to not enable Posted mode. However, on some SoCs (atleast AM33xx) which carry this errata, Posted mode is enabled on reset. So we not only need to ignore enabling of the POSTED bit when the timer is requested, but also disable Posted mode if errata is present. [1] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/285744.aspx [2] http://e2e.ti.com/support/arm/sitara_arm/f/791/t/270632.aspx [3] http://www.spinics.net/lists/linux-omap/msg81770.html Cc: stable@vgerk.kernel.org Reported-by: Russ Dill <russ.dill@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-11-26Merge tag 'v3.12'Paul Moore
Linux 3.12
2013-11-26Merge tag 'ux500-defconfig-v3.13-rcs' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into fixes From Linus Walleij, Ux500 defconfig patches for the v3.13 rc series: - Allow creation and mounting of devtmpfs, which is used by OpenEmbedded root filesystems among others. - Enable CPUidle for the ux500, it has been accidentally disabled due to a Kconfig change. * tag 'ux500-defconfig-v3.13-rcs' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: u8500_defconfig: add missing cpuidle option u8500_defconfig: allow creation and mounting of devtmpfs
2013-11-26Merge tag 'ux500-fixes-v3.13-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into fixes From Linus Walleij, Ux500 fixes for the v3.13 series: - Restore platform data for the (e)MMC/SD controllers, so they can pins and special flags properly like before. * tag 'ux500-fixes-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: Revert "ARM: ux500: Stop passing MMC's platform data for Device Tree boots" Revert "ARM: ux500: Remove AUXDATA relating to SDI (MMC) clock-name bindings"
2013-11-26Revert "ARM: ux500: Stop passing MMC's platform data for Device Tree boots"Linus Walleij
This reverts commit 49c129519a7a8840767321c38d2eaf84a263529b. The special settings for the SD/MMC card parameters that are not yet fully agreed upon how to encode into the device tree went missing with this commit. We need to first put it into the device tree, and then remove the platform data. Cc: Lee Jones <lee.jones@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26Revert "ARM: ux500: Remove AUXDATA relating to SDI (MMC) clock-name bindings"Linus Walleij
This reverts commit ce16feb8510cbbcd090c2320c35db2fbbffde210. This commit stopped tying down the name of the MMC/SD devices, but these names are used in the pin control table, so the MMC/SD cards stopped working. Cc: Lee Jones <lee.jones@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26ARM: ux500: u8500_defconfig: add missing cpuidle optionDaniel Lezcano
With the commit d3f2950f2adeea3da0317e952914b59adaa4cdb3, the option ARM_U8500_CPUIDLE was added to the Kconfig but not reflected in the default config file, hence the cpuidle driver is no longer enabled since this commit. Enable it again by adding the missing option in the default config file. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26u8500_defconfig: allow creation and mounting of devtmpfsAndi Shyti
This patch enables CONFIG_DETTMPFS and CONFIG_DEVTMPFS_MOUNT flags for u8500 based devices. In this way it's possible to create a tmpfs/ramfs already in the early stages of the boot, allowing programs like udev/mdev to populate the /dev directory. Signed-off-by: Andi Shyti <andi@etezian.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Mostly bugfixes and a few small code removals. Worth pointing out is: - A handful of more fixes to get DT enablement working properly on OMAP, finding new breakage of things that don't work quite right yet without the traditional board files. I expect a bit more of this to come in this release as people test on their hardware. - Implementation of power_down_finish() on vexpress, to make kexec work and to stop the MCPM core to produce a warning (the warning was new to 3.13-rc1). - A handful of minor fixes for various platforms" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: bcm2835: add missing #xxx-cells to I2C nodes ARM: dts: Add max77686 RTC interrupt to cros5250-common ARM: vexpress/TC2: Implement MCPM power_down_finish() ARM: tegra: Provide dummy powergate implementation ARM: omap: fix warning with LPAE build ARM: OMAP2+: Remove legacy omap4_twl6030_hsmmc_init ARM: OMAP2+: Remove legacy mux code for display.c ARM: OMAP2+: Fix undefined reference to set_cntfreq gpio: twl4030: Fix passing of pdata in the device tree case gpio: twl4030: Fix regression for twl gpio output ARM: OMAP2+: More randconfig fixes for reconfigure_io_chain ARM: dts: imx6qdl: disable spdif "rxtx5" clock option ARM: dts: Fix omap2 specific dtsi files by adding the missing entries ARM: OMAP2+: Fix GPMC and simplify bootloader timings for 8250 and smc91x i2c: omap: Fix missing device tree flags for omap2
2013-11-26Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security Pull IMA fixes from James Morris: "These three patches fix regressions in the IMA code in your current tree. The first fixes a couple of bugs in template_desc_init_fields(), and the other two ensure that changes in this kernel don't break userspace" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security: ima: make a copy of template_fmt in template_desc_init_fields() ima: do not send field length to userspace for digest of ima template ima: do not include field length in template digest calc for ima template
2013-11-26Merge tag 'ntb-3.13' of git://github.com/jonmason/ntbLinus Torvalds
Pull non-transparent bridge updates from Jon Mason: "NTB driver bug fixes to address a missed call to pci_enable_msix, NTB-RP Link Up issue, Xeon Doorbell errata workaround, ntb_transport link down race, and correct dmaengine_get/put usage. Also, clean-ups to remove duplicate defines and document a hardware errata. Finally, some changes to improve performance" * tag 'ntb-3.13' of git://github.com/jonmason/ntb: NTB: Disable interrupts and poll under high load NTB: Enable Snoop on Primary Side NTB: Document HW errata NTB: remove duplicate defines NTB: correct dmaengine_get/put usage NTB: Fix ntb_transport link down race ntb: Fix missed call to pci_enable_msix() NTB: Fix NTB-RP Link Up NTB: Xeon Doorbell errata workaround
2013-11-26drm/i915: add a debugfs entry for power domain infoImre Deak
Add a debugfs entry showing the use-count for all power domains of each power well. v3: address comments from Paulo: - simplify power_domain_str() by using a switch table - move power_well::domain_count to power_domains - WARN_ON decrementing a 0 refcount Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: add a default always-on power wellImre Deak
So far we distinguished platforms without a dynamic power well with the HAS_POWER_WELL macro and for such platforms we didn't call any power domain functions. Instead of doing this check we can add an always-on power well for these platforms and call the power domain functions unconditionally. For always-on power wells we only increase/decrease their refcounts, otherwise they are nop. This makes high level driver code more readable and as a bonus provides some idea of the current power domains state for all platforms (once the relevant debugfs entry is added). v3: rename intel_power_wells to i9xx_always_on_power_well (Paulo) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: don't do BDW/HSW specific powerdomains init on other platformsImre Deak
Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: protect HSW power well check with IS_HASWELL in redisable_vgaJesse Barnes
This may need work if other platforms do the same thing, but in the meantime we should avoid looking at HSW specific bits in this generic function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [added IS_BROADWELL too as that needs the same handling (Imre)] Signed-off-by: Imre Deak <imre.deak@intel.com> [danvet: Add Imre's missing sob.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: use IS_HASWELL/BROADWELL instead of HAS_POWER_WELLImre Deak
In intel_display_capture_error_state we use HAS_POWER_WELL to check if we are running on Haswell/Broadwell when accessing HSW_PWR_WELL_DRIVER which is specific to these platforms. Future platforms with power wells don't have this register, so HAS_POWER_WELL won't work there any more. Use IS_HASWELL/IS_BROADWELL instead. v3: fix using logical || instead of bitwise | (Paulo) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: add always-on power wells instead of special casing themImre Deak
Instead of using a separate function to check whether a power domain is is always on, add an always-on power well covering all these power domains and do the usual get/put on these unconditionally. Since we don't assign a .set handler for these the get/put won't have any effect besides the adjusted refcount. This makes the code more readable and provides debug info also on the use of always-on power wells (once the relevant debugfs entry is added.) v3: make is_always_on to be bool instead of a bit field (Paulo) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: support for multiple power wellsImre Deak
HW generations so far had only one always-on power well and optionally one dynamic power well. Upcoming HW gens may have multiple dynamic power wells, so add some infrastructure to support them. The idea is to keep the existing power domain API used by the rest of the driver and create a mapping between these power domains and the underlying power wells. This mapping can differ from one HW to another but high level driver code doesn't need to know about this. Through the existing get/put API it would just ask for a given power domain and the power domain framework would make sure the relevant power wells get enabled in the right order. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26drm/i915: add audio power domainImre Deak
This way the code is simpler and can also be used for other platforms where the audio power domain->power well mapping is different. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26PCI: mvebu: Return 'unsupported' for Interrupt Line and Interrupt PinJason Gunthorpe
The emulated bridge does not support interrupts, so it should return the value 0 for Interrupt Line and Interrupt Pin. This indicates that interrupts are not supported. Since Max_Lat and Min_Gnt are also in the same 32-bit word, we return 0 for them, which means "do not care." This corrects an error message from the kernel: pci 0000:00:01.0: of_irq_parse_pci() failed with rc=135 Which is due to the default return of 0xFFFFFFFF indicating that interrupts are supported. The error message regression was caused by 16b84e5a505 ("of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.") Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
2013-11-26xen/gnttab: leave lazy MMU mode in the case of a m2p override failureMatt Wilson
Commit f62805f1 introduced a bug where lazy MMU mode isn't exited if a m2p_add/remove_override call fails. Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Reviewed-by: Anthony Liguori <aliguori@amazon.com> Cc: xen-devel@lists.xenproject.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Matt Wilson <msw@amazon.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> CC: stable@vger.kernel.org
2013-11-26drm/i915: take mode config lock around crtc disable at suspendJesse Barnes
This is just a theoretical issue, but we need to do this to prevent the WARN in pipe_from_connector at suspend time. This regression has been introduce in commit 7bd688cd66db93f6430f6e2b3145ee5686daa315 Author: Jani Nikula <jani.nikula@intel.com> Date: Fri Nov 8 16:48:56 2013 +0200 drm/i915: handle backlight through chip specific functions https://bugs.freedesktop.org/show_bug.cgi?id=71978 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26Merge branch 'clockevents/fixes' of ↵Thomas Gleixner
git://git.linaro.org/people/dlezcano/linux into timers/urgent * Hide event stream Kconfig option for the arch_arm_timer for ARM=n * Fix a missing a clk_put in case the registering of the sh_mtu[2] drivers fails. * Reuse clockevents_config_and_register for the at91rm9200_time timer
2013-11-26drm/i915: split fb allocation and initialization v2Jesse Barnes
If we use a stolen buffer, our probe callback shouldn't allocate a new buffer; we should re-use the one from the BIOS instead if possible. v2: fix locking (Jesse) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26Merge branch 'fix/firewire' into for-linusTakashi Iwai
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding
The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot
This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding
The clock for the PWM controller is slightly different from other peripheral clocks on Tegra30. The clock source mux field start at bit position 28 rather than 30. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding
There are two GPUs on Tegra30 and each of them uses a separate clock, so the secondary clock needs to be initialized in order for the gr3d module to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen
Add disp1 and disp2 clocks to the clock initialization table. These clocks are required for display and HDMI support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo
Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2013-11-26clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo
Hook the functions for CPU hotplug support. After the CPU is hot unplugged, the flow controller will handle to clock gate the CPU clock. But still need to implement an empty function to avoid warning message. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com>
2013-11-26clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver
Implement clock support for Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra124: Add new peripheral clocksPeter De Schrijver
Tegra124 introduces a number of new peripheral clocks. This patch adds those to the common peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver
Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver
Tegra124 has a clock which consists of a mux and a fractional divider. Add support for this. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver
Tegra124 has periph clocks which share the hw register. Hence locking is required. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Add periph regs bank XPeter De Schrijver
Tegra124 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: Add support for PLLSSPeter De Schrijver
Tegra124 introduces a new PLL type, PLLSS. Add support for it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move tegra20 to common infraPeter De Schrijver
Move tegra20 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move tegra30 to common infraPeter De Schrijver
Move tegra30 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver
Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver
Introduce new files for fixed and PMC clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver
Introduce a new file for peripheral clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT clocks will be initialized here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver
Move audio clocks and PLLA initialization to a common file so it can be used by multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114 which specifies which common clocks are available on Tegra114 and what their DT IDs are. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver
Add a common infra for registering clkdev. This allows decoupling clk registration from clkdev registration. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add common infra for DT clocksPeter De Schrijver
Introduce a common infrastructure for sharing clock initialization between SoCs. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add header for common tegra clock IDsPeter De Schrijver
Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
generated by cgit (git 2.34.1) at 2025-09-16 00:59:19 +0000