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2016-10-04mfd: arizona: Add sensible return value to some error pathsCharles Keepax
There are some cases in arizona_dev_init, such as where we don't recognise the chip ID, in which we head to the error path without setting a sensible error code in ret. This would lead to the chip silently failing probe, as it would still return 0. Fix this up by adding appropriate sets of the return value. Whilst adding these update the existing paths that do return an error when the chip is not recognised to use ENODEV, which seems like a better fit. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: Add Samsung Exynos Low Power Audio Subsystem driverSylwester Nawrocki
This patch adds common driver for the Top block of the Samsung Exynos SoC Low Power Audio Subsystem. This is a minimal driver which prepares resources for IP blocks like I2S, audio DMA and UART and exposes a regmap for the Top block registers. Also system power ops are added to ensure the Audio Subsystem is operational after system suspend/resume cycle. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: Add DT bindings documentation for Samsung Exynos LPASSSylwester Nawrocki
This patch adds documentation of the DT bindings for the Samsung Exynos SoC Low Power Audio Subsystem. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: da9053: Ensure the FAULT_LOG is cleared during MFD driver probeSteve Twiss
The function da9052_clear_fault_log() is added to mitigate the case of persistent data being transferred between reboots. Clearance of any the persistent information within the DA9053 FAULT_LOG register must be completed during start-up so the fault-log does not continue with previous values. A clearance function has been added here in the kernel driver because wiping the fault-log cannot be counted on outside the Linux kernel. Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com> Reviewed-by: Adam Thomson <adam.thomson.opensource@diasemi.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: dm355evm_msp: Refactoring for add_child()Markus Elfring
Adjust jump targets according to the Linux coding style convention. Another check for the variable "status" can be omitted then at the end. Link: https://lkml.kernel.org/g/<20160628163146.GG29166@dell> Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: rtsx_usb: Avoid setting ucr->current_sg.statusLu Baolu
Member "status" of struct usb_sg_request is managed by usb core. A spin lock is used to serialize the change of it. The driver could check the value of req->status, but should avoid changing it without the hold of the spinlock. Otherwise, it could cause race or error in usb core. This patch could be backported to stable kernels with version later than v3.14. Cc: stable@vger.kernel.org # 3.14+ Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Roger Tseng <rogerable@realtek.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: ucb1x00: Allow IRQ probing to work with IRQs > 32Russell King
probe_irq_on() only returns non-zero if it found any interrupts below IRQ32 which could be probe candidates. If all the probable interrupts are higher than 32, then this will cause a failure. Fix this. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: qcom_rpm: Handle message RAM clockLinus Walleij
The MSM8660, APQ8060, IPQ806x and MSM8960 have a GCC clock to the message RAM used by the RPM. This needs to be enabled for messages to pass through. This is a crude solution that simply prepare/enable at probe() and disable/unprepare at remove(). More elaborate PM is probably possible to add later. The construction uses IS_ERR() to gracefully handle the platforms that do not provide a message RAM clock. It will bail out of probe only if the clock is hitting a probe deferral situation. Of course this requires the proper device tree set-up: rpm: rpm@104000 { compatible = "qcom,rpm-msm8660"; clocks = <&gcc RPM_MSG_RAM_H_CLK>; clock-names = "ram"; ... }; I have provided this in the MSM8660 device tree, and will provide patches for the other targets. Cc: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: max14577: Change Krzysztof Kozlowski's email to kernel.orgKrzysztof Kozlowski
Change my email address to kernel.org instead of Samsung one for the purpose of any future contact. The copyrights remain untouched and are attributed to Samsung. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04Documentation: mfd: Add DT bindings for the LP873XKeerthy
The lp873x series of PMICs have a bunch of regulators and a couple of GPO(General Purpose Outputs). Add information for the MFD and regulator drivers. Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: intel_soc_pmic_bxtwc: Add bxt_wcove_usbc deviceBin Gao
The Intel Whiskey Cove PMIC includes several function units, e.g. ADC, thermal, USB Type-C, GPIO, etc. The corresponding device has to be created in the mfd driver(intel_soc_pmic_bxtwc.c). This change adds the USB Type-c device. Signed-off-by: Bin Gao <bin.gao@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDsMika Westerberg
Intel Kaby Lake PCH-H has the same LPSS than Intel Sunrisepoint. Add the new IDs to the list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: 88pm80x: Double shifting bug in suspend/resumeDan Carpenter
set_bit() and clear_bit() take the bit number so this code is really doing "1 << (1 << irq)" which is a double shift bug. It's done consistently so it won't cause a problem unless "irq" is more than 4. Fixes: 70c6cce04066 ('mfd: Support 88pm80x in 80x driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: altera-a10sr: Make altr_a10sr_regmap_config static constAxel Lin
It's only used in this driver and never get modified, make it static const. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: wm8350-i2c: Make sure the i2c regmap functions are compiledUwe Kleine-König
This fixes a compile failure: drivers/built-in.o: In function `wm8350_i2c_probe': core.c:(.text+0x828b0): undefined reference to `__devm_regmap_init_i2c' Makefile:953: recipe for target 'vmlinux' failed Fixes: 52b461b86a9f ("mfd: Add regmap cache support for wm8350") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: da9063: Update author information to remove incorrect e-mail addressesSteve Twiss
Remove incorrect e-mail addresses from the copyright header and MODULE_AUTHOR() macro. These e-mail addresses are no longer in use. The author names have not been changed, only the e-mail addresses have been deleted from the source files. Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: axp20x: Add AXP209 GPIO supportMaxime Ripard
Now that we have a GPIO driver for the AXP209, we can add it to our MFD. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04mfd: qcom_rpm: Add missing of_node_put after calling of_parse_phandlePeter Chen
of_node_put needs to be called when the device node which is got from of_parse_phandle has finished using. Signed-off-by: Peter Chen <peter.chen@nxp.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04Merge branches 'ib-mfd-gpio-4.9', 'ib-mfd-gpio-regulator-4.9', ↵Lee Jones
'ib-mfd-input-4.9', 'ib-mfd-regulator-4.9', 'ib-mfd-regulator-4.9.1', 'ib-mfd-regulator-rtc-4.9', 'ib-mfd-regulator-rtc-4.9-1' and 'ib-mfd-rtc-4.9' into ibs-for-mfd-merged
2016-10-04mfd: arizona: Add gating of external MCLKn clocksSylwester Nawrocki
This patch adds requesting of the clocks supplied on MCLK1, MCLK2 pins, gating of the 32k clock is added to the arizona_clk32k_enable(), arizona_clk32k_disable() helpers. It's a temporary change until the CODEC's clock controller gets exposed through the clk API and is helpful for board configurations where the MCLK clocks are not provided by always on oscillators. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04MIPS: uprobes: Flush icache via kernel addressJames Hogan
Update arch_uprobe_copy_ixol() to use the kmap_atomic() based kernel address to flush the icache with flush_icache_range(), rather than the user mapping. We have the kernel mapping available anyway and this avoids having to switch to using the new __flush_icache_user_range() for the sake of Enhanced Virtual Addressing (EVA) where flush_icache_range() will become ineffective on user addresses. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14154/ Patchwork: https://patchwork.linux-mips.org/patch/14308/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: cacheflush: Use __flush_icache_user_range()James Hogan
The cacheflush(2) system call uses flush_icache_range() to flush a range of usermode addresses from the icache, so change it to utilise the new __flush_icache_user_range() API to allow the more generic flush_icache_range() to be changed to work on kernel addresses only. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: c-r4k: Split user/kernel flush_icache_range()James Hogan
flush_icache_range() is used for both user addresses (i.e. cacheflush(2)), and kernel addresses (as the API documentation describes). This isn't really suitable however for Enhanced Virtual Addressing (EVA) where cache operations on usermode addresses must use a different instruction, and the protected cache ops assume user addresses, making flush_icache_range() ineffective on kernel addresses. Split out a new __flush_icache_user_range() and __local_flush_icache_user_range() for users which actually want to flush usermode addresses (note that flush_icache_user_range() already exists on various architectures but with different arguments). The implementation of flush_icache_range() will be changed in an upcoming commit to use unprotected normal cache ops so as to always work on the kernel mode address space. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: c-r4k: Drop bc_wback_inv() from icache flushJames Hogan
The EVA conditional bc_wback_inv() at the end of flush_icache_range() to flush the modified code all the way back to RAM was apparently there for debug purposes and to accommodate the Malta EVA configuration which makes use of a physical alias, and didn't use the CP0_EBase.WG (Write Gate) bit to put the exception vector in the same physical alias where the exception vector code is written and is being flushed. Now that CP0_EBase.WG is used, lets drop this flush. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14151/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: traps: Ensure full EBase is writtenMatt Redfearn
On CPUs which support the EBase WG (write gate) flag, the most significant bits of the exception base can be changed. Firmware running on a VP(E) using MIPS rproc may change EBase to point into the user segment where the firmware is located such that it can service interrupts. When control is transferred back to the kernel the EBase must be switched back into the kernel segment, such that the kernel's exception vectors are used. Similarly when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled an exception vector is allocated from bootmem, and written to the EBase register. Due to the WG flag being clear, only bits 29:12 will be written. Asside from the rproc case above this is normally fine (as it will usually be a low allocation within the KSeg0 range, however when Enhanced Virtual Addressing (EVA) is enabled the allocation may be outside of the traditional KSeg0/KSeg1 address range, resulting in the wrong EBase being written. Correct both cases (configure_exception_vector() for the boot CPU, and per_cpu_trap_init() for secondary CPUs) to write EBase with the WG flag first if supported. On the Malta EVA configuration, KSeg0 is mapped to physical address 0, and memory is allocated from the KUSeg segment which is mapped to physical address 0x80000000, which physically aliases the RAM at 0. This only worked due to the exception base address aliasing the same underlying RAM that was written to & cache flushed, and due to flush_icache_range() going beyond the call of duty and flushing from the L2 cache too (due to the differing physical addresses). Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14150/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: traps: Convert ebase to KSEG0James Hogan
When allocating boot memory for the exception vector when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled, try to ensure that the virtual address resides in KSeg0 (and WARN should that not be possible). This will be helpful on MIPS64 cores supporting the CP0_EBase Write Gate (WG) bit once we start using the WG bit to write the full ebase into CP0_EBase, as we ideally need to avoid hitting the architecturally poorly defined exception base for Cache Errors when CP0_EBase is in XKPhys. An exception is made for Enhanced Virtual Addressing (EVA) kernels which allow segments to be rearranged and to become uncached during cache error handling, making it valid for ebase to be elsewhere. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: traps: 64bit kernels should read CP0_EBase 64bitJames Hogan
When reading the CP0_EBase register containing the WG (write gate) bit, the ebase variable should be set to the full value of the register, i.e. on a 64-bit kernel the full 64-bit width of the register via read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width including bits 31:30 which may be writeable. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14148/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs.Matt Redfearn
This patch enables the MIPS CPS driver for MIPSr6 CPUs. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: linux-mips@linux-mips.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14228/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_otherMatt Redfearn
All calls to mips_cpc_lock_other should be wrapped in mips_cm_lock_other. This only matters if the system has CM3 and is using cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b) any systems with CM > 3 have not been able to use cpu idle until now. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hogan <james.hogan@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/14227/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Support CM3 changes to Coherence Enable RegisterMatt Redfearn
MIPS CM3 changed the management of coherence. Instead of a coherence control register with a bitmask of coherent domains, CM3 simply has a coherence enable register with a single bit to enable coherence of the local core. Support this by clearing and setting this single bit to disable / enable coherence. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Tony Wu <tung7970@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nikolay Martynov <mar.kolya@gmail.com> Cc: Kees Cook <keescook@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14226/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Add MIPSr6 CPU supportMatt Redfearn
This patch adds support for CPUs implementing the MIPSr6 ISA to the CPS power management code. Three changes are necessary: 1. In MIPSr6, coupled coherence is necessary when CPUS implement multiple Virtual Processors (VPs). 2. MIPSr6 virtual processors are more like real cores and cannot yield to other VPs on the same core, so drop the MT ASE yield instruction. 3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the MT ASE TCHalt CP0 register. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Kees Cook <keescook@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14225/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Remove selection of sync typesMatt Redfearn
Instead of selecting an implementation or vendor specific sync type for the required sync operations, always use the architecturally mandated sync types which previous patches have put in place. The selection of special sync types is now redundant an can be removed. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Kees Cook <keescook@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14223/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Use MIPS standard completion barrierMatt Redfearn
SYNC type 0 is defined in the MIPS architecture as a completion barrier where all loads/stores in the pipeline before the sync instruction must complete before any loads/stores subsequent to the sync instruction. In places where we require loads / stores be globally completed, use the standard completion sync stype. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Use MIPS standard lightweight ordering barrierMatt Redfearn
Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but architecturally defined ordering barrier. If a CPU does not implement it, the arch specifies that it must fall back to SYNC(0). In places where we require that the instruction stream not be reordered, but do not require that loads / stores are gloablly completed, use the defined standard sync stype. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14221/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Barrier: Add definitions of SYNC stype valuesMatt Redfearn
Add the definitions of sync stype 0 (global completion barrier) and sync stype 0x10 (local ordering barrier) to barrier.h for use with the sync instruction. These types are defined by the MIPS Instruction Set since R2 of the architecture and are documented in document MD00087 table 6.5. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14222/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Update comments on barrier instructionsMatt Redfearn
This code makes large use of barriers, which had quite vague descriptions. Update the comments to make the choice of barrier and reason for it more clear. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Kees Cook <keescook@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14220/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: pm-cps: Change FSB workaround to CPU blacklistMatt Redfearn
The check for whether a CPU required the FSB flush workaround previously required every CPU not requiring it to be whitelisted. That approach does not scale well as new CPUs are introduced so change the default from a WARN and returning an error to just returning 0. Any CPUs requiring the workaround can then be added to the blacklist. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: CPC: Avoid lock when MIPS CM >= 3 is presentMatt Redfearn
MIPS CM version 3 removed the CPC_CL_OTHER register and instead the CM_CL_OTHER register is used to redirect the CPC_OTHER region. As such, we should not write the unimplmented register and can avoid the spinlock as well. These lock functions should aleady be called within the context of a mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region will be accessed. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14219/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: CPC: Convert bare 'unsigned' to 'unsigned int'Matt Redfearn
Checkpatch complains about use of bare unsigned type. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Fix PCI interrupt routing on D-Link DSR-500N.Aaro Koskinen
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Add DTS for D-Link DSR-500N.Aaro Koskinen
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14249/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Split dlink_dsr-1000n.dts to allow reuse with D-Link DSR-500N.Aaro Koskinen
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14248/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Delete unused cvmx-mdio.hAaro Koskinen
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14206/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Delete legacy code for PHY accessAaro Koskinen
PHY access through the board helper is impossible with the current drivers, so delete this code. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Delete unused cvmx_helper_board_link_set_phy.Aaro Koskinen
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14204/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Delete unused cvmx_override_board_link_get.Aaro Koskinen
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14203/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Don't try to maintain link state in early init.Aaro Koskinen
Leave that to actual ethernet/phy drivers. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14202/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: Octeon: Delete legacy hack for broken bootloadersAaro Koskinen
Delete legacy hack for broken bootloaders. The warning has been in kernel for several years, and if there are still users using such bootloaders, they can fix the boot by supplying a proper DTB. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: BCM63xx: Let clk_disable() return immediately if clk is NULLMasahiro Yamada
In many of clk_disable() implementations, it is a no-op for a NULL pointer input, but this is one of the exceptions. Making it treewide consistent will allow clock consumers to call clk_disable() without NULL pointer check. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/14264/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-04MIPS: PCI: Reduce stack frame usageKeith Busch
This patch removes creating a fake pci device in MIPS early config access and instead just uses the pci bus to get the same functionality. The struct pci_dev is too large to allocate on the stack, and was relying on compiler optimizations to remove its usage. Signed-off-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14253/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
generated by cgit (git 2.34.1) at 2025-09-15 19:11:35 +0000