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2020-03-20io_uring: make sure accept honor rlimit nofileJens Axboe
Just like commit 4022e7af86be, this fixes the fact that IORING_OP_ACCEPT ends up using get_unused_fd_flags(), which checks current->signal->rlim[] for limits. Add an extra argument to __sys_accept4_file() that allows us to pass in the proper nofile limit, and grab it at request prep time. Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-03-20io_uring: make sure openat/openat2 honor rlimit nofileJens Axboe
Dmitry reports that a test case shows that io_uring isn't honoring a modified rlimit nofile setting. get_unused_fd_flags() checks the task signal->rlimi[] for the limits. As this isn't easily inheritable, provide a __get_unused_fd_flags() that takes the value instead. Then we can grab it when the request is prepared (from the original task), and pass that in when we do the async part part of the open. Reported-by: Dmitry Kadashev <dkadashev@gmail.com> Tested-by: Dmitry Kadashev <dkadashev@gmail.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-03-20staging: mt7621-pci: be sure gpio descriptor is null on failsSergio Paracuellos
Function 'devm_gpiod_get_index_optional' returns NULL if the descriptor is invalid and the error associated for the error pointer is ENOENT. Sometimes if the pin is just assigned the error associated for the pointer might not be ENOENT but other. In order to avoid weirds behaviours if this happen set descriptor to NULL in the driver port structure. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-pci: change variable to print for slotSergio Paracuellos
We are using the counter to print the slot which has been enabled. Use the correct associated slot for the port instead. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-5-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-pci: use only two phys from device treeSergio Paracuellos
In order to align work with the mt7621-pci-phy part of the driver and device tree which is now using only two real phys one of them dual ported properly parse the device tree and don't call phy initialization for the slot 1 because is being taking into account when the phy for the slot 0 is instantiated. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-dts: set up only two pcie physSergio Paracuellos
This soc has only two real pcie phys one of them having a different register to enable and disable it. Change this to have only two dt nodes for the phys and use 'phy-cells' properly to say if the phy has dual ports. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-pci-phy: avoid to create to different phys for a dual port oneSergio Paracuellos
This soc has two phy's for the pcie one of them using just a different register for settig it up but sharing all the rest of the config. Until now we was presenting this schema as three different phy's in the device tree using the 'phy-cells' node property to discriminate an index and setting up a complete phy for the dual port index. This sometimes worked properly but reconfiguring the same registers twice presents sometimes some unstable pcie links and the ports was not properly being detected. The problems only appears on hard resets and soft resets was properly working. Instead of having this schema just set two phy's in the device ree and use the 'phy-cells' property to say if the port has or not a dual port. Doing this configuration and set up becomes easier, LOC is decreased and the behaviour also gets deterministic with properly and stable pcie links in both hard and soft resets. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: vc04_services: interface: vchi: Correct long line comments and make ↵R Veera Kumar
them C89 style Correct long lines of comments to respect 80 character per line limit and make them C89 style one. Found using checkpatch.pl. Signed-off-by: R Veera Kumar <vkor@vkten.in> Link: https://lore.kernel.org/r/20200320024337.4754-1-vkor@vkten.in Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: rtl8723bs: hal: Correct typos in commentsR Veera Kumar
Correct typos in comments. Misspellings found using checkpatch.pl. Signed-off-by: R Veera Kumar <vkor@vkten.in> Link: https://lore.kernel.org/r/46d4e7cd66ec8d5bf7445201e10e3d50fe1c618e.1584687545.git.vkor@vkten.in Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: rtl8723bs: hal: Correct multi-line comments as per coding styleR Veera Kumar
Correct multi-line comments as per coding style to respect 80 characters per line limit. Amalgamate individual lines into single multiline comment. Reorganize it for readability. Signed-off-by: R Veera Kumar <vkor@vkten.in> Link: https://lore.kernel.org/r/5b5cdb520df6d579a6659fbe45ac545628be50e4.1584687545.git.vkor@vkten.in Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: gdm724x: use netdev_err() instead of pr_err()Lourdes Pedrajas
use netdev_err() which is a message printing function specific for network devices instead of pr_err(), in function netlink_send(). Signed-off-by: Lourdes Pedrajas <lu@pplo.net> Link: https://lore.kernel.org/r/20200320003947.31726-1-lu@pplo.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: rtl8712: Remove unnecessary bracesGokce Kuler
Remove unnecessary braces for single statement block Signed-off-by: Gokce Kuler <gokcekuler@gmail.com> Link: https://lore.kernel.org/r/20200320000326.GA9349@siyah2 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHYSandeep Maheswaram
Added support for overriding bias-ctrl-value,charge-ctrl-value and hsdisc-trim-value params for QUSB2 V2 PHY Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHYSandeep Maheswaram
Added new structure for overriding tuning parameters in QUSB2 V2 PHY as the override params are increased due to usage of generic QUSB2 V2 phy table. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning parametersSandeep Maheswaram
Add support for overriding QUSB2 V2 phy tuning parameters in device tree bindings. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add generic QUSB2 V2 PHY supportSandeep Maheswaram
Add generic QUSB2 V2 PHY table so the respective phys can use the same table. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: qcom,qusb2: Add compatibles for QUSB2 V2 phy and SC7180Sandeep Maheswaram
Add compatibles for generic QUSB2 V2 phy which can be used for sdm845 and sc7180. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: qcom,qusb2: Convert QUSB2 phy bindings to yamlSandeep Maheswaram
Convert QUSB2 phy bindings to DT schema format using json-schema. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: rk-inno-usb2: Decrease verbosity of repeating log.Christoph Muellner
phy-rockchip-inno-usb2 logs the message "phy-ff2c0000.syscon:usb2-phy@100.2: charger = INVALID_CHARGER" constantly with a frequency of about 1 Hz and a verbosity level of INFO. As this is clearly annoying, this patch decreases the log level to DEBUG. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: amlogic: Add Amlogic A1 USB2 PHY DriverHanjie Lin
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. It supports host mode only. Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: Add Amlogic A1 USB2 PHY BindingsHanjie Lin
Add the Amlogic A1 Family USB2 PHY Bindings It supports Host mode only. Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: ti: gmii-sel: add support for am654x/j721e socGrygorii Strashko
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding support for TI AM654x/J721E SoCs PHY interface selection. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e socGrygorii Strashko
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qualcomm: usb: Add SuperSpeed PHY driverJorge Ramirez-Ortiz
Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: Sriharsha Allenki's <sallenki@codeaurora.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: Add Qualcomm USB SuperSpeed PHY bindingsJorge Ramirez-Ortiz
Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY appears in a number of SoCs on various flavors of 20nm and 28nm nodes. This commit adds information related to the 28nm node only. Based on Sriharsha Allenki's <sallenki@codeaurora.org> original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driverShawn Guo
Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY bindingSriharsha Allenki
Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps, 28nm components] Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: remove qcom-dwc3-usb-phyJorge Ramirez-Ortiz
This binding is not used by any driver. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a new reference clockChunfeng Yun
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it, this can avoid confusion when support new platforms Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: make the ref clock optionalChunfeng Yun
Sometimes the reference clock of USB3 PHY comes from oscillator directly, and no need refer to a fixed-clock in DTS anymore if make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a property for internal resistanceChunfeng Yun
This is used to tune J-K voltage by internal R (resistance), the range is [0, 31], the resistance value is about 6.9K ohm for 0, 3.8K ohm for 31, and the step is 1K ohm Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a property for disconnect thresholdChunfeng Yun
This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy-mtk-tphy: add the properties about address mappingChunfeng Yun
Add three required properties about the address mapping, including '#address-cells', '#size-cells' and 'ranges' Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy-mtk-tphy: add a new reference clockChunfeng Yun
Usually the digital and analog phys use the same reference clock, but on some platforms, they are separated, so add another optional clock to support it. In order to keep the clock names consistent with PHY IP's, use the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it to avoid confusion Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy-mtk-tphy: make the ref clock optionalChunfeng Yun
Make the ref clock optional, then we no need refer to a fixed-clock in DTS anymore when the clock of USB3 PHY comes from oscillator directly Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy-mtk-tphy: add two optional properties for u2phyChunfeng Yun
Add two optional properties, one for tuning J-K voltage by INTR, another for disconnect threshold, both of them are related with connect detection Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: amlogic: G12A: Fix misuse of GENMASK macroJoe Perches
Arguments are supposed to be ordered high then low. Signed-off-by: Joe Perches <joe@perches.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom: qmp: Use power_on/off ops for PCIeBjorn Andersson
The PCIe PHY initialization requires the attached device to be present, which is primarily achieved by the PCI controller driver. So move the logic from init/exit to power_on/power_off. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-pcie: Add SoC-dependent phy-mode function supportKunihiko Hayashi
Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-pcie: Add legacy SoC support for Pro5Kunihiko Hayashi
Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failureKunihiko Hayashi
In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-usb3hs: Add legacy SoC support for Pro5Kunihiko Hayashi
Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-usb3ss: Add Pro5 supportKunihiko Hayashi
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphyKunihiko Hayashi
This adds compatible string for Pro5 SoC that needs to manage gio clock and reset. And Pro4 SoC uses USB2 PHY instead of USB3 HS-PHY, so this removes Pro4 description from usb3-hsphy. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: socionext: Use devm_platform_ioremap_resource()Kunihiko Hayashi
Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qmp: Add MSM8996 UFS QMP supportBjorn Andersson
The support for the 14nm MSM8996 UFS PHY is currently handled by the UFS-specific 14nm QMP driver, due to the earlier need for additional operations beyond the standard PHY API. Add support for this PHY to the common QMP driver, to allow us to remove the old driver. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Add support for subnode bindingsSwapnil Jakhade
Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Add platform dependent initialization structureSwapnil Jakhade
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit (git 2.34.1) at 2025-09-12 20:54:50 +0000