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2017-04-24dm integrity: support larger block sizesMikulas Patocka
The DM integrity block size can now be 512, 1k, 2k or 4k. Using larger blocks reduces metadata handling overhead. The block size can be configured at table load time using the "block_size:<value>" option; where <value> is expressed in bytes (defult is still 512 bytes). It is safe to use larger block sizes with DM integrity, because the DM integrity journal makes sure that the whole block is updated atomically even if the underlying device doesn't support atomic writes of that size (e.g. 4k block ontop of a 512b device). Depends-on: 2859323e ("block: fix blk_integrity_register to use template's interval_exp if not 0") Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2017-04-24dm integrity: various small changes and cleanupsMikulas Patocka
Some coding style changes. Fix a bug that the array test_tag has insufficient size if the digest size of internal has is bigger than the tag size. The function __fls is undefined for zero argument, this patch fixes undefined behavior if the user sets zero interleave_sectors. Fix the limit of optional arguments to 8. Don't allocate crypt_data on the stack to avoid a BUG with debug kernel. Rename all optional argument names to have underscores rather than dashes. Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2017-04-24dm: mark targets that pass integrity dataMikulas Patocka
A dm-crypt on dm-integrity device incorrectly advertises an integrity profile on the DM crypt device. It can be seen in the files "/sys/block/dm-*/integrity/*" that both dm-integrity and dm-crypt target advertise the integrity profile. That is incorrect, only the dm-integrity target should advertise the integrity profile. A general problem in DM is that if we have a DM device that depends on another device with an integrity profile, the upper device will always advertise the integrity profile, even when the target driver doesn't support handling integrity data. Most targets don't support integrity data, so we provide a whitelist of targets that support it (linear, delay and striped). The targets that support passing integrity data to the lower device are marked with the flag DM_TARGET_PASSES_INTEGRITY. The DM core will now advertise integrity data on a DM device only if all the targets support the integrity data. Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2017-04-24dm table: replace while loops with for loopsMikulas Patocka
Also remove some unnecessary use of uninitialized_var(). Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2017-04-24Merge branch '1GbE' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue Jeff Kirsher says: ==================== 1GbE Intel Wired LAN Driver Updates 2017-04-20 This series contains updates to e1000, e1000e, igb/vf and ixgb. Tobias Klauser cleans up e1000, ixgb and igbvf from having a local function or structure for netdev stats. Bernd Faust fixes an issue for 82579 devices, where the clock frequency was being incorrectly set for these devices. These devices only support 96MHz, so make sure they are set to use only that. Yury Kylulin extends the work Jake and Alex did for ixgbe in MAC filter handling into the igb driver. Kim Tatt Chuah enables igb to wake up by packet and to read the necessary Wake Up Status (WUS) and Wake Up Packet Memory (WUPM) registers. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24perf tools: Add compress.h for the *_decompress_to_file() headersArnaldo Carvalho de Melo
Out of util.h, the implementations were already in separate files, that are built conditionally. Link: http://lkml.kernel.org/n/tip-0ur7szxsb59f8758kfe63prb@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2017-04-24perf mem: Fix display of data source snoop indicationAndi Kleen
'perf mem report' doesn't display the data source snoop indication correctly. In the kernel API the definition is: #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ but the table used by the perf tools exchanged "Hit" and "Miss": "None", "Miss", "Hit", Fix the table in perf. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/20170419174940.13641-1-andi@firstfloor.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2017-04-24perf debug: Move dump_stack() and sighandler_dump_stack() to debug.hArnaldo Carvalho de Melo
Two more out of util.h. Link: http://lkml.kernel.org/n/tip-polkuxm1cpr06lbgue5pyqum@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2017-04-24perf kvm: Make function only used by 'perf kvm' staticArnaldo Carvalho de Melo
No need to have this polluting util.h, it was polluted enough already. Link: http://lkml.kernel.org/n/tip-wfdidqlwbvi5y0s61kv6z2gn@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2017-04-24ext4: Improve comments in ext4_quota_{on|off}()Jan Kara
Improve comments in ext4_quota_{on|off}() to explain that returning success despite ext4_journal_start() failing is deliberate. Signed-off-by: Jan Kara <jack@suse.cz>
2017-04-24fsnotify: remove a stray unlockDan Carpenter
We recently shifted this code around, so we're no longer holding the lock on this path. Fixes: 755b5bc681eb ("fsnotify: Remove indirection from mark list addition") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jan Kara <jack@suse.cz>
2017-04-24pinctrl: make artpec6 explicitly non-modularPaul Gortmaker
The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_ARTPEC6 drivers/pinctrl/Kconfig: bool "Axis ARTPEC-6 pin controller driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Lars Persson <lars.persson@axis.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: linux-arm-kernel@axis.com Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24udf: use kmap_atomic for memcpy copyingFabian Frederick
Use temporary mapping for memory copying operations. To avoid any sleeping problem, mark_inode_dirty(inode) was moved after kunmap() in udf_adinicb_readpage() down_write(&iinfo->i_data_sem) set before kmap_atomic() in udf_expand_file_adinicb() Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Jan Kara <jack@suse.cz>
2017-04-24udf: use octal for permissionsFabian Frederick
According to commit f90774e1fd27 ("checkpatch: look for symbolic permissions and suggest octal instead") Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Jan Kara <jack@suse.cz>
2017-04-24hwmon: (tmp103) Use SIMPLE_DEV_PM_OPS helper macroRahul Bedarkar
Replace ifdefs with SIMPLE_DEV_PM_OPS helper macro. Signed-off-by: Rahul Bedarkar <rahulbedarkar89@gmail.com> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2017-04-24pinctrl: aspeed: g5: Add pinconf supportAndrew Jeffery
Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: g4: Add pinconf supportAndrew Jeffery
Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: Add core pinconf supportAndrew Jeffery
Several pinconf parameters have a fairly straight-forward mapping onto the Aspeed pin controller. These include management of pull-down bias, drive-strength, and some debounce configuration. Pin biasing largely is managed on a per-GPIO-bank basis, aside from the ADC and RMII/RGMII pins. As the bias configuration for each pin in a bank maps onto a single per-bank bit, configuration tables will be introduced to describe the ranges of pins and the supported pinconf parameter. The use of tables also helps with the sparse support of pinconf properties, and the fact that not all GPIO banks support biasing or drive-strength configuration. Further, as the pin controller uses a consistent approach for bias and drive strength configuration at the register level, a second table is defined for looking up the the bit-state required to enable or query the provided configuration. Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU. The test method was to set the appropriate bits via devmem and verify the result through the controller's pinconf-pins debugfs file. This simultaneously validates the get() path and half of the set() path. The remainder of the set() path was validated by configuring a handful of pins via the devicetree with the supported pinconf properties and verifying the appropriate registers were touched. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: Document pinconf in devicetree bindingsAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrlAlexandre TORGUE
Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24drm: mali-dp: Check the mclk rate and allow up/down scalingMihail Atanassov
When downscaling, mclk needs to be sufficiently higher than pxlclk in order to be able to fetch the higher-resolution data and produce output pixels. When not scaling, or when upscaling, mclk can be equal to pxlclk. Since the driver doesn't control mclk, just ensure that the requirement is satisfied with the current clock rate. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Enable image enhancement when scalingMihail Atanassov
Apply image enhacement when we are upscaling by a factor of 2 or more in either direction. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Add plane upscaling supportMihail Atanassov
Enable the scaling engine for upscaling a single plane using the polyphase scaler. No image enhancement support or downscaling yet*, and composition result scaling is not implemented. * Downscaling a plane requires mclk > pxlclk. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24pinctrl: stm32: Add STM32F469 MCU supportAlexandre TORGUE
This patch which adds STM32F469 pinctrl and GPIO support, relies on the generic STM32 pinctrl driver. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24Documentation: dt: Remove ngpios from stm32-pinctrl bindingAlexandre TORGUE
Remove "ngpios" bindings definition as it is no more used in stm32 pinctrl driver. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: stm32: replace device_initcall() with arch_initcall()Alexandre TORGUE
Pinctrl has to be registered earlier. Mainly to register bank irqdomain earlier as other devices could use interrupts from those irqdomain. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: stm32: add possibility to use gpio-ranges to declare bank rangeAlexandre TORGUE
Use device tree entries to declare gpio range. It will allow to use no contiguous gpio bank and holes inside a bank. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: armada-37xx: Add gpio supportGregory CLEMENT
GPIO management is pretty simple and is part of the same IP than the pin controller for the Armada 37xx SoCs. This patch adds the GPIO support to the pinctrl-armada-37xx.c file, it also allows sharing common functions between the gpiolib and the pinctrl drivers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24tty: fix comment for __tty_alloc_driver()Thadeu Lima de Souza Cascardo
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@cascardo.eti.br> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2017-04-24init/main: properly align the multi-line commentViresh Kumar
Add a tab before it to follow standard practices. Also add the missing full stop '.'. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2017-04-24init/main: Fix double "the" in commentViresh Kumar
s/the\ the/the Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2017-04-24crypto: algif_aead - Require setkey before accept(2)Stephan Mueller
Some cipher implementations will crash if you try to use them without calling setkey first. This patch adds a check so that the accept(2) call will fail with -ENOKEY if setkey hasn't been done on the socket yet. Fixes: 400c40cf78da ("crypto: algif - add AEAD support") Cc: <stable@vger.kernel.org> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: scomp - add support for deflate rfc1950 (zlib)Giovanni Cabiddu
Add scomp backend for zlib-deflate compression algorithm. This backend outputs data using the format defined in rfc1950 (raw deflate surrounded by zlib header and footer). Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: scomp - allow registration of multiple scompsGiovanni Cabiddu
Add crypto_register_scomps and crypto_unregister_scomps to allow the registration of multiple implementations with one call. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: ccp - Change ISR handler method for a v5 CCPGary R Hook
The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: <stable@vger.kernel.org> # 4.9.x+ Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: ccp - Change ISR handler method for a v3 CCPGary R Hook
The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: <stable@vger.kernel.org> # 4.9.x+ Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: crypto4xx - rename ce_ring_contol to ce_ring_controlColin Ian King
trivial spelling mistake, missing r, rename to ce_ring_control Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: testmgr - Allow ecb(cipher_null) in FIPS modeMilan Broz
The cipher_null is not a real cipher, FIPS mode should not restrict its use. It is used for several tests (for example in cryptsetup testsuite) and also temporarily for reencryption of not yet encrypted device in cryptsetup-reencrypt tool. Problem is easily reproducible with cryptsetup benchmark -c null Signed-off-by: Milan Broz <gmazyland@gmail.com> Acked-by: Stephan Müller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24drm/mali-dp: Add core_id file to the sysfs interfaceLiviu Dudau
Add a core_id file in the driver's sysfs directory, exposing the hardware CORE ID. This is useful to allow userspace to discover the hardware version used. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Add CTM supportMihail Atanassov
All DPs have a COLORADJ matrix which is applied prior to output gamma. Attach that to the CTM property. Also, ensure the input CTM's coefficients can fit in the DP registers' Q3.12 format. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: enable gamma supportMihail Atanassov
Add gamma via the DRM GAMMA_LUT/GAMMA_LUT_SIZE CRTC properties. The expected LUT size is 4096 in order to produce as accurate a set of segments as possible. This version uses only the green channel's gamma curve to set the hardware curve on DP550/650. For the sake of simplicity, it uses the same table of coefficients for all 3 curves on DP500. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
2017-04-24drm: mali-dp: add malidp_crtc_state structMihail Atanassov
Add a custom CRTC state struct to enable storing driver's private state. This patch only adds the base drm_crtc_state struct and the atomic functions that handle it. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: add custom reset hook for planesMihail Atanassov
Now that we are using a custom plane state in mali-dp, we need a bespoke reset that takes into account the larger structure. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> [Updated commit message] Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: remove unused variableArnd Bergmann
The newly introduced function causes a harmless build warning: drivers/gpu/drm/arm/malidp_planes.c: In function 'malidp_plane_atomic_print_state': drivers/gpu/drm/arm/malidp_planes.c:98:23: error: unused variable 'mp' [-Werror=unused-variable] The variable serves no purpose here and can be removed. Fixes: 242f43b69c61 ("drm: mali-dp: add atomic_print_state for planes") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: add atomic_print_state for planesMihail Atanassov
Add function to dump the state of the plane. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Enable power management for the device.Liviu Dudau
Enable runtime and system Power Management. Clocks are now managed from malidp_crtc_{enable,disable} functions. Suspend-to-RAM tested as working on Juno. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Update the state of all planes before re-enabling active CRTCs.Liviu Dudau
Mali DP needs to have all the planes that are becoming inactive in the new state disabled before re-enabling the active CRTC, otherwise we start streaming out data from old pointers in memory. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24pinctrl: armada-37xx: Add pin controller support for Armada 37xxGregory CLEMENT
The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllersGregory CLEMENT
Document the device tree binding for the pin controllers found on the Armada 37xx SoCs. Update the binding documention of the xtal clk which is a subnode of this syscon node. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [Fixed gpios node] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24Merge tag 'vfio-ccw-20170413' of ↵Martin Schwidefsky
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/vfio-ccw into features Pull vfio-ccw fixes from Cornelia Huck: Two fixes for the new vfio-ccw support.
generated by cgit (git 2.34.1) at 2025-10-03 05:52:14 +0000