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2019-06-21drm/amdgpu: add Navi10 pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdkfd: Add navi10 support to amdkfd. (v3)Philip Cox
KFD (kernel fusion driver) is the kernel driver for the compute backend for usermode compute stack. v2: squash in updates (Alex) v3: squash in rebase fixes (Alex) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Philip Cox <Philip.Cox@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: update golden setting programming logicHawking Zhang
Since from soc15, make sure only AndMasked bit get changed when applied or_mask Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: Add navi10 kfd support for amdgpu (v3)Hawking Zhang
KFD (Kernel Fusion Driver) is the compute backend driver for AMD GPUs. v2: squash in updates (Alex) v3: fix warnings (Alex) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Philip Cox <Philip.Cox@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add navi10 common ip block (v3)Hawking Zhang
This adds the core SOC code for navi asics. v1: add place holder and initial basic function (Ray) v2: add new introduced functions to avoid reference NULL pointer (Hawking) v3L squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10Hawking Zhang
Move to the header file. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add gfx v10 implementation (v10)Hawking Zhang
GFX is the graphics and compute block on the GPU. v1: add initial gfx v10 implementation (Ray) v2: convert to new get_vm_pde function in emit_vm_flush (Hawking) v3: switch to new emit ib interfaces (Hawking) v4: squash in updates (Alex) v5: remove unused variables (Alex) v6: v6: some golden regs moved to vbios (Alex) v7: squash in some cleanups (Alex) v8: squash in golden settings update (Alex) v9: squash in whitespace fixes (Ernst Sjöstrand, Alex) v10: squash in GDS backup size fix and GDS/GWS/OA removal rebase fixes (Hawking) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: add ip block mes10.1 (v2)Jack Xiao
MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: enable mes on navi10 and later asicJack Xiao
When amdgpu_mes is enabled and asic family is navi10 and later asic, enable mes per device. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: add definitions of ip callback functionJack Xiao
Abstract mes ip independent function layer. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: add mes header file and definitionJack Xiao
Add dummy header file and definitions of mes. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: add amdgpu_mes driver parameterJack Xiao
amdgpu_mes, which is a driver scope parameter, is used to whether enable mes or not. MES (Micro Engine Scheduler) is the new on chip hw scheduling microcontroller. It can be used to handle queue scheduling and preemption and priorities. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add initial VCN2.0 support (v2)Leo Liu
VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add JPEG2.0 decode ring ib testLeo Liu
Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add JPEG2.0 decode ring testLeo Liu
Use register from JPEG tile, the UVD tile reg won't work for JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add VCN2.0 decode ib testLeo Liu
Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add VCN2.0 decode ring testLeo Liu
Add internal register offset for registers involving in ring tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add Navi10 VCN firmware supportLeo Liu
Add Navi10 to VCN family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add initial support for sdma v5.0 (v6)Hawking Zhang
SDMA (System DMA) is a general purpose DMA engine usable by UMDs for transfers or the kernel for paging or GPUVM updates. v1: support basic funcitonalites includes rb, ib, vm, copy buffer and trap irq v2: convert to use new get_vm_pde in emit_vm_flush v3: retire amdgpu_ttm_set_active_vram_size from sdma v5 v4: retire the redundant hdp_invalidate implementation v5: squash in updates v6: some golden regs moved to vbios Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: set the default value of pa_sc_tile_steering_overrideHawking Zhang
So userspace can access it. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_deviceHawking Zhang
the initial/default value of pa_sc_tile_steering_override need to be exposed to user mode driver Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: disable concurrent flushes for Navi10 v2Christian König
Navi10 have a bug in the SDMA which can theoretically cause memory corruption with concurrent VMID flushes v2: explicitely check Navi10 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: refactor ip list traversalXiaojie Yuan
for each ip, check whether it is needed by amdgpu driver, if yes, record its base addresses v2: change some DRM_INFO to DRM_DEBUG v3: remove unused variable (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add module param for ip discovery enablementXiaojie Yuan
to control enablement. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: stop converting the units of base addressesXiaojie Yuan
the unit is already in dword Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: update definition for struct die_headerXiaojie Yuan
Update to latest spec. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: stop taking psp header into accountXiaojie Yuan
psp will write a header to vram, but the value exposed in RCC_CONFIG_MEMSIZE does not include the memory that this header is written to. Therefore, the interpretation of the table does not need to take the psp header into account. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: fix hwid for nbioXiaojie Yuan
Properly set this. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZEXiaojie Yuan
register base offset of nbio is not known before IP Discovery table is parsed, so hardcode this value. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add harvest info data tableXiaojie Yuan
Add support for the harvest tables. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: update definitions of table_info and binary_headerXiaojie Yuan
Use the proper definitions. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: fix calculations of some gfx infoXiaojie Yuan
fix gfx info table handling. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add ip discovery initial supportXiaojie Yuan
The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: mark the partial job as preempted in mcbp unit testJack Xiao
In mcbp unit test, the test should detect the preempted job which may be a partial execution ib and mark it as preempted; so that the gfx block can correctly generate PM4 frame. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add mcbp unit test in debugfs (v3)Jack Xiao
The MCBP unit test is used to test the functionality of MCBP. It emualtes to send preemption request and resubmit the unfinished jobs. v2: squash in fixes (Alex) v3: squash in memory leak fix (Jack) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: program for resuming preempted ibJack Xiao
For new submission ib, CE/DE metadata should be programmed to 0; for partially execution ib, CE/DE metadata should be restored. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma: allocate CSA per sdma ringJack Xiao
Allocate CSA for the given sdma ring. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add ib preemption status in amdgpu_job (v2)Jack Xiao
Add ib preemption status in amdgpu_job, so that ring level function can detect preemption and program for resuming it. v2: squash in fix to restore job->preamble_status back to status value (Jack) Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable the static csa when mcbp enabledJack Xiao
CSA is the Context Save Area for preemption. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add mcbp driver parameterJack Xiao
Add mcbp driver parameter, so that mcbp feature can be enabled/disabled by driver parameter. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: Add new ring interface preempt_ibRex Zhu
Used to trigger preemtption Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add the trailing fence per ringJack Xiao
The trailing fence for ring is used to track the completion of preemption. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_execRex Zhu
can preempt the ring by setting cond_exec to false Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable virtual display feature for navi10Le.Ma
Virtual display is a pure sw implementation of KMS for use in virtualization and for bring up and emulation. Signed-off-by: Le.Ma <Le.Ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/komeda: Make Komeda interrupts shareableAyan Halder
Komeda interrupts may be shared with other hardware blocks. One needs to use devm_request_irq() with IRQF_SHARED to create a shared interrupt handler. As a result of not using drm_irq_install() api, one needs to set "(struct drm_device *)->irq_enabled = true/false" to enable/disable vblank interrupts. Changes from v1:- 1. Squashed the following two patches into one (as the second patch is a consequence of the first one):- drm/komeda: Avoid using DRIVER_IRQ_SHARED drm/komeda: Enable/Disable vblank interrupts 2. Fixed the commit message (as pointed by Daniel Vetter) 3. Removed calls to 'drm_irq_uninstall()' as we are no longer using drm_irq_install() 4. Removed the struct member 'komeda_kms_driver.irq_handler' as it is not used anywhere. Signed-off-by: Ayan Halder <ayan.halder@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2019-06-21drm/komeda: fix 32-bit komeda_crtc_update_clock_ratioArnd Bergmann
clang points out a bug in the clock calculation on 32-bit, that leads to the clock_ratio always being zero: drivers/gpu/drm/arm/display/komeda/komeda_crtc.c:31:36: error: shift count >= width of type [-Werror,-Wshift-count-overflow] aclk = komeda_calc_aclk(kcrtc_st) << 32; Move the shift into the division to make it apply on a 64-bit variable. Also use the more expensive div64_u64() instead of div_u64() to account for pxlclk being a 64-bit integer. Fixes: 1f7f9ab7900e ("drm/komeda: Add engine clock requirement check for the downscaling") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2019-06-21Merge tag 'drm-intel-next-2019-06-19' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next Features: - HDR support (Uma, Ville) - Add I2C symlink under HDMI connector similar to DP (Oleg) - Add ICL multi-segmented gamma support (Shashank, Uma) - Update register whitelist support for new hardware (Robert, John) - GuC firmware update with updated ABI interface (Michal, Oscar) - Add support for new DMC header versions (Lucas) - In-kernel blitter client for selftest use (Matthew) - Add Mule Creec Canyon (MCC) PCH support to go with EHL (Matt) - EHL platform feature updates (Matt) - Use Command Transport Buffers with GuC on all gens (Daniele) - New i915.force_probe module parameter to replace i915.alpha_support (Jani) Refactoring: - Better runtime PM code abstraction/encapsulation (Daniele) - VBT parsing cleanup and improvements (Jani) - Move display code to its own subdirectory (Jani) - Header cleanup (Jani, Daniele) - Prep work for subsclice mask expansion (Stuart) - Use uncore mmio register accessors more, remove unused macro wrappers (Tvrtko) - Remove unused atomic property get/set stubs (Maarten) - GTT cleanups and improvements (Mika) - Pass intel_ types instead of drm_ types in plenty of display code (Ville) - Engine reset, hangcheck, fault code cleanups and improvements (Tvrtko) - Consider AML variants simply as either KBL or CFL ULX (Ville) - State checker cleanups and improvements (Ville) - GEM code reorganization to more files under gem subdirectory (Chris) - Reducing dependency on a coarse struct_mutex (Chris) Fixes: - Fix use of uninitialized/incorrect error pointers (Colin, Dan) - Fix DSI fastboot on some VLV/CHV platforms (Hans) - Fix DSI error path (Hans) - Add ICL port A combo PHY HW state check (Imre) - Fix ICL AUX-B HW not done issue (Imre) - Fix perf whitelist on gen10+ (Lionel) - Fix PSR exit by forcing manual exit on older gens (José) - Match voltage ranges instead of exact values (Lucas) - Fix SDVO HDMI audio, with cleanups (Ville) - Fix plane state dumps (Ville) - Fix driver cleanup code to support driver hot unbind (Janusz) - Add checks for ICL memory bandwidth requirements (Ville) - Fix toggling between no C8 planes vs. at least one C8 plane (Ville) - Improved checks on PLL usage conditions, refactoring (Ville) - Avoid clobbering M/N values in fastset fuzzy checks (Ville) - Take a runtime pm wakeref for atomic commits (Chris) - Do not allow runtime pm autosuspend to remove userspace GGTT mmaps too quickly (Chris) - Avoid refcount_inc on known zero count to avoid debug flagging (Chris) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87v9x1lpdh.fsf@intel.com
2019-06-21Merge tag 'drm-misc-next-2019-06-20' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.3: UAPI Changes: - Give each dma-buf their own inode, add DMA_BUF_SET_NAME ioctl and a show_fdinfo handler. Cross-subsystem Changes: - Pull in the topic/remove-fbcon-notifiers branch: * remove fbdev notifier usage for fbcon, as prep work to clean up the fbcon locking * assorted locking checks in vt/console code * assorted notifier and cleanups in fbdev and backlight code Core Changes: - Make drm_debugfs_create_files() never fail. - add debug print to update_vblank_count. - Add DP_DPCD_QUIRK_NO_SINK_COUNT quirk. - Add todo item for drm_gem_objects. - Unexport drm_gem_(un)pin/v(un)map. - Document struct drm_cmdline_mode. - Rewrite the command handler for mode names, and add support to specify rotation, reflection and overscan. With a new selftest! :) - Fixes to drm/client for improving rotation support, and fixing variable scope. - Small fixes to self refresh helper. Driver Changes: - Add rockchip RK3328 support. - Assorted driver fixes to rockchip, vc4, rcar-du, vkms. - Expose panfrost performance counters through unstable ioctl's, hidden behind a module parameter. - Enumerate CRC sources list in vkms. - Add a basic kms driver for the Ingenic JZ47xx SoC, which will be expanded soon with more advanced features. - Suspend/resume fix for stm. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/18e22ec1-adf3-3a75-34a3-9fe09a91eef5@linux.intel.com
2019-06-20drm/amdgpu/psp11: skip ta firmware for navi10Hawking Zhang
Not used on Navi10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: declare navi10 asd firmwareHawking Zhang
So the dependencies are properly handled. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-13 07:20:15 +0000