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The first leak occurs when entering the default case
in the switch for the initiator in set_regdom.
The second leaks a platform_device struct if the
platform registration in regulatory_init succeeds but
the sub sequent regulatory hint fails due to no memory.
Signed-off-by: Ola Olsson <ola.olsson@sonymobile.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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__user_swpX_asm maybe failed in first STREX operation, emulate_swpX
will try again, but the *data has been changed in first time. which
causes the result is wrong.
This patch is to fix this issue. When STREX succeed, change the *data.
if it fail, *data is not changed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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In cpu_v7_do_suspend routine, r11 is used while it is NOT
saved/restored, different compiler may have different usage
of ARM general registers, so it may cause issues during
calling cpu_v7_do_suspend.
We meet kernel fault occurs when using GCC 4.8.3, r11 contains
valid value before calling into cpu_v7_do_suspend, but when returned
from this routine, r11 is corrupted and lead to kernel fault.
Doing save/restore for those corrupted registers is a must in
assemble code.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Cc: <stable@vger.kernel.org> # v3.3+
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The uaccess_with_memcpy() code is currently incompatible with the SW
PAN code: it takes locks within the region that we've changed the DACR,
potentially sleeping as a result. As we do not save and restore the
DACR across co-operative sleep events, can lead to an incorrect DACR
value later in this code path.
Reported-by: Peter Rosin <peda@axentia.se>
Tested-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Merge in EFI memblock changes from Ard, which form the preparatory work
for UEFI support on 32-bit ARM.
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The current code to initialize, register and read the clocksource is
already factored out in mmio.c via the clocksource_mmio_init function.
Factor out the code with the clocksource_mmio_init function.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Add the COMPILE_TEST option so the drivers can be compiled on different
architecture with the 'allyesconfig' kernel configuration.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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For the sake of consistency, let rename all ctrl_out/in calls to the write/read
calls so we have the same API consistent with the other architectures hence
open the door for the increasing of the test compilation coverage.
The unsigned long coercive cast is removed because all variables are set to
the right type "void __iomem *".
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Gateworks Ventana boards seem to need "RGMII-ID" (internal delay)
PHY mode, instead of simple "RGMII", for their Marvell 88E1510
transceiver. Otherwise, the Ethernet MAC doesn't work with Marvell PHY
driver (TX doesn't seem to work correctly).
Tested on GW5400 rev. C.
This bug affects ARM Fedora 23.
Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The 'assigned-clock-parents' and 'assigned-clock-rates' list
should corresponding to the 'assigned-clocks' property clock list.
Signed-off-by: Bai Ping <b51503@freescale.com>
Fixes: ed339363de1b ("ARM: dts: imx6qdl-sabreauto: Allow HDMI and LVDS to work simultaneously")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The current Kconfig option is the H8300 arch option. In order to comply to the
current rule, let's create a specific option for the timer8 and select it
from the arch's Kconfig.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The current code to initialize, register and read the clocksource is
already factored out in mmio.c via the clocksource_mmio_init function.
The only difference is the readl vs readl_relaxed.
Factor out the code with the clocksource_mmio_init function.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The lock in the timer16_clocksource_read is not needed, remove it.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The function irq_of_parse_and_map returns zero in case of failure.
Fix the return code test to check against zero.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The fields are not used in the code, remove them.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The macros are no longer used in the code, remove them.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The headers are not needed, remove them.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The current code retrieves the rate value when the timer is enabled which
occurs each time a timer is re-armed. Except if the clock frequency has changed
magically I don't see why this should be done each time.
Retrieve the clock rate value at init time only.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The time framawork takes care of disabling the interrupts and takes a lock
to prevent races.
Remove the legacy code in the driver taking care of the races.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The current code assumes the interrupt function is re-entrant.
That is not correct. An interrupt handler is never invoked concurrently. The
interrupt line is masked on all processors.
Remove the chewing flags in the code.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The value returned in case of error for the 'irq_of_parse_and_map' function is
zero in case of error. Fix the check in the init code.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Specify the delta as parameter for the timer8_clock_event_start function
instead of using a macro to tell PERIODIC or ONESHOT.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Some macros are unused, delete them.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The dev_warn is using the platform driver which was removed in the previous
patch.
Let's replace dev_warn by pr_warn.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Remove some legacy code and replace it by the clksrc-of code.
Do some cleanup and code consolidation.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Implement an ARM delay timer to be used for udelay(). This allows us to
skip the delay loop calibration at boot on Marvell BG2, BG2Q, BG2CD
platforms. And after this patch, udelay() will be unaffected by CPU
frequency changes.
Note: Although in case there are several possible delay timers, we may
not select the "best" delay timer. Take one Marvell Berlin platform for
example: we have arch timer and dw-apb timer. The arch timer freq is
25MHZ while the dw-apb timer freq is 100MHZ, current selection would
choose the dw-apb timer. But the dw apb timer is on the APB bus while
arch timer sits in CPU, the cost of accessing the apb timer is higher
than the arch timer. We could introduce "rating" concept to delay
timer, but this approach "brings a lot of complexity and workarounds
in the code for a small benefit" as pointed out by Daniel.
Later, Arnd pointed out "However, we could argue that this actually
doesn't matter at all, because the entire point of the ndelay()/
udelay()/mdelay() functions is to waste CPU cycles doing not much at
all, so we can just as well waste them reading the timer register
than spinning on the CPU reading the arch timer more often.", so we
just simply register the dw apb base delay timer.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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In order to compile on all arch without error with 'allyesconfig' make
sure the platform selected the GENERIC_CLOCKEVENTS. Without this patch
the new added drivers will prevent the kernel to compile on PARISC.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Let the platform's Kconfig to select the clock instead of having a reverse
dependency from the driver to the platform options.
Add the COMPILE_TEST option for the compilation test coverage. Due to the
non portable 'delay' code, this driver is only compilable on ARM.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
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Let the platform's Kconfig to select the clock instead of having a reverse
dependency from the driver to the platform options.
Add the COMPILE_TEST option for the compilation test coverage.
This change is debatable as the option itself in the Kconfig allows to
select the driver for the platform or not. This change will make the prcmu
timer always selected.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Due to the non portable code for the delay timer, this option is only
available for the ARM architecture.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
The driver depends on the common clock framework, thus the dependency added
on COMMON_CLK.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Remove the <asm/time.h> header inclusion which is pointless.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Due to the non portable code for the delay timer, this option is only
available for the ARM architecture.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
The driver depends on the common clock framework, thus the dependency added
on COMMON_CLK.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
The driver is using the atomic_io API which is not portable, so the
compilation is restricted to ARM only.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Due to the non portable 'delay' code, the compilation is restricted to the
ARM architecture only.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Due to the dsb() usage in the driver, this driver is only compilable on
ARM and ARM64.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Increase the compilation test coverage by adding the COMPILE_TEST option.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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