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2023-12-13drm/amd/pm: add flood detection for wbrf eventsEvan Quan
To protect PMFW from being overloaded. Signed-off-by: Evan Quan <quanliangl@hotmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/pm: setup the framework to support Wifi RFI mitigation featureEvan Quan
With WBRF feature supported, as a driver responding to the frequencies, amdgpu driver is able to do shadow pstate switching to mitigate possible interference(between its (G-)DDR memory clocks and local radio module frequency bands used by Wifi 6/6e/7). -- v1->v2: - update the prompt for feature support(Lijo) v8->v9: - update parameter document for smu_wbrf_event_handler(Simon) v9->v10: v10->v11: - correct the logics for wbrf range sorting(Lijo) v13: - Fix the format issue (IIpo Jarvinen) Signed-off-by: Evan Quan <quanliangl@hotmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/pm: update driver_if and ppsmc headers for coming wbrf featureEvan Quan
Add those data structures to support Wifi RFI mitigation feature. Signed-off-by: Evan Quan <quanliangl@hotmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13Merge tag 'platform-drivers-x86-amd-wbrf-v6.8-1' into amd-drm-nextAlex Deucher
Immutable branch between pdx86 amd wbrf branch and wifi / amdgpu due for the v6.8 merge window platform-drivers-x86-amd-wbrf-v6.8-1: v6.7-rc1 + AMD WBRF support for merging into the wifi subsys and amdgpu driver for 6.8. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdkfd: Import DMABufs for interop through DRMFelix Kuehling
Use drm_gem_prime_fd_to_handle to import DMABufs for interop. This ensures that a GEM handle is created on import and that obj->dma_buf will be set and remain set as long as the object is imported into KFD. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by: Xiaogang.Chen <Xiaogang.Chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdkfd: Export DMABufs from KFD using GEM handlesFelix Kuehling
Create GEM handles for exporting DMABufs using GEM-Prime APIs. The GEM handles are created in a drm_client_dev context to avoid exposing them in user mode contexts through a DMABuf import. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdgpu: xgmi_fill_topology_infoVignesh Chander
1. Use the mirrored topology info to fill links for VF. The new solution is required to simplify and optimize host driver logic. Only use the new solution for VFs that support full duplex and extended_peer_link_info otherwise the info would be incomplete. 2. avoid calling extended_link_info on VF as its not supported Signed-off-by: Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Reviewed-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Fix memory leak in dm_set_writeback()Harshit Mogalapalli
'wb_info' needs to be freed on error paths or it would leak the memory. Smatch pointed this out. Fixes: c81e13b929df ("drm/amd/display: Hande writeback request from userspace") Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add plane HDR multiplier driver-specific propertyJoshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80 nits for SDR content. So if you want, 203 nits for SDR content, pass in (203.0 / 80.0). v4: - comment about the PQ TF need for L-to-NL (from Harry's review) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: document AMDGPU pre-defined transfer functionsMelissa Wen
Brief documentation about pre-defined transfer function usage on AMD display driver and standardized EOTFs and inverse EOTFs. v3: - Document BT709 OETF (Pekka) - Fix description of sRGB and pure power funcs (Pekka) v4: - Add description of linear and non-linear forms (Harry) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Co-developed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: explicitly define EOTF and inverse EOTFMelissa Wen
Instead of relying on color block names to get the transfer function intention regarding encoding pixel's luminance, define supported Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that includes pure gamma or standardized transfer functions. v3: - squash linear and unity TFs to identity (Pekka) - define the right TFs for BT.709 (Pekka and Harry) - add comment about AMD TF coefficients Suggested-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add plane degamma TF driver-specific propertyJoshua Ashton
Allow userspace to tell the kernel driver the input space and, therefore, uses correct predefined transfer function (TF) to go from encoded values to linear values. v2: - rename TF enum prefix from DRM_ to AMDGPU_ (Harry) - remove HLG TF Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Disable PSR-SU on Parade 0803 TCON againMario Limonciello
When screen brightness is rapidly changed and PSR-SU is enabled the display hangs on panels with this TCON even on the latest DCN 3.1.4 microcode (0x8002a81 at this time). This was disabled previously as commit 072030b17830 ("drm/amd: Disable PSR-SU on Parade 0803 TCON") but reverted as commit 1e66a17ce546 ("Revert "drm/amd: Disable PSR-SU on Parade 0803 TCON"") in favor of testing for a new enough microcode (commit cd2e31a9ab93 ("drm/amd/display: Set minimum requirement for using PSR-SU on Phoenix")). As hangs are still happening specifically with this TCON, disable PSR-SU again for it until it can be root caused. Cc: stable@vger.kernel.org Cc: aaron.ma@canonical.com Cc: binli@gnome.org Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2046131 Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: 3.2.264Aric Cyr
Summary: Bug fixes for: * DCN35 power gating * P-state change, & prefetch logic * ABM * DP 2.1 Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: fix HW block PG sequenceCharlene Liu
[why] Power up and power down has reverted programming order. also make sure disable root clock last. Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Force p-state disallow if leaving no plane configAlvin Lee
[Description] - When we're in a no plane config, DCN is always asserting P-State allow - This creates a scenario where the P-State blackout can start just as VUPDATE takes place and transitions the DCN config to a one where one or more HUBP's are active which can result in underflow - To fix this issue, force p-state disallow and unforce after the transition from no planes case -> one or more planes active Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: For prefetch mode > 0, extend prefetch if possibleAlvin Lee
[Description] For mode programming we want to extend the prefetch as much as possible (up to oto, or as long as we can for equ) if we're not already applying the 60us prefetch requirement. This is to avoid intermittent underflow issues during prefetch. The prefetch extension is applied under the following scenarios: 1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank) 2. We're using subvp or drr methods of p-state switch, in which case we we don't care if prefetch takes up more of the blanking time Mode programming typically chooses the smallest prefetch time possible (i.e. highest bandwidth during prefetch) presumably to create margin between p-states / c-states that happen in vblank and prefetch. Therefore we only apply this prefetch extension when p-state in vblank is not required (UCLK p-states take up the most vblank time). Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Exit from idle state before accessing HW dataSung Joon Kim
[why & how] User interface cannot guarantee system is in idle state, so need to ensure we exit idle state before accessing any HW data. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Disable OPTC pg to match DC Hubp/dpp pgAllen
[Why] To match the hardware sequence Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Allen <allen.pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Populate dtbclk from bounding boxFangzhi Zuo
dtbclk is unavaliable from pmfw. Try to grab the value from bounding box Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Revert DP2 MST hub triple display fixMichael Strauss
[WHY] Introduces regression with DP2 native displays [HOW] Revert the change Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: trivial comment changeAurabindo Pillai
FP guard is valid for all recent asics, not just RV, so fix the comment. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Revert "Fix conversions between bytes and KB"Taimur Hassan
[Why & How] HostVMMinPageSize is expected to be in KB according to spec, the checks later down the line reflect this as well. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: allow DP40 cables to do UHBR13.5Ran Shi
why: With DP2.1a expansion we are allowing DP40 cables to do UHBR13.5 how: Assume UHBR10 means UHBR13.5 also for unknown cable type and passive cable type. Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Ran Shi <ran.shi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Use explicit size for types in DCCG's struct dp_dto_paramsAurabindo Pillai
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Remove minor revision 5 until proper parser is readyJoshua Aberback
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/pm: Remove redundant function members of pptable_funcsMa Jun
Remove redundant functions members of pptable_funcs and change the function type as static because they are not called by other files. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdgpu/jpeg: configure doorbell for each playbackSaleemkhan Jamadar
Doorbell is configured during start of each playback. v1 - add comment for the doorbell programming change Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdgpu: Use the right method to get IP versionLijo Lazar
Replace direct usage of adev->ip_versions with amdgpu_ip_version. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add driver-specific property for plane degamma LUTMelissa Wen
Hook up driver-specific atomic operations for managing AMD color properties. Create AMD driver-specific color management properties and attach them according to HW capabilities defined by `struct dc_color_caps`. First add plane degamma LUT properties that means user-blob and its size. We will add more plane color properties in the next patches. In addition, we define AMD_PRIVATE_COLOR to guard these driver-specific plane properties. Plane degamma can be used to linearize input space for arithmetical operations that are more accurate when applied in linear color. v2: - update degamma LUT prop description - move private color operations from amdgpu_display to amdgpu_dm_color v5: - get degamma blob correctly (Joshua) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Co-developed-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/drm_plane: track color mgmt changes per planeMelissa Wen
We will add color mgmt properties to DRM planes in the next patches and we want to track when one of this properties change to define atomic commit behaviors. Using a similar approach from CRTC color props, we set a color_mgmt_changed boolean whenever a plane color prop changes. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/drm_property: make replace_property_blob_from_id a DRM helperMelissa Wen
Place it in drm_property where drm_property_replace_blob and drm_property_lookup_blob live. Then we can use the DRM helper for driver-specific KMS properties too. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/drm_mode_object: increase max objects to accommodate new color propsMelissa Wen
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached and we are increasing that value all time we add a new property (generic or driver-specific). In this series, we are adding 13 new KMS driver-specific properties for AMD color manage: - CRTC Gamma enumerated Transfer Function - Plane: Degamma LUT+size+TF, HDR multiplier, shaper LUT+size+TF, 3D LUT+size, blend LUT+size+TF (12) Therefore, just increase DRM_OBJECT_MAX_PROPERTY to a number (64) that accomodates these new properties and gives some room for others, avoiding change this number everytime we add a new KMS property. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Simon Ser <contact@emersion.fr> Signed-off-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: Fix spelling mistake "SMC_MSG_AllowZstatesEntr" -> ↵Colin Ian King
"SMC_MSG_AllowZstatesEntry" There is a spelling mistake in a smu_print message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdgpu: fix buffer funcs setting order on suspend harderAlex Deucher
Part of commit c03581986234 ("drm/amdgpu: fix buffer funcs setting order on suspend") got dropped accidently. Add it back. Fixes: c03581986234 ("drm/amdgpu: fix buffer funcs setting order on suspend") Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/i915: Simplify intel_ddi_compute_min_voltage_level()Ville Syrjälä
Drop the redundant dev_priv parameters from intel_ddi_compute_min_voltage_level() to make life easier. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-9-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/mtl: Calculate the correct voltage level from port_clockVille Syrjälä
On MTL we need to bump the voltage level to only 1 (not 2) when port clock exceeds 594MHz. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-8-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915: Split intel_ddi_compute_min_voltage_level() into platform variantsVille Syrjälä
The mess inside intel_ddi_compute_min_voltage_level() is illegible. Clean it up a bit by splitting the internals into per-platform functions. TODO: make it a vfunc? Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-7-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/mtl: Fix voltage_level for cdclk==480MHzVille Syrjälä
Allow MTL to use voltage level 1 for 480MHz cdclk, instead of the voltage level 2 that it's currently using. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-6-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tablesVille Syrjälä
The cdclk->voltage_level if ladders are hard to read, especially as they're written the other way around compared to how bspec lists the limits. Let's rewrite them to use simple arrays that gives us the max cdclk for each voltage level. v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to accommodate JSL machines in CI that boot with high cdclk Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211221759.29725-1-ville.syrjala@linux.intel.com
2023-12-13drm/i915/cdclk: Remove the assumption that cdclk divider==2 when using squashingVille Syrjälä
Currently we have a hardcoded assumption that the cdclk divider (2*cd2x divider) is always 2 when squashing is used. While that is true for all current platforms it might not hold in the future. So eliminate the assumption and calculate the correct divider from the other parameters. v2: s/cd2x divider/cdclk divider/ (Gustavo) s/clock/unsquashed_cdclk/ (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211221636.29658-1-ville.syrjala@linux.intel.com
2023-12-13drm/i915/cdclk: Give the squash waveform length a nameVille Syrjälä
Replace the slightly magic 'size = 16' with a bit more descriptive name. We'll have another user for this value later on. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-3-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915/cdclk: s/-1/~0/ when dealing with unsigned valuesVille Syrjälä
cdclk_pll_is_unknown() used ~0 when checking for the "VCO is unknown" value, but the assignment uses -1. They are the same in the end, but let's use the same ~0 form on both sides for consistency. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-2-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
2023-12-13drm/i915: Reject async flips with bigjoinerVille Syrjälä
Currently async flips are busted when bigjoiner is in use. As a short term fix simply reject async flips in that case. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9769 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231211081134.2698-1-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
2023-12-13drm: ci: Update xfailsVignesh Raman
Update msm-apq8016-fails, mediatek-mt8173-fails and virtio_gpu-none-fails to include the tests which fail. Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-11-vignesh.raman@collabora.com
2023-12-13drm/doc: ci: Add IGT version details for flaky testsVignesh Raman
Document the IGT version in the flaky tests reporting template. Acked-by: Helen Koike <helen.koike@collabora.com> Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-10-vignesh.raman@collabora.com
2023-12-13drm: ci: uprev IGTVignesh Raman
virtio-gpu kernel driver reports 16 for count_crtcs which exceeds IGT_MAX_PIPES set to 8 in igt-gpu-tools. This results in below memory corruption,  malloc(): corrupted top size  Received signal SIGABRT.  Stack trace:   #0 [fatal_sig_handler+0x17b]   #1 [__sigaction+0x40]   #2 [pthread_key_delete+0x14c]   #3 [gsignal+0x12]   #4 [abort+0xd3]   #5 [__fsetlocking+0x290]   #6 [timer_settime+0x37a]   #7 [__default_morecore+0x1f1b]   #8 [__libc_calloc+0x161]   #9 [drmModeGetPlaneResources+0x44]   #10 [igt_display_require+0x194]   #11 [__igt_unique____real_main1356+0x93c]   #12 [main+0x3f]   #13 [__libc_init_first+0x8a]   #14 [__libc_start_main+0x85]   #15 [_start+0x21]   This is fixed in igt-gpu-tools by increasing IGT_MAX_PIPES to 16.   https://patchwork.freedesktop.org/series/126327/   Uprev IGT to include the patches which fixes this issue. Acked-by: Helen Koike <helen.koike@collabora.com> Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-9-vignesh.raman@collabora.com
2023-12-13drm: ci: virtio: Make artifacts availableVignesh Raman
There were no artifacts available for virtio job. So make the artifacts available in the pipeline job. Acked-by: Helen Koike <helen.koike@collabora.com> Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-8-vignesh.raman@collabora.com
2023-12-13drm: ci: mt8173: Do not set IGT_FORCE_DRIVER to panfrostVignesh Raman
Mediatek 8173 and 8183 SOCs have a separate display controller and GPU with different drivers for each. For mt8173, the GPU driver is powervr and the display driver is mediatek. In the case of mt8183, the GPU driver is panfrost and the display driver is mediatek. Setting IGT_FORCE_DRIVER to panfrost for mt8173 is not the expected driver. So set mediatek for mt8173. Support to test both GPU and display drivers for these ARM SOCs will be added in the next patch series to increase test coverage. Acked-by: Helen Koike <helen.koike@collabora.com> Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-7-vignesh.raman@collabora.com
2023-12-13drm: ci: Use scripts/config to enable/disable configsVignesh Raman
Instead of modifying files in git to enable/disable configs, use scripts/config on the .config file which will be used for building the kernel. Acked-by: Helen Koike <helen.koike@collabora.com> Suggested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207091831.660054-6-vignesh.raman@collabora.com
generated by cgit (git 2.34.1) at 2025-09-17 03:27:14 +0000