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2014-08-05drm/i915: Update DRIVER_DATE to 20140725Daniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-05kbuild, LLVMLinux: Supress warnings unless W=1-3Behan Webster
clang has more warnings enabled by default. Turn them off unless W is set. This patch fixes a logic bug where warnings in clang were disabled when W was set. Signed-off-by: Behan Webster <behanw@converseincode.com> Signed-off-by: Jan-Simon Möller <dl9pf@gmx.de> Signed-off-by: Mark Charlebois <charlebm@gmail.com> Cc: bp@alien8.de Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-08-05KVM: nVMX: fix "acknowledge interrupt on exit" when APICv is in useWanpeng Li
After commit 77b0f5d (KVM: nVMX: Ack and write vector info to intr_info if L1 asks us to), "Acknowledge interrupt on exit" behavior can be emulated. To do so, KVM will ask the APIC for the interrupt vector if during a nested vmexit if VM_EXIT_ACK_INTR_ON_EXIT is set. With APICv, kvm_get_apic_interrupt would return -1 and give the following WARNING: Call Trace: [<ffffffff81493563>] dump_stack+0x49/0x5e [<ffffffff8103f0eb>] warn_slowpath_common+0x7c/0x96 [<ffffffffa059709a>] ? nested_vmx_vmexit+0xa4/0x233 [kvm_intel] [<ffffffff8103f11a>] warn_slowpath_null+0x15/0x17 [<ffffffffa059709a>] nested_vmx_vmexit+0xa4/0x233 [kvm_intel] [<ffffffffa0594295>] ? nested_vmx_exit_handled+0x6a/0x39e [kvm_intel] [<ffffffffa0537931>] ? kvm_apic_has_interrupt+0x80/0xd5 [kvm] [<ffffffffa05972ec>] vmx_check_nested_events+0xc3/0xd3 [kvm_intel] [<ffffffffa051ebe9>] inject_pending_event+0xd0/0x16e [kvm] [<ffffffffa051efa0>] vcpu_enter_guest+0x319/0x704 [kvm] To fix this, we cannot rely on the processor's virtual interrupt delivery, because "acknowledge interrupt on exit" must only update the virtual ISR/PPR/IRR registers (and SVI, which is just a cache of the virtual ISR) but it should not deliver the interrupt through the IDT. Thus, KVM has to deliver the interrupt "by hand", similar to the treatment of EOI in commit fc57ac2c9ca8 (KVM: lapic: sync highest ISR to hardware apic on EOI, 2014-05-14). The patch modifies kvm_cpu_get_interrupt to always acknowledge an interrupt; there are only two callers, and the other is not affected because it is never reached with kvm_apic_vid_enabled() == true. Then it modifies apic_set_isr and apic_clear_irr to update SVI and RVI in addition to the registers. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Suggested-by: "Zhang, Yang Z" <yang.z.zhang@intel.com> Tested-by: Liu, RongrongX <rongrongx.liu@intel.com> Tested-by: Felipe Reyes <freyes@suse.com> Fixes: 77b0f5d67ff2781f36831cba79674c3e97bd7acf Cc: stable@vger.kernel.org Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-05drm/radeon: Use pflip irqs for pageflip completion if possible. (v2)Mario Kleiner
Skip the "manual" pageflip completion checks via polling and guessing in the vblank handler radeon_crtc_handle_vblank() on asics which are known to reliably support hw pageflip completion irqs. Those pflip irqs are a more reliable and race-free method of handling pageflip completion detection, whereas the "classic" polling method has some small races in combination with dpm on, and with the reworked pageflip implementation since Linux 3.16. On old asics without pflip irqs, the classic method is used. On asics with known good pflip irqs, only pflip irqs are used by default, but a new module parameter "use_pflipirqs" allows to override this in case we encounter asics in the wild with unreliable or faulty pflip irqs. A module parameter of 0 allows to use the classic method only in such a case. A parameter of 1 allows to use both classic method and pflip irqs as additional band-aid to avoid some small races which could happen with the classic method alone. The setting 1 gives Linux 3.16 behaviour. Hw pflip irqs are available since R600. Tested on DCE-4, AMD Cedar - FirePro 2270. v2: agd5f: only enable pflip interrupts on DCE4+ as they are not reliable on older asics. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: tweak ACCEL_WORKING2 query for the new firmware for hawaiiAndreas Boll
Adjust the previous tweak for hawaii to return 3 if the new firmware is used. Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: use packet3 for nop on hawaii with new firmwareAlex Deucher
Older firmware didn't support the new nop packet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
2014-08-05drm/radeon: tweak ACCEL_WORKING2 query for hawaiiAlex Deucher
Return 2 so we can be sure the kernel has the necessary changes for acceleration to work. Note: This patch depends on these two commits: - drm/radeon: fix cut and paste issue for hawaii. - drm/radeon: use packet2 for nop on hawaii with old firmware Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon: use packet2 for nop on hawaii with old firmwareAlex Deucher
Older firmware didn't support the new nop packet. v2 (Andreas Boll): - Drop usage of packet3 for new firmware Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon: update IB size estimation for VMChristian König
That should allow us to allocate bigger BOs. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: split PT setup in more functionsChristian König
Move the decision what to use into the common VM code. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: add VM GART copy optimization to NI as wellChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: take a BO reference on VM cleanupChristian König
This closes a small window where the GPU might have accessed freed up memory. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: add radeon_bo_ref functionChristian König
To be consistent with radeon_bo_unref, needed in the following patch. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: remove taking mclk_lock from radeon_bo_unrefChristian König
It's causing lockdep warnings and why should we access the memory that is freed up? Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: adjust default radeon_vm_block_size v2Christian König
v2: rebase on vm_size scale change. Adjust vm_size default to 8, Better handle the default and smaller values. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: try to enable VM flushing once moreChristian König
Let's try to fix bugs related to this instead of just disabling it. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: use an intervall tree to manage the VMA v2Alex Deucher
Scales much better than scanning the address range linearly. v2: store pfn instead of address Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: remove radeon_bo_clear_vaChristian König
Won't work anyway, instead WARN_ON if the VA list isn't empty when we free the BO. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: invalidate moved BOs in the VM (v2)Christian König
Don't wait for the BO to be used again, just update the PT on the next VM use. v2: remove stray semicolon. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: re-enable dpm by default on BTCAlex Deucher
This patch depends on: e07929810f0a19ddd756558290c7d72827cbfcd9 (drm/radeon/dpm: fix typo in vddci setup for eg/btc) bugs: https://bugs.freedesktop.org/show_bug.cgi?id=73053 https://bugzilla.kernel.org/show_bug.cgi?id=68571 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon: re-enable dpm by default on caymanAlex Deucher
This patch depends on: b0880e87c1fd038b84498944f52e52c3e86ebe59 (drm/radeon/dpm: fix vddci setup typo on cayman) bug: https://bugs.freedesktop.org/show_bug.cgi?id=69723 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon: Only flush HDP cache from idle ioctl if BO is in VRAMMichel Dänzer
The HDP cache only applies to CPU access to VRAM. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon/dpm: handle voltage info fetching on hawaiiAlex Deucher
Some hawaii cards use a different method to fetch the voltage info from the vbios. bug: https://bugs.freedesktop.org/show_bug.cgi?id=74250 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon/atom: add new voltage fetch function for hawaiiAlex Deucher
Some hawaii boards use a different method for fetching the voltage information from the vbios. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon: Always flush the HDP cache before submitting a CS to the GPUMichel Dänzer
This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: s/ioctl_wait_idle/mmio_hpd_flush/Michel Dänzer
And clean up the function comment a little. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: separate ring and IB handlingChristian König
Both on their own are complex enough. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: fix reversed logic in evergreen_mc_resumeAlex Deucher
Need to unblank the display when resuming the MC. No functional change as this code path is not currently hit. We always disable the displays entirely rather than just blanking them. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: set VM base addr using the PFP v2Christian König
Seems to make VM flushes more stable on SI and CIK. v2: only use the PFP on the GFX ring on CIK Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon/cik: Read back SDMA WPTR register after writing itMichel Dänzer
For symmetry with other *_set_wptr hooks. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Use write-combined CPU mappings of IBs on >= CIKMichel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Use write-combined CPU mappings of ring buffers with PCIeMichel Dänzer
PCI GART doesn't support unsnooped access. AGP GART already uses write-combined CPU mappings. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: load the lm63 driver for an lm64 thermal chip.Alex Deucher
Looks like the lm63 driver supports the lm64 as well. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2014-08-05drm/radeon: make radeon_connector_encoder_is_hbr2 staticAlex Deucher
It's only used in radeon_connectors.c. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: add trace_radeon_vm_flushChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: fix R600_PTE_GART handlingChristian König
That didn't worked correctly any more and opened up a security problem. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: remove discardable flag from radeon_gem_object_createChristian König
Unused and unimplemented. Also fix specifying the kernel flag incorrectly at one occasion. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: add a PX quirk listAlex Deucher
Some PX laptops seems to have problems turning the dGPU on/off. Add a quirk list to disable runpm by default on those systems. Also convert the current PX d3 delay handling to a quirk. bug: https://bugzilla.kernel.org/show_bug.cgi?id=51381 https://bugzilla.kernel.org/show_bug.cgi?id=74551 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: remove visible vram size limit on bo allocation (v4)Alex Deucher
Now that fallback to gtt is fixed for cpu access, we can remove this limit. bug: https://bugs.freedesktop.org/show_bug.cgi?id=78717 v2: use new gart_pin_size to accurately track available gtt. v3: fix comment v4: clarify comment Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-05drm/radeon: use vram/gart pinned size in radeon_do_test_movesAlex Deucher
Gives more accurate count and prevents failures when we can't allocate memory for the tests. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-05drm/radeon: use vram/gart pinned size in radeon_gem_info_ioctlAlex Deucher
Gives a more accurate limit than the previous code. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-05drm/radeon: track pinned memory (v2)Alex Deucher
So we know how large an allocation we can allow. v2: incorporate Michel's comments Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-05drm/radeon: Allow write-combined CPU mappings of BOs in GTT (v2)Michel Dänzer
v2: fix rebase onto drm-fixes Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Pass GART page flags to radeon_gart_set_page() explicitlyMichel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Remove radeon_gart_restore()Michel Dänzer
Doesn't seem necessary, the GART table memory should be persistent. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Demote 'BO allocation size too large' message to debug onlyMichel Dänzer
These clutter up dmesg during piglit runs. Userspace generally deals gracefully with this failure. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: use a fetch function to get the edidAlex Deucher
We keep a cached version of the edid in radeon_connector which we use for determining connectedness and when to enable certain features like hdmi audio, etc. When the user uses the firmware interface to override the driver with some other edid the driver's copy is never updated. The fetch function will check if there is a user supplied edid and update the driver's copy if there is. bug: https://bugs.freedesktop.org/show_bug.cgi?id=80691 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: restructure edid fetchingAlex Deucher
Split radeon_ddc_get_modes() and move it into radeon_connectors.c since that is the only place that uses it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon/audio: break out of loops once we match connectorStefan Brüns
No need to continue with the loops once we've matched the appropriate connector. See commit 8a992ee14551eae53fd3ab6c2dc8e06ba6fff174 Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Use correct value for unknown audio/video latencyStefan Brüns
Valid values are 1 to 251 for 0 to 500 ms latency, 0 for unknown and 255 for audio/video unsupported by sink, according to HDMI 1.3 spec. Also matches Radeon HDA verb 0xf7b documentation. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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